an1750

Application Note 1750
Author: David Sorlien
ISL9110AIITAZ-EVAL1Z/ISL9110AIITNZ-EVAL1Z
Evaluation Board User Guide
Evaluation Board Features
• ISL9110A high efficiency buck-boost regulator
TABLE 2. DESCRIPTION OF CONNECTORS
CONNECTOR
DESCRIPTION
• Input voltage rating from 1.8V to 5.5V
J1
Header for connecting input power
• Resistor programmable output voltage on the
ISL9110AIITAZ-EVAL1Z evaluation board
J2
Header for connecting external load
• Fixed 3.3V output voltage on the ISL9110AIITNZ-EVAL1Z
evaluation board
• Up to 1200mA output current
TABLE 3. DESCRIPTION OF JUMPERS
JUMPER
DESCRIPTION
J3
Jumper to select EN input logic state. Set EN = VIN to
enable device, or set EN = GND to disable device.
J4
Jumper to select MODE input logic state. Set
MODE = VIN to enable auto-PFM mode, or set
MODE = GND to select forced PWM mode.
• 2.5MHz switching frequency
• Jumper selectable EN (enabled/disabled)
• Jumper selectable MODE (auto-PFM/forced-PWM)
• LED indicators for PG and BAT status outputs
To use external sync feature, remove this jumper and
apply an external clock between 2.75MHz and
3.25MHz on the MODE testpoint (TP10) or center pin
on the J10 header.
• Connectors, testpoints, and jumpers for easy evaluation
Required Equipment
• Power supply capable of delivering up to 5.5V and 3A
• Electronic load
• Multimeter to measure voltages and currents
J5
Jumper to enable PG LED. Remove this jumper when
measuring quiescent current.
J6
Jumper to enable BAT LED. Remove this jumper when
measuring quiescent current.
• Oscilloscope
Testpoints, Connectors, and
Jumpers
TABLE 1. DESCRIPTION OF TEST POINTS
Quick Setup Guide
1. Install jumpers on J5 and J6 to enable the status LEDs.
2. Install jumper on J3, shorting EN to VIN.
3. Install jumper on J4, shorting MODE to VIN.
TEST POINT(S)
DESCRIPTION
TP1
VOUT Kelvin connection for efficiency measurements
TP2
LX1 (Input side of power inductor)
TP3
PGND (Power ground)
6. Place scope probes on VOUT testpoint, and other testpoints
of interest.
TP4
LX2 (Output side of power inductor)
7. Turn on the power supply.
TP5
PVIN Kelvin connection for efficiency measurements
TP7
PG (Open drain status output)
8. Monitor the output voltage startup sequence on the scope.
The waveforms will look similar to that shown in Figure 1
and Figure 2.
TP8
BAT (Open drain status output)
TP9
EN (Enable input, drive high to enable device)
TP10
MODE/SYNC (Mode input, drive low for forced PWM,
or apply external clock between 2.75MHz and
3.25MHz for external sync)
TP11, TP13, GND (Ground)
TP14
4. Connect power supply to J1, with voltage setting between
1.8V and 5.5V.
5. Connect electronic load to J2.
9. Turn on the electronic load.
10. Measure the output voltage with the voltmeter. The voltage
should regulate within data sheet spec limits.
11. To determine efficiency, first remove jumpers J5 and J6 to
eliminate LED currents. Then measure input and output
voltages at the Kelvin testpoints TP5 and TP1 and measure
the input and output currents. Calculate efficiency based
on these measurements.
12. To test external sync, remove the jumper at J4, then apply
an external clock between 2.75MHz and 3.25MHz on the
MODE input (testpoint TP10, or the center pin of header J4).
June 8, 2012
AN1750.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Copyright Intersil Americas Inc. 2012. All Rights Reserved.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Application Note 1750
Typical Start-up Waveforms
Output Voltage Programming
The ISL9110AIITAZ-EVAL1Z evaluation board uses resistors to
program the output voltage. To change the output voltage,
resistor R2 should be removed and replaced with a resistor value
corresponding to the desired output voltage, as shown in Table 4.
A precision resistor with 1% tolerance should be used.
LX1
2V/DIV
LX2
2V/DIV
TABLE 4. OUTPUT VOLTAGE PROGRAMMING
VOUT
2V/DIV
EN
2V/DIV
400µs/DIV
VIN = 2V
VOUT = 3.3V
IOUT = 200mA
FIGURE 1. ISL9110A START-UP WITH VIN = 2V and VOUT = 3.3V
DESIRED OUTPUT VOLTAGE
(V)
R2 RESISTOR VALUE
(kΩ)
2.0
665
2.5
470
3.0
365
3.3
324
3.4
309
4.0
249
4.5
215
5.0
191
LX1
2V/DIV
LX2
2V/DIV
VOUT
2V/DIV
EN
2V/DIV
400µs/DIV
VIN = 4V
VOUT = 3.3V
IOUT = 200mA
FIGURE 2. ISL9110A START-UP WITH VIN = 4V and VOUT = 3.3V
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AN1750.1
June 8, 2012
Application Note 1750
ISL9110AIITAZ-EVAL1Z Evaluation Board Schematic
J2
VOUT
1
2
3
4
C4
56pF
R1
1.00M
HDR4
R2
324k
LX2
L1
2.2µH
VIN
1.8V TO 5.5V
LX1
TP4
J1
PVIN
1
2
3
4
C1
10µF
TP5
A4
B4
U1
ISL9110AIITAZ
VOUT
FB
VOUT
MODE
LX2
LX2
EN
A2
B2
LX1
LX1
A1
B1
PVIN
PVIN
C1
VIN
VIN
EN
C2
nBAT
PG
D1
PG
1
2
3
J3
HDR3
TP9
D3
D2
PGND
VIN
D5
nBAT
GND
GND
MODE
1
2
3
TP8
VIN
J6
C5
D4
TP7
C4
C3
B3
A3
C3
1µF
HDR4
FB
A5
B5
TP1
TP2
J4
HDR3
TP10
C2
10µF
D2
HDR2
J5
R4
1k
D1
HDR2
TP3
VOUT
3.3V
R3
1k
TP13 TP14 TP11
FIGURE 3. ISL9110AIITAZ-EVAL1Z EVALUATION BOARD SCHEMATIC
TABLE 5. ISL9110AIITAZ-EVAL1Z EVALUATION BOARD BILL OF MATERIALS
ITEM#
QTY
DESIGNATORS
PART TYPE
FOOTPRINT
1
1
U1
ISL9110AIITAZ
W4x5.20
WLCSP
Intersil ISL9110 Buck-Boost Regulator with
Adjustable Output Voltage
2
1
L1
2.2µH
4x4mm
NR4018T2R2M
3
2
C1, C2
10µF/6.3V/X5R
0805
GRM21BR71A106KE51L
4
1
C3
1µF/6.3V/X5R
0402
Capacitor, Generic
ANY
5
1
C4
56pF
0402
Capacitor, Generic
ANY
6
1
R1
1MΩ, 1%
0402
Resistor, Generic
ANY
7
1
R2
324kΩ, 1%
0402
Resistor, Generic
ANY
8
2
R3, R4
1kΩ
0603
Resistor, Generic
ANY
9
2
D1, D2
LED, RED
1.6x0.8
LED, RED, SMD
ANY
10
2
J5, J6
HDR-2
HDR-2
Vert. Pin Header, 2-Pin, 0.1” Spacing, Generic
ANY
11
2
J3, J4
HDR-3
HDR-3
Vert. Pin Header, 3-Pin, 0.1” Spacing, Generic
ANY
12
2
J1, J2
HDR-4
HDR-4
Vert. Pin Header, 4-Pin, 0.1” Spacing, Generic
ANY
13
12
TP1, TP2, TP3, TP4,
TP5, TP7, TP8, TP9,
TP10, TP11, TP13,
TP14
TEST POINT
TEST POINT
3
DESCRIPTION
Test Point, Thru-Hole, White, Mouser 534-5002
VENDORS
INTERSIL
Taiyo Yuden
Murata
KEYSTONE
AN1750.1
June 8, 2012
Application Note 1750
ISL9110AIITNZ-EVAL1Z Evaluation Board Schematic
J2
VOUT
1
2
3
4
C4
OPEN
R1
0
HDR4
R2
OPEN
LX2
L1
2.2µH
VIN
1.8V TO 5.5V
LX1
TP4
J1
PVIN
1
2
3
4
C1
10µF
TP5
A4
B4
U1
ISL9110AIITNZ
VOUT
FB
VOUT
MODE
LX2
LX2
EN
A2
B2
LX1
LX1
A1
B1
PVIN
PVIN
C1
VIN
VIN
EN
C2
nBAT
PG
D1
PG
1
2
3
J3
HDR3
TP9
D3
D2
PGND
VIN
D5
nBAT
GND
GND
MODE
1
2
3
TP8
VIN
J6
C5
D4
TP7
C4
C3
B3
A3
C3
1µF
HDR4
FB
A5
B5
TP1
TP2
J4
HDR3
TP10
C2
10µF
D2
HDR2
J5
R4
1k
D1
HDR2
TP3
VOUT
3.3V
R3
1k
TP13 TP14 TP11
FIGURE 4. ISL9110AIITNZ-EVAL1Z EVALUATION BOARD SCHEMATIC
TABLE 6. ISL9110AIITNZ-EVAL1Z EVALUATION BOARD BILL OF MATERIALS
ITEM#
QTY
DESIGNATORS
PART TYPE
FOOTPRINT
DESCRIPTION
VENDORS
1
1
U1
ISL9110AIITNZ
W4x5.20
WLCSP
Intersil ISL9110 Buck-Boost Regulator with Fixed
3.3V Output
INTERSIL
2
1
L1
2.2µH
4x4mm
NR4018T2R2M
3
2
C1, C2
10µF/6.3V/X5R
0805
GRM21BR71A106KE51L
4
1
C3
1µF/6.3V/X5R
0402
Capacitor, Generic
ANY
5
1
C4
OPEN
0402
Not installed
ANY
6
1
R1
0Ω
0402
Resistor, Generic
ANY
7
1
R2
OPEN
0402
Not installed
ANY
8
2
R3, R4
1kΩ
0603
Resistor, Generic
ANY
9
2
D1, D2
LED, RED
1.6x0.8
LED, RED, SMD
ANY
10
2
J5, J6
HDR-2
HDR-2
Vert. Pin Header, 2-Pin, 0.1” Spacing, Generic
ANY
11
2
J3, J4
HDR-3
HDR-3
Vert. Pin Header, 3-Pin, 0.1” Spacing, Generic
ANY
12
2
J1, J2
HDR-4
HDR-4
Vert. Pin Header, 4-Pin, 0.1” Spacing, Generic
ANY
13
12
TP1, TP2, TP3, TP4,
TP5, TP7, TP8, TP9,
TP10, TP11, TP13,
TP14
TEST POINT
TEST POINT
4
Test Point, Thru-Hole, White, Mouser 534-5002
Taiyo Yuden
Murata
KEYSTONE
AN1750.1
June 8, 2012
Application Note 1750
Evaluation Board Layout
FIGURE 5. ISL9110A EVALUATION TOP SILKSCREEN
FIGURE 6. ISL9110A EVALUATION BOARD TOP COPPER
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June 8, 2012
Application Note 1750
Evaluation Board Layout (Continued)
FIGURE 7. ISL9110A EVALUATION BOARD MID1 LAYER (GND)
FIGURE 8. ISL9110A EVALUATION BOARD MID2 LAYER (PVIN)
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June 8, 2012
Application Note 1750
Evaluation Board Layout (Continued)
FIGURE 9. ISL9110A EVALUATION BOARD BOTTOM LAYER (GND)
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
7
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