LTC6754 -High Speed Rail-to-Rail Input Comparator with LVDS Compatible Outputs

LTC6754
High Speed Rail-to-Rail
Input Comparator with
LVDS Compatible Outputs
Description
Features
Low Propagation Delay: 1.8ns Typ.
nn Low Overdrive Dispersion: 1ns Typ.
(10mV to 125mV Overdrive)
nn High Toggle Rate: 890Mbps Typ.
nn LVDS Compatible Output Stage
nn Rail-to-Rail Inputs Extend Beyond Both Rails
nn Low Quiescent Current: 13.4mA
nn Supply Range: 2.4V to 5.25V
nn Features within the LTC6754 Family:
nn Separate Input and Output Supplies
nn Shutdown Pin for Reduced Power
nn Output Latch and Adjustable Hysteresis
nn SC70 and 3mm × 3mm QFN Packages
The LTC®6754 is a high speed rail-to-rail comparator with
LVDS compatible outputs. The LTC6754 exhibits 1.8ns of
propagation delay, only 1ns of dispersion (10mV to 125mV
overdrive) and a toggle rate up to 890Mbps.
nn
The LTC6754 has rail-to-rail inputs, and will operate from
a 2.4V to 5.25V supply. For the QFN package, the LVDS
output is operated with a separate supply, providing isolation between input and output circuitry, and allowing for
logic level translation.
In shutdown mode, power is reduced from 13.4mA to
under 1.1mA, and the comparator can wake up in 120ns.
The LTC6754 includes 4.5mV of hysteresis to minimize
instability. For the QFN package, a separate pin is available
to set the hysteresis from 0mV (off) up to 40mV. The QFN
version also features output latching to provide the ability
to quickly capture the state of the comparator.
Applications
Clock and Data Recovery
Level Translation
nn High Speed Data Acquisition Systems
nn Window Comparators
nn High Speed Line Receivers
nn Time Domain Reflectometry
nn Time of Flight Measurements
nn Cable Drivers
nn
nn
The dispersion of only 1ns combined with excellent
propagation delay of 1.8ns makes the device an excellent choice for timing critical applications. Similarly, the
890Mbps toggle rate and low jitter of 1.5psRMS (200mVP–P,
245.76MHz input) make the LTC6754 ideally suited for
high frequency line driver and clock recovery circuits.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical Application
High Speed Differential Line Receiver and LVDS Translator
with Excellent Common Mode Rejection
SMALL DIFFERENTIAL SIGNAL WITH
LARGE COMMON MODE COMPONENT
Q–Q
VCCI
Q–Q
100mV/DIV
VCCO
+IN
–IN
+
Q
VEE
+IN, –IN
200mV/DIV
0mV
700mV
100Ω
LTC6754
–
+IN
–IN
Q
6754 T01a
20ns/DIV
6754 F16
6754f
For more information www.linear.com/LTC6754
1
LTC6754
Absolute Maximum Ratings
(Note 1)
Total Input Supply Voltage (VEE to VCCI)...................5.5V
Total Output Supply Voltage (VEE to VCCO)...............5.5V
Input Voltage
–IN, +IN, LE/HYST, SHDN........VEE – 0.3V, VCCI + 0.3V
Input Current
–IN, +IN, LE/HYST, SHDN (Note 2)................... ±10mA
Output Current(Q, Q)............................................ ±20mA
Operating Temperature Range (Note 3)... –40°C to 125°C
Specified Temperature Range (Note 4)
LTC6754I..............................................–40°C to 85°C
LTC6754H........................................... –40°C to 125°C
Storage Temperature Range................... –65°C to 125°C
Maximum Junction Temperature (Note 4)............. 150°C
Lead Temperature Soldering
(10 sec) (SC70 Only).......................................... 300°C
pin Configuration
Q
12 11 10
TOP VIEW
6Q
VCCO 1
VEE 2
5 VCCI/VCCO
VCCI 2
+IN 3
4 –IN
13
VEE
TJMAX = 150°C, θJA = 256°C/W (NOTE 3)
4
5
6
–IN
SC6 PACKAGE
6-LEAD PLASTIC SC70
NC
VEE 3
+IN
Q1
NC
Q
TOP VIEW
9
VEE
8
LE/HYST
7
SHDN
UD PACKAGE
12-LEAD (3mm × 3mm) PLASTIC QFN
TJMAX = 150°C, θJA = 68°C/W (NOTE 3)
EXPOSED PAD (PIN 13) IS VEE, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
SPECIFIED
TEMPERATURE RANGE
LTC6754ISC6#TRMPBF
LTC6754ISC6#TRPBF
LGVH
6-Lead Plastic SC-70
–40°C to 85°C
LTC6754HSC6#TRMPBF
LTC6754HSC6#TRPBF
LGVH
6-Lead Plastic SC-70
–40°C to 125°C
LTC6754IUD#PBF
LTC6754IUD#TRPBF
LGVJ
12-Lead Plastic QFN
–40°C to 85°C
LTC6754HUD#PBF
LTC6754HUD#TRPBF
LGVJ
12-Lead Plastic QFN
–40°C to 125°C
TRM = 500 pieces. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2
6754f
For more information www.linear.com/LTC6754
LTC6754
Electrical
Characteristics (VCCI = VCCO = 5.0V)
The l denotes the specifications which apply over
the specified temperature range, otherwise specifications are at TA = 25°C, LE/HYST, SHDN pins floating, VOVERDRIVE = 50mV,
–IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size, RL=100Ω , unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCCI–VEE
Input Supply Voltage (Note 5)
l
2.4
5.25
V
VCCO–VEE
Output Supply Voltage (Note 5)
l
2.4
5.25
V
VCMR
Input Voltage Range (Note 7)
l VEE – 0.2
VOS
Input Offset Voltage (Note 6)
l
–4
–8.5
VCCI + 0.1
±0.75
4
8.5
18
mV
mV
µV/ºC
4.5
mV
TCVOS
Input Offset Voltage Drift
VHYST
Input Hysteresis Voltage (Note 5)
CIN
Input Capacitance
1.1
pF
RDM
Differential Mode Resistance
55
kΩ
RCM
Common Mode Resistance
6.5
MΩ
IB
Input Bias Current
–1.8
μA
µA
µA
µA
μA
l
LE/HYST pin floating
VCM = VEE + 0.3V
l
–3.8
–4
VCM = VCCI – 0.3V
0.6
l
IOS
Input Offset Current
CMRR_LVCM
Common Mode Rejection Ratio, Low VCM
Region
Common Mode Rejection Ratio (Measured at
Extreme Ends of VCMR)
Power Supply Rejection Ratio
CMRR_FR
PSRR
l
VCM = VEE – 0.2V to VCCI – 1.5V
l
VCM = VEE – 0.2V to VCCI+0.1V
l
VCCI = VCCO Varied from 2.45V to 5.25V
l
–0.7
58
53
60
50
62
59.5
77
dB
dB
dB
dB
dB
dB
dB
76.5
80
AVOL
Open Loop Gain
VOD
Differential Output Voltage
l
260
362
420
mV
ΔVOD
Difference in VOD Between Complementary
Output States
Output Common Mode Voltage
l
–15
±5
15
mV
l
1.18
1.26
1.31
l
–10
±1.8
10
mV
20
mA
VOCM
Hysteresis Removed (Note 10)
1.5
2.5
0.7
Difference in VOD Between Complementary
Output States
Short Circuit Current, through Either Output, both
ISC_VEE
Outputs Connected to VEE
ISC_OUT_SHORT Output Current, Complementary Outputs Shorted
Input Stage Supply Current, Device On
Comparator On, Input Section Supply
IVCCI
Current
Output Stage Supply Current, Device On
Comparator On, Output Section Supply
IVCCO
Current
Total Supply Current, Device On
Comparator On, Single Supply Pin Version,
IVCC
ΔVOCM
53
l
l
2.4
l
11
l
13.4
l
tR, tF
Rise/Fall Time
20% to 80%
tPD
Propagation Delay (Note 8)
VOVERDRIVE = 50mV
5
mA
2.9
3
11.8
12.5
14.7
15.5
mA
mA
mA
mA
mA
mA
ns
2.8
2.9
0.77
1.8
V
tSKEW_RISEFALL Propagation Delay Skew, Rising to Falling Transition
40
ns
ns
ps
tSKEW_COMP
Propagation Delay Skew, Q to Q
50
ps
tOD_DISP
Overdrive Dispersion
Overdrive Varied from 10mV to 125mV
1
ns
tCM_DISP
Common Mode dispersion
VCM Varied from VEE – 0.2V to VCCI + 0.1V
200
ps
TR
Toggle Rate
VIN = 200mVP–P Sine Wave, 50% Output Swing
890
Mbps
l
6754f
For more information www.linear.com/LTC6754
3
LTC6754
Electrical
Characteristics (VCCI = VCCO = 5.0V)
The l denotes the specifications which apply
over the specified temperature range, otherwise specifications are at TA = 25°C, LE/HYST, SHDN pins floating, VOVERDRIVE = 50mV,
–IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size, RL=100Ω , unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
tJIT_RMS
RMS Jitter, Sine Wave Input
VIN = 200mVP–P
fIN = 245.76MHz, Jitter BW = 10Hz – 122.88MHz
fIN = 245.76MHz, Jitter BW = 12kHz – 20MHz
fIN = 100MHz, Jitter BW = 10Hz – 50MHz
fIN = 100MHz, Jitter BW = 12kHz – 20MHz
fIN = 61.44MHz, Jitter BW = 10Hz – 30.72MHz
fIN = 61.44MHz, Jitter BW = 12kHz – 20MHz
fIN = 10MHz, Jitter BW = 10Hz – 5MHz
MIN
TYP
MAX
UNITS
ps
ps
ps
ps
ps
ps
ps
1.53
0.7
2.2
1.34
2.93
2.37
20
Latching/Adjustable Hysteresis Characteristics
VLE/HYST
LE/HYST Pin Voltage
Open Circuit
l
1.05
1.25
1.45
RHYST
Resistor Value at LE/HYST
LE/HYST Pin Voltage < Open Circuit Value
l
11.6
14.5
17.6
VHYST_LARGE
Hysteresis Voltage
VLE/HYST = 800mV
VIL_LE
Latch Pin Voltage, Latch Guaranteed
l
l
40
V
kΩ
mV
0.4
V
70
µA
VIH_LE
Latch Pin Voltage, Hysteresis Disabled
IIH_LE
Latch Pin Current High
VLE/HYST = 1.7V
l
1.7
V
IIL_LE
Latch Pin Current Low
VLE/HYST = 0.4V
l
–59
µA
tSETUP
Latch Setup Time
2
ns
tHOLD
Latch Hold Time
–2
ns
tPL
Latch to Output Delay
3
ns
31
–75
Shutdown Characteristics
ISD_VCCI
Shutdown Mode Input Stage Supply Current
VSHDN = 0.8V
0.78
l
ISD_VCCO
Shutdown Mode Output Stage Supply Current
VSHDN = 0.8V
270
l
ISD_TOT
Shutdown Mode Total Supply Current
VSHDN = 0.8V
1.05
l
tSD
Shutdown Time
Output Hi-Z
VIH_SD
Shutdown Pin Voltage High
Part Guaranteed to be Powered On
VIL_SD
Shutdown Pin Voltage Low
Part Guaranteed to be Powered Off
tWAKEUP
Wake-Up Time from Shutdown
VOVERDRIVE = 100mV, Output Valid
4
1.07
1.14
410
430
1.48
1.57
110
l
2
mA
mA
μA
µA
mA
mA
ns
V
0.8
120
V
ns
6754f
For more information www.linear.com/LTC6754
LTC6754
Electrical Characteristics
(VCCI = VCCO = 2.5V) The l denotes the specifications which apply
over the specified temperature range, otherwise specifications are at TA = 25°C, LE/HYST, SHDN pins floating,VOVERDRIVE = 50mV,
–IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size, RL=100Ω , unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCCI – VEE
Input Supply Voltage (Note 5)
l
2.4
5.25
V
VCCO – VEE
Output Supply Voltage (Note 5)
l
2.4
5.25
V
VCMR
Input Voltage Range (Note 7)
l VEE – 0.2
VOS
Input Offset Voltage (Note 6)
l
–4.2
–7.5
VCCI + 0.1
±0.7
4.2
7.5
18
mV
mV
µV/ºC
4.9
mV
TCVOS
Input Offset Voltage Drift
VHYST
Input Hysteresis Voltage (Note 5)
CIN
Input Capacitance
1.1
pF
RDM
Differential Mode Resistance
55
kΩ
RCM
Common Mode Resistance
6.5
MΩ
IB
Input Bias Current
–1.7
µA
μA
µA
μA
μA
l
LE/HYST pin floating
VCM = VEE + 0.3V
l
–3.8
–4
VCM = VCCI – 0.3V
0.5
l
IOS
Input Offset Current
l
CMRR_LVCM Common Mode Rejection Ratio,
Low VCM Region
CMRR_FR
Common Mode Rejection Ratio (Measured at
Extreme Ends of VCMR)
PSRR
Power Supply Rejection Ratio
VCM = VEE – 0.2V to VCCI – 1.5V
l
VCM = VEE – 0.2V to VCCI+0.1V
l
VCCI = VCCO Varied from
2.45V to 5.25V
Hysteresis Removed (Note 10)
l
–0.7
55
47
55
45.7
62
59.5
1.3
2.3
0.7
75
dB
dB
dB
dB
dB
dB
dB
72
80
AVOL
Open Loop Gain
VOD
Differential Output Voltage
l
260
345
420
mV
ΔVOD
Difference in VOD Between Complementary
Output States
Output Common Mode Voltage
l
–15
±5
15
mV
l
1.18
1.25
1.31
l
–10
±1.8
10
mV
15.5
mA
VOCM
Difference in VOCM Between Complementary
Output States
Short Circuit Current, through Either Output, both
ISC_VEE
Outputs Connected to VEE
ISC_OUT_SHORT Output Current, Complementary Outputs Shorted
Input Stage Supply Current, Device On
Comparator On,
IVCCI
Input Section Supply Current
Output Stage Supply Current, Device On
Comparator On, Output Section Supply
IVCCO
Current
Total Supply Current, Device On
Comparator On, Single Supply Pin Version,
IVCC
ΔVOCM
53
l
l
2.2
l
10.4
l
12.5
l
tR, tF
Rise/Fall Time
20% to 80%
tPD
Propagation Delay (Note 8)
VOVERDRIVE = 50mV
5
mA
2.65
2.9
11.5
11.7
14.15
14.6
mA
mA
mA
mA
mA
mA
ns
2.9
3.0
0.8
2
V
tSKEW_RISEFALL Propagation Delay Skew, Rising to Falling Transition
50
ns
ns
ps
tSKEW_COMP
Propagation Delay Skew, Q to Q
40
ps
tOD_DISP
Overdrive Dispersion
Overdrive Varied from 10mV to 125mV
1.1
ns
tCM_DISP
Common Mode Dispersion
VCM Varied from VEE – 0.2V to VCCI + 0.1V
200
ps
TR
Toggle Rate
VIN = 200mVP–P Sine Wave, 50% Output Swing
800
Mbps
l
6754f
For more information www.linear.com/LTC6754
5
LTC6754
Electrical
Characteristics (VCCI = VCCO = 2.5V) The l denotes the specifications which apply
over the specified temperature range, otherwise specifications are at TA = 25°C, LE/HYST, SHDN pins floating, VOVERDRIVE = 50mV,
–IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size, RL=100Ω , unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
tJIT_RMS
RMS Jitter, Sine Wave Input
VIN = 200mVP–P
fIN = 245.76MHz, Jitter BW = 10Hz – 122.88MHz
fIN = 245.76MHz, Jitter BW = 12kHz – 20MHz
fIN = 100MHz, Jitter BW = 10Hz – 50MHz
fIN = 100MHz, Jitter BW = 12kHz – 20MHz
fIN = 61.44MHz, Jitter BW = 10Hz – 30.72MHz
fIN = 61.44MHz, Jitter BW = 12kHz – 20MHz
fIN = 10MHz, Jitter BW = 10Hz – 5MHz
TYP
MAX
UNITS
ps
ps
ps
ps
ps
ps
ps
1.6
0.73
2.2
1.36
3
2.4
19
Latching/Adjustable Hysteresis Characteristics
VLE/HYST
LE/HYST Pin Voltage
Open Circuit
l
1.05
1.25
1.45
l
11.6
14.5
17.6
RHYST
Resistor Value at LE/HYST
LE/HYST Pin Voltage < Open Circuit Value
VHYST_LARGE
Hysteresis Voltage
VLE/HYST = 800mV
VIL_LE
Latch Pin Voltage, Latch Guaranteed
l
l
43
V
kΩ
mV
0.4
V
70
µA
VIH_LE
Latch Pin Voltage, Hysteresis Disabled
IIH_LE
Latch Pin Current High
VLE/HYST = 1.7V
l
1.7
V
IIL_LE
Latch Pin Current Low
VLE/HYST = 0.4V
l
–58
µA
tSETUP
Latch Setup Time
2
ns
tHOLD
Latch Hold Time
–2
ns
tPL
Latch to Output Delay
3
ns
31
–78
Shutdown Characteristics
ISD_VCCI
Shutdown Mode Input Stage Supply Current
VSHDN = 0.8V
650
l
ISD_VCCO
Shutdown Mode Output Stage Supply Current
VSHDN = 0.8V
240
l
ISD_TOT
Shutdown Mode Total Supply Current
VSHDN = 0.8V
0.89
l
tSD
Shutdown Time
Output Hi-Z
VIH_SD
Shutdown Pin Voltage High
Part Guaranteed to be Powered On
VIL_SD
Shutdown Pin Voltage Low
Part Guaranteed to be Powered Off
tWAKEUP
Wake-Up Time from Shutdown
VOVERDRIVE = 100mV, Output Valid
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Reverse biased ESD protection exists on all input, shutdown,
latching/hysteresis and output pins. If the voltage on the input, shutdown,
or latching/hysteresis pins goes beyond either input supply, the current
should be limited to less than 10mA. This parameter is guaranteed to meet
specification through design and/or characterization. It is not production
tested.
Note 3: A heat sink may be required to keep the junction temperature
below the absolute maximum rating. This parameter is guaranteed to meet
specified performance through design and/or characterization. It is not
production tested.
Note 4: The LTC6754I is functional and guaranteed to meet specified
performance from –40 °C to 85 °C. The LTC6754H is functional and
guaranteed to meet specified performance from –40 °C to 125 °C.
6
880
970
370
380
1.25
1.35
110
l
2
μA
µA
μA
µA
mA
mA
ns
V
0.8
120
V
ns
Note 5: Supply voltage range is guaranteed by the PSRR test.
Note 6: Both hysteresis and offset are measured by determining positive
and negative trip points (input values needed to change the output in the
opposite direction). Hysteresis is defined as the difference of the two trip
points and offset as the average of the two trip points.
Note 7: Guaranteed by CMRR spec.
Note 8: Propagation delays are measured with a step size of 150mV.
Note 9: Latch setup time is defined as the minimum time before the
LE/HYST pin is asserted low for an input signal change to be acquired and
held at the output. Latch hold time is defined as the minimum time before
an input signal change for a high to low transition on the LE/HYST pin to
prevent the output from changing. Latch enable pulse width is defined as
the minimum time for the LE/HYST pin to be held high for an input change
to affect the output. See Figure 7 for a graphical definition of these terms.
Note 10: The devices have effectively infinite gain when hysteresis is
enabled.
6754f
For more information www.linear.com/LTC6754
LTC6754
Typical Performance Characteristics
VOVERDRIVE = 50mV, VCM = 300mV, unless otherwise noted.
5.0
HYSTERESIS
OFFSET, HYSTERESIS (mV)
OFFSET, HYSTERESIS (mV)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
7
4.0
6
3.5
HYSTERESIS
3.0
2.5
2.0
1.5
1.0
OFFSET
1.0
OFFSET
0.5
0.5
0
2.4000
3.1125
3.8250
4.5375
TOTAL SUPPLY VOLTAGE (V)
0
2.4000
5.2500
3.1125
3.8250
4.5375
TOTAL SUPPLY VOLTAGE (V)
6754 G01
8
OFFSET, HYSTERESIS (mV)
OFFSET, HYSTERESIS (mV)
4
3
2
OFFSET
1
0
–1
–2
–55 –35 –15
3
2
1
5 25 45 65 85 105 125
TEMPERATURE (°C)
3.0
2.0
1.0
OFFSET
0
–1.0
–1.5
–2.0
–2.5
–3.0
–1.0
–3.5
–2.0
–0.2 0.3 0.9 1.4 1.9 2.5 3.0 3.5 4.0 4.6 5.1
INPUT COMMON MODE VOLTAGE (V)
–4.0
–5.4 –4.3 –3.2 –2.2 –1.1 0.0 1.1 2.2 3.2 4.3 5.4
INPUT DIFFERENTIAL VOLTAGE (V)
6754 G06
6754 G05
Output Common Mode Voltage
vs Temperature
1.276
1.2765
–2.5
–3.0
–3.5
–4.0
–0.2 0.3 0.9 1.4 1.9 2.5 3.0 3.5 4.0 4.6 5.1
INPUT DIFFERENTIAL VOLTAGE (V)
6754 G07
OUTPUT COMMON MODE VOLTAGE (V)
0.5
OUTPUT COMMON MODE VOLTAGE (V)
1.2800
–2.0
+IN
–0.5
1.280
–1.5
–IN
0
1.0
–1.0
Input Bias Current vs Differential
Voltage, VCC = 5.0V
0.5
Output Common Mode Voltage vs
Supply Voltage
–0.5
5 25 45 65 85 105 125
TEMPERATURE (°C)
6754 G03
1.0
4.0
Input Bias Current vs Common
Mode Voltage
0
OFFSET
0
–2
–55 –35 –15
5.2500
HYSTERESIS
6754 G04
INPUT BIAS CURRENT (µA)
4
–1
6.0
5.0
HYSTERESIS
HYSTERESIS
5
Input Offset, Hysteresis vs
Input Common Mode Voltage
7
5
Input Offset and Hysteresis vs
Temperature, VCCI = VCCO = 5.0V
6754 G02
Input Offset and Hysteresis vs
Temperature, VCCI = VCCO = 2.5V
6
8
4.5
OFFSET, HYSTERESIS (mV)
5.5
Input Offset and Hysteresis vs
Supply Voltage, VCM = VCCI
CC – 0.3V
BIAS CURRENT (µA)
6.0
Input Offset and Hysteresis vs
Supply Voltage, VCM = 0.3V
VCCI = VCCO = 5.0V, RL = 100Ω,
1.272
1.268
1.264
1.260
1.256
1.252
1.248
1.244
1.240
2.4000
3.1125
3.8250
4.5375
TOTAL SUPPLY VOLTAGE (V)
5.2500
6754 G08
1.2730
1.2695
1.2660
1.2625
VCCI = VCCO = 5.0V
1.2590
1.2555
VCCI = VCCO = 2.5V
1.2520
1.2485
1.2450
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
6754 G09
6754f
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7
LTC6754
Typical
Performance Characteristics
VOVERDRIVE = 50mV, VCM = 300mV, unless otherwise noted.
Output Differential Voltage vs
Supply Voltage
Output Differential Voltage
vs Temperature
361
358
355
352
349
346
343
3.1125
3.8250
4.5375
SUPPLY VOLTAGE (V)
5.2500
365
VCCI = VCCO = 5V
360
355
350
VCCI = VCCO = 2.5V
345
340
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
6754 G10
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
IVCCI
3.1125
3.8250
4.5375
SUPPLY VOLTAGE (V)
5.2500
5 25 45 65 85 105 125
TEMPERATURE (°C)
14
13
12
11
10
9
VCCI = VCCO = 5.0V
8
7
6
5
4
3
2
VCCI = VCCO = 2.5V
1
0
–0.3 0.3 0.8 1.4 1.9 2.5 3.1 3.6 4.2 4.7 5.3
SHDN PIN VOLTAGE (V)
6754 G15
6754 G14
Input Hysteresis vs
LE/HYST Pin Voltage
LE/HYST Pin I–V Characteristics
45
180
40
150
35
120
LE/HYST PIN CURRENT (µA)
INPUT HYSTERESIS (mV)
SHDN Pin I–V Characteristics
6754 G16
IVCCI
Total Supply Current vs
SHDN Pin Voltage
14
13
ITOTAL
12
11
10
IVCCO
9
8
7
6
5
4
IVCCI
3
2
1
–0.2 0.3 0.9 1.4 1.9 2.5 3.0 3.5 4.0 4.6 5.1
INPUT COMMON MODE VOLTAGE (V)
6754 G13
1
0 VCCI = VCCO = 2.5V
–1
–2
–3
–4
–5
–6
–7
–8
–9
VCCI = VCCO = 5.0V
–10
–11
–12
–13
–14
–15
–0.3 0.3 0.8 1.4 1.9 2.5 3.1 3.6 4.2 4.7 5.3
SHDN PIN VOLTAGE (V)
IVCCO
6754 G12
Supply Current vs Common Mode
Voltage
ITOTAL
IVCCO
14
13
ITOTAL
12
11
10
9
8
7
6
5
4
3
2
1
–55 –35 –15
6754 G11
Supply Current vs Supply Voltage
14
13
12
11
10
9
8
7
6
5
4
3
2
1
2.4000
SUPPLY CURRENT (mA)
364
TOTAL SUPPLY CURRENT (mA)
367
340
2.4000
SHDN PIN CURRENT (µA)
Supply Current vs Temperature
370
OUTPUT DIFFERENTIAL VOLTAGE (mV)
OUTPUT DIFFERENTIAL VOLTAGE (mV)
370
8
VCCI = VCCO = 5.0V, RL = 100Ω,
30
25
20
15
10
5
0
0.75
90
VCCI = VCCO = 2.5V
60
30
VCCI = VCCO = 5.0V
0
–30
–60
–90
1
1.25
1.50
1.75
LE/HYST PIN VOLTAGE (V)
2
6754 G17
–120
–0.3 0.3 0.8 1.4 1.9 2.5 3.1 3.6 4.2 4.7 5.3
LE/HYST PIN VOLTAGE (V)
6754 G18
6754f
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LTC6754
Typical Performance Characteristics
VCCI = VCCO = 5.0V, RL = 100Ω,
VOVERDRIVE = 50mV, VCM = 300mV, transient input voltage 50MHz, 150mVP-P square wave unless otherwise noted.
Propagation Delay vs
Input Overdrive
PROPAGATION DELAY (ns)
2.9
2.7
2.5
2.3
2.1
1.9
2.10
2.05
1.95
1.90
1.85
1.80
1.75
1.70
tPD, OUTPUT RISING (tPDLH)
1.7
1.65
1.5
1.60
–0.2 0.3 0.9 1.4 1.9 2.5 3.0 3.5 4.0 4.6 5.1
INPUT COMMON MODE VOLTAGE (V)
5 15 25 35 45 55 65 75 85 95 105115125
INPUT OVERDRIVE (mV)
2.4
2.1
2.0
1.9
1.375
1.250 2.5V SUPPLY
1.125
0.875
0.750
5
10
15
20
LOAD CAPACITANCE AT EACH OUTPUT (pF)
600
540
480
5V SUPPLY, VOD
SWINGS TO > ±247mV
2.5V SUPPLY, VOD
SWINGS TO > ±247mV
420
360
300
18
0
16
RMS OUTPUT JITTER (ps)
660
500
400
300
0
100
0.01
5
10
15
20
LOAD CAPACITANCE AT EACH OUTPUT (pF)
Output Jitter vs Input Amplitude
(Sinusoidal Input)
200mVP–P SINUSOIDAL INPUT
5V SUPPLY, 50% OUTPUT SWING
2.5V SUPPLY, 50% OUTPUT SWING
720
600
6754 G23
Toggle Rate vs Capacitive Load
780
700
200
5 V SUPPLY
6754 G22
840
5 25 45 65 85 105 125
TEMPERATURE (°C)
800
1.500
1.7
900
1.7
900
1.625
1.000
0
1.8
Toggle Rate vs Input Amplitude
(Sinusoidal Input)
1.750
1.8
1.6
1.9
Rise/Fall Times vs Capacitive Load
1.875
2.2
2.0
6754 G21
2.000
2.3
2.1
6754 G20
RISE/FALL TIMES (ns)
2.5
2.2
1.5
–55 –35 –15
2.125
tPDLH, 5V SUPPLY
tPDHL, 5V SUPPLY
tPDLH, 2.5V SUPPLY
tPDHL, 2.5V SUPPLY
2.6
2.3
1.6
TOGGLE RATE (Mbps)
2.7
tPDLH, 5V SUPPLY
tPDHL, 5V SUPPLY
tPDLH, 2.5V SUPPLY
tPDHL, 2.5V SUPPLY
2.4
2.00
Propagation Delay vs Capacitive Load
PROPAGATION DELAY (ns)
2.5
tPD, OUTPUT FALLING (tPDHL)
6754 G19
TOGGLE RATE (Mbps)
Propagation Delay vs
Temperature
PROPAGATION DELAY (ns)
tPDLH, 5V SUPPLY
tPDHL, 5V SUPPLY
tPDLH, 2.5V SUPPLY
tPDHL, 2.5V SUPPLY
PROPAGATION DELAY (ns)
3.1
Propagation Delay vs Common
Mode Voltage
14
0.1
INPUT AMPLITUDE (VP–P)
1
6754 G24
5V SUPPLY, 50% OUTPUT SWING
5V SUPPLY VOD SWINGS TO > ±247mV
2.5V SUPPLY, 50% OUTPUT SWING
2.5V SUPPLY, VOD SWINGS TO > ±247mV
Differential Output Toggle Waveform
f = 200MHz
JITTER BW = 10 Hz TO fIN/2
fIN = 245.76 MHz
fIN = 100 MHz
12
10
100mV/DIV
8
6
4
2
5
10
15
20
LOAD CAPACITANCE AT EACH OUTPUT (pF)
6754 G25
0
0 100 200 300 400 500 600 700 800 900 1000
INPUT AMPLITUDE (mVP–P)
1ns/DIV
6754 G27
6754 G26
6754f
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9
LTC6754
Pin Functions
(SC70/QFN)
+IN (Pin 3/Pin 4): Positive Input of the Comparator.
The voltage range of this pin can go from VEE (–0.2V)
to VCCI (+0.1V).
SHDN (Pin 7) UD Only: Active Low Comparator Shutdown, threshold is 0.8V above VEE. If left unconnected,
the comparator will be fully powered up.
–IN (Pin 4/Pin 5): Negative Input of the Comparator.
The voltage range of this pin can go from VEE (–0.2V)
to VCCI (+0.1V).
LE/HYST (Pin 8) UD Only: This pin allows the user to
adjust the comparator’s hysteresis as well as latch the
output if the pin voltage is pulled to within 400mV above
VEE. Hysteresis can be increased or disabled by voltage,
current or a resistor to VEE. Leaving the pin unconnected
results in a typical hysteresis of 4.5mV.
VCCI (Pin 5/Pin 2): Positive Supply Voltage for the Input
Stage. The voltage between VCCI and VEE should be between 2.4V and 5.25V. This pin is combined with VCCO in
the SC70 package.
VCCO (Pin 5/Pin 1): Positive Supply Voltage for the LVDS
Output Stage. See the section High Speed Board Design
Techniques for proper power supply layout and bypassing.
The voltage between VCCO and VEE should be between
2.4V and 5.25V.This pin is combined with VCCI in the
SC70 package.
VEE (Pin 2/Pins 3, 9): Negative Power Supply, normally
tied to ground. This can be tied to a voltage other than
ground as long as the constraints for total supply voltage
relative to VCCI/VCCO are maintained.
Q (Pin 1/Pin 12): Positive Comparator Output. When the comparator outputs are differentially loaded with a 100Ω resistor,
Q swings to VOCM + VOD / 2 when +IN > –IN and
VOCM – VOD / 2 when +IN < –IN, where VOCM and VOD are
typically 1.26V and 360mV respectively for a supply of 5V.
Q (Pin 6/Pin 10): Negative Comparator Output. When the comparator outputs are differentially loaded with a 100Ω resistor,​
Q swings to VOCM + VOD / 2 when +IN < –IN and
VOCM – VOD / 2 when +IN > –IN, where VOCM and VOD are
typically 1.26V and 360mV respectively for a supply of 5V.
Block Diagram
HYSTERESIS STAGE
OUTPUT CURRENT
DRIVER STAGE
VEE
+
+IN
–
–IN
+
INPUT
STAGE
–
+
–
VCCI
VEE
LE/HYST PIN INTERFACE
1.25V
VEE
Q+Q
2
VEE
Figure 1.
For more information www.linear.com/LTC6754
VEE
VEE
COMMON
MODE
DETECTOR
ERROR
AMPLIFIER
6754 BD
+
–
VEE
10
Q
14.5k
LE/HYST
SHDN
VCCO
I = 3.6mA, +IN < –IN
I = –3.6mA, +IN > –IN
GAIN
STAGE
VCCI
VEE
350k
VCCO
Q
+
+
VEE
VCCI
VCCO
+
VCCI
–
VCCI
1.26V
VEE
6754f
LTC6754
Applications Information
Circuit Description
There are no restrictions regarding the sequence in which
the positive or negative supplies are applied as long as the
absolute maximum ratings are not violated.
The block diagram of the LTC6754 is shown in Figure 1.
There are differential inputs (+IN, –IN), a negative power
supply (VEE), two positive supply pins: VCCI for the input
stage and VCCO for the output stage, two output pins (Q and
Q), a pin for latching and adjusting hysteresis (LE/HYST),
and a pin to put the device in a low power mode (SHDN).
The signal path consists of a rail-to-rail input stage, an
intermediate gain stage and an output driver stage to an
output stage that sources or sinks 3.6mA between the two
output pins, depending on the polarity of the differential
input (+IN – –IN). The output stage also has a common
mode feedback network that keeps the average of Q and
Q approximately 1.26V. A Latching/Hysteresis interface
block allows the user to latch the output state and/or
remove or adjust the comparator input hysteresis. All of
the internal signal paths make use of low voltage swings
for high speed at low power.
Input Voltage Range and Offset
The LTC6754 family uses a rail-to-rail input stage that
consists of a PNP pair and an NPN pair that are active
over different input common mode ranges. The PNP pair
is active for inputs between VEE – 0.2V and approximately
VCCI – 1.5V (low common mode region of operation).
The NPN pair is active for inputs between approximately
VCCI – 1V and VCCI + 0.1V (high common mode region of
operation). Partial activation of both pairs occurs when
one input is in the low common mode region of operation
and the other input is in the high common mode region
of operation, or either of the inputs is between approximately VCCI – 1.5V and VCCI – 1V (transition region). The
device has small, trimmed offsets as long as both inputs
are completely in the low or high common mode region
of operation. In the transition region, the offset voltage
may increase. Applications that require good DC precision
should avoid the transition region.
Power Supply Configurations
The LTC6754UD (QFN Package) has separate positive
supply pins for the input and output stages that allow for
better isolation between the sensitive inputs and circuitry
connected to the output load by removing a direct path for
noise coupling through the positive supply. This feature
also allows the user the ability to decouple input signal
range from output stage power consumption (for example
by using a 5.25V input supply to allow for > 5V common
mode input range and a 2.4V output supply to minimize
total power consumption). Figure 2 shows a few possible
configurations.
Input Bias Current
When both inputs are in the low common mode region,
the input bias current is negative, with current flowing
out of the input pins. When both inputs are in the high
common mode region, the input bias current is positive,
with current flowing into the input pins. The input stage
has been designed to accommodate large differential input
voltages without large increases in input bias current. With
one input at the positive input supply rail and the other
input at the negative supply rail, the magnitude of the
input bias current at either pin is typically less than 3.5μA.
For proper and reliable operation both supply pins should
be between 2.4V and 5.25V above the negative supply pin.
3V
3V
VCCI
+IN
+
VCCO
5V 2.4V
VCCI
Q
+IN
+
VCCO
3.3V 5V
VCCI
Q
100Ω
–IN
–
Q
VEE
0V
(a) SINGLE SUPPLY
+IN
+
VCCO
Q
100Ω
–IN
–
Q
100Ω
–IN
VEE
Q
VEE
0V
(b) OUTPUT SUPPLY < INPUT SUPPLY
–
0V
(c) OUTPUT SUPPLY > INPUT SUPPLY
6754 F02
Figure 2. Typical Power Supply Configurations Applicable to the LTC6754UD (QFN Package)
For more information www.linear.com/LTC6754
6754f
11
LTC6754
Applications Information
Input Protection
The input stage is protected against damage from conditions where the voltage on either pin exceeds the supply
voltage (VEE to VCCI) without external protection. External
input protection circuitry is only needed if input currents
can exceed the absolute maximum rating. For example,
if an input is taken beyond 300mV of either the positive
or negative supply, an internal ESD protection diode will
conduct and an external series resistor should be used to
limit the current to less than 10mA.
Outputs
The LTC6754 has been designed for driving a 100Ω load
connected between the output pins to standard LVDS
levels, with a differential output voltage of 360mV and a
common mode voltage of 1.26V, as described in the Circuit
Description Section. See the section on High Speed Board
Design Techniques for information on connecting the load
to the output pins. The outputs should not be used as
CMOS or TTL level outputs, and should not be used for
sourcing or sinking excessive load currents.
ESD
In some cases, additional noise immunity is required
above what is provided by the nominal 4.5mV hysteresis.
Conversely, when processing small or fast differential
signals, hysteresis may need to be eliminated.
VOUT
VOH
There are additional clamps between the positive and
negative supplies that further protect the device during
ESD strikes. Hot-plugging of the device into a powered
socket is not recommended since this can trigger the clamp
resulting in large currents flowing between the supply pins.
Hysteresis
Comparators have very high open-loop gain. With slow
input signals that are close to each other, input noise can
cause the output voltage to switch randomly. Hysteresis
is positive feedback that increases the trip point in the
direction of the input signal transition when the output
switches. This pulls the inputs away from each other, and
FOR VTRIP+ = 3mV,
VTRIP– = –2mV,
VOS = 0.5mV,
VHYST = 5mV
VHYST
(= VTRIP+ – VTRIP–)
VOL
∆VIN = VIN+ – VIN–
0
The LTC6754 has reverse-biased ESD protection diodes
on pins as shown in Figure 1.
12
prevents continuous switching back and forth. The addition of positive feedback also has the effect of making the
small signal gain infinite around the trip points. Hysteresis
is designed into most comparators and the LTC6754 has
adjustable hysteresis with a default hysteresis of 4.5mV.
The input-output transfer characteristic is illustrated in
Figure 3 showing the definitions of VOS and HYST based
upon the two measurable trip points.
VTRIP–
VOS
VTRIP+
++V
–
V
TRIP
VOS = TRIP
2
6754 F03
Figure 3.
The LTC6754UD (QFN package) provides a hysteresis
pin, LE/HYST, that can be used to increase the internal
hysteresis, completely remove it, or enable the output
to latch. The internal hysteresis is disabled when the LE/
HYST pin voltage is above 1.7V. Although eliminating
hysteresis does reduce the voltage gain of the comparator to a finite value, in many cases it will be high enough
(typically 450V/V) to amplify small input signals to valid
LVDS levels. The output will latch when the LE/HYST pin
voltage is below 0.4V. The internal hysteresis will increase
as the voltage of the pin is adjusted downward from its
default open circuit value of 1.25V to 800mV.
6754f
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LTC6754
Applications Information
The LE/HYST pin can be modeled as a 1.25V voltage source
in series with a 15kΩ resistor. The simplest method to increase the internal hysteresis is to connect a single resistor
between the LE/HYST pin and VEE to adjust hysteresis as
shown in Figure 4. Figure 5 shows how hysteresis typically
varies with the value of the resistor.
+IN
–IN
VCCI
+
VCCO
–
LE/HYST
Q
Q
VEE
R
6754 F04
Figure 4. Adjusting Hysteresis Using an External
Resistor at the LE/HYST Pin
45
HYSTERESIS (mV)
35
30
25
20
15
10
5
0
VOS _ FB ≈
VREFR1+ VCMR2
+ VOS
R1+ R2
VHYST _ FB ≈
VODR2
+V
R1+ R2 HYST
VOS_FB and VHYST_FB denote the values of offset and
hysteresis with positive feedback present. VHYST denotes
the hysteresis of the device without positive feedback.
VOCM and VOD are defined in the Electrical Characteristics
Tables. Additional inaccuracies are introduced by ΔVOD
and ΔVOCM, which are typically less than 5mV and 1.8mV,
respectively. They typically will introduce only a few mV
of error, which may be acceptable for large hysteresis
settings in many applications.
In order to ensure that VOD does not deviate too much from
its value without positive feedback, R1 and R2 should be
chosen such that the current through them is much less
than 3.5mA by at least an order of magnitude. Extremely
high resistance values however can degrade transient
performance because of the phase shift caused by the
resistors and device input capacitance.
VCC = 5V
CONTROL RESISTOR CONNECTED
BETWEEN LE/HYST AND VEE
40
The offset and hysteresis become:
25 75 125 175 225 275 325 375 425 475
CONTROL RESISTANCE (kΩ)
6754 F05
Figure 5. Hysteresis vs Control Resistance
For VREF = 0V, VEE = 0V, an increase in hysteresis of approximately 100mV can be obtained with R1 = 7.5kΩ and
R2 = 3.01kΩ, assuming VOD = 350mV and VOCM = 1.25V.
Offset induced is approximately 350mV. Similarly for
VREF = 1.25V, R2 = 5.9kΩ, R1 = 3.01kΩ, additional hysteresis of approximately 230mV can be obtained with an
offset of approximately 1.25V.
Alternatively, additional hysteresis can be added by using
positive feedback as shown in Figure 6.
SIGNAL
+
Q
100Ω
–
VREF
R2
Q
R1
6754 F06
Figure 6. Additional Hysteresis Using positive Feedback
6754f
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13
LTC6754
Applications Information
Latching
The internal latch of the LTC6754UD (QFN package) retains
the output state when the LE/HYST pin is taken to less
than 400mV above the negative supply.
Figures 7a to 7e illustrate the latch timing definitions. The
latch setup time is defined as the time for which the input
should be stable before the latch pin is asserted low to
ensure that the correct state will be held at the output. The
latch hold time is the interval after which the latch pin is
asserted in which the input signal must remain stable for
the output to be the correct state at the time latch was
asserted. The latch propagation delay (tPL) is the time
taken for the output to return to input control after the
latch pin is released. Latching is disabled if the LE/HYST
pin is left floating.
LE/HYST
t < tHOLD
+IN – –IN
tPD
Q–Q
6754 F07c
Figure 7c. Input State Not Held Long Enough,
Wrong Output State Latched
LE/HYST
t > tSETUP
t > tHOLD
+IN – –IN
LE/HYST
tPD
Q–Q
t > tSETUP
6754 F07d
Figure 7d. Short Input Pulse Properly Captured and Latched
+IN – –IN
Q–Q
tPD
6754 F07a
LE/HYST
Figure 7a. Input State Change Properly Latched
tPL
+IN – –IN
LE/HYST
Q–Q
6754 F07e
t < tSETUP
Figure 7e. Latched Output Disabled
+IN – –IN
Q–Q
6754 F07b
Figure 7b. Input State Change Setup Time Too Short
14
6754f
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LTC6754
Applications Information
Shutdown
The LTC6754UD (QFN package) has a shutdown pin (SHDN,
active low) that can reduce the total supply current to a
typical value of only 1.05mA. When the part is in shutdown, the outputs are placed in a high impedance state.
The shutdown pin needs to be taken to within 800mV of
the negative supply for the part to shut down. When left
floating, the shutdown pin is internally pulled towards the
positive supply and comparators remain fully biased on.
Dispersion
Dispersion is defined as the change in propagation delay
for different input overdrive or common mode conditions.
It becomes very crucial in timing sensitive applications.
Overdrive dispersion from 10mV overdrive to 125mV
overdrive (150mV total step size) is typically 1ns. The
graph titled Propagation Delay vs Common Mode voltage shows the dispersion due to shifts in input common
mode voltage.
pins (Q and Q) if possible. Surface mounted resistors as
opposed to leaded resistors are preferable due to lower
parasitic inductances and capacitances. In many situations,
however, it may not be possible to keep the LTC6754 close
to the LVDS receiver. In such situations, 50Ω transmission
lines should be used to route the outputs of the LTC6754 to
the 100Ω receiver as shown in Figure 8. Since the outputs
of the LTC6754 are fully differential in nature, each output
sees a 50Ω load at the receiver. Using 50Ω characteristic
impedance transmission lines minimizes reflections from
the load and helps to maintain signal integrity. It is crucial,
however, that the traces on both outputs be symmetrical,
otherwise reflections may occur, since the broadband
impedance seen by each single ended output would then
deviate from 50Ω.
+
Q
LTC6754
–
Z = 50Ω
Z = 50Ω
100Ω
Q
6754 F08
Jitter
The LTC6754 has been designed for low phase noise and
jitter. This allows it to be used in applications where high
frequency low amplitude sine waves need to be converted
to full LVDS level outputs with minimal additive jitter. The
graph titled Output Jitter vs Input Amplitude demonstrates
the additive jitter of the LTC6754 for different amplitudes
of a sinusoidal input. Refer to the Electrical Characteristics
Table to see how jitter varies with signal frequency.
High Speed Board Design Techniques
In order to obtain optimal performance from the LTC6754,
certain guidelines regarding signal routing and power supply bypassing should be carefully followed. If implemented
properly, output signal integrity can be maintained, oscillations can be eliminated and electromagnetic interference
due to fast switching at the outputs can be minimized.
The LTC6754 has been designed to drive LVDS loads. LVDS
receivers are terminated with 100Ω loads connected differentially to the outputs of the transmitter. In order to obtain
the fastest performance out of the LTC6754, the 100Ω load
should be connected directly across the LTC6754’s output
Figure 8. Routing LTC6754 Outputs to a 100Ω LVDS Receiver
Asymmetrical routing on the outputs should also be
avoided as this reduces the extent to which EMI induced
by the positive and negative outputs cancel each other.
Additional improvements in EMI can be obtained by shielding the output traces with a low impedance ground plane
Parasitic feedback between +IN and Q on one hand, and
between –IN and Q on the other, should be minimized to
avoid oscillations. If the inputs and complementary outputs
can’t be placed away from each other, a ground trace as
a shield should be used to isolate them.
The positive supply pins should be adequately bypassed
to the VEE pin to minimize transients on the supply. Low
ESR and ESL capacitors are required due to the high speed
nature of the device.
Even a few nanohenries of parasitic trace inductance in
series with the supply bypassing can cause several hundred
millivolts of disturbance on the supply pins during output
transitions, especially if the supply is used to power up
other devices that are also switching. A 2.2μF capacitor
6754f
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15
LTC6754
Applications Information
in parallel with multiple low ESL, low ESR 100nF capacitors connected as close to the supply pins as possible
to minimize trace impedance is recommended. In many
applications the VEE pin will be connected to ground. In
applications where the VEE pin is not connected to ground,
the positive supplies should still be bypassed to VEE. The
VEE pin should also then be bypassed to a ground plane
with a 2.2μF capacitor in parallel with low ESL, low ESR
100nF capacitors if possible.
For devices with separate positive input and output supplies,
bypass capacitors should be placed from each positive
supply to VEE. Capacitors should NOT be placed between
the two positive supplies; otherwise disturbances due to
output switching can couple back to the inputs.
When the input slew rate is small, sustained oscillations
can occur at the output pin while the input is transitioning
due to even one millivolt of ground bounce. For applications where the input slew rate is low, internal hysteresis
should not be removed by taking the LE/HYST pin high,
as the addition of hysteresis makes the comparators more
immune to disturbances such as ground bounce. Increasing hysteresis by adjusting the LE/HYST pin voltage or by
adding positive feedback as discussed in the section on
hysteresis can further improve noise immunity. When adding positive feedback, surface mounted resistors should
be used for R1 and R2 in Figure 6. The resistors should
be as close to the device as possible.
Typical Applications
High Speed Clock Recovery and Level Translation
Circuit
High speed comparators are often used in digital systems
to recover distorted clock waveforms. The LTC6754 can be
used to recover a distorted TTL clock signal, and translate
it into a signal suitable for driving an LVDS receiver.
In this application, an input clock signal is required to drive
an LVDS receiver. If the input signal gets distorted and
its amplitude severely reduced due to stray capacitance,
stray inductance or due to reflections on the transmission
line, the LTC6754 can be used to convert it into a full scale
LVDS signal that can drive the receiver.
Figure 10 shows the input and output waveforms of
the LTC6754, used to recover a 400mVP–P 340MHz
(680Mbps) corrupted clock signal, into a full scale LVDS
output signal. AC-coupling could have been used at the
input of the comparator, however to preserve input duty
cycle information DC-coupling may be preferable, and
that is where having a wide input common mode range
is an advantage. The input to output delay on the graph
is larger than the actual propagation delay. The additional
delay is due to the measurement cables.
Q OUTPUT
VEE + 3.3V
VCCI
340MHz
CLOCK INPUT
+
100mV/DIV
VOCM = 1.25V
VCCO
Q OUTPUT
Q
LTC6754
LTC6754
VREF = 200mV
–
100Ω
Q
VEE
1ns/DIV
6754 F09
Figure 9. Corrupted Clock Recovery to LVDS Translator Circuit.
16
INPUT
200mV/DIV
0V
6754 F10
Figure 10. LVDS Output at 340MHz
6754f
For more information www.linear.com/LTC6754
LTC6754
Typical Applications
Optical Receiver Circuit
Figure 12 shows the output of the LTC6268-10 driving
the +IN pin of the LTC6754 and the LTC6754 outputs. The
photodiode is being driven by a pulsed laser.
The LTC6754, along with a high speed high performance
FET input operational amplifier like the LTC6268-10, can be
used to implement an optical receiver as shown in Figure 11.
CF
0.05pF
ACCY-P 04021JR05PBS
Q
LTC6754
OUTPUTS
200mV/DIV Q
14k
5V
2.5pF
LASER AVALANCHE
SOURCE PHOTODIODE
10nF
–
49.9Ω INPUT
LTC6268-10
+ SHDN
VREF1 = 1V
CD
3.3nF
630V
GRM31BR72J332KW01L
LTC6754
POSITIVE INPUT
500mV/DIV
5V
1nF
+
VCCI
1nF
VCCO
VREF2 = 1.5V
–
V–
LE/HYST
SHDN
VEE
5ns/DIV
6754 F12
Figure 12. Optical Receiver with LVDS Output
Q
LTC6754
1k
10nF
100Ω
Q
6754 F11
HIGH VOLTAGE
REGULATOR
Figure 11. Optical Receiver Circuit
High Performance Sine Wave to LVDS Converter with
Low Phase Shift over Amplitude
VCCI = 2.7V
VCCO = 2.7V
SINE WAVE
INPUT
+IN
50Ω
–IN
+
Q
LTC6754
–
100Ω
Q
VEE = 0.3V
6754 F13
Figure 13. High Performance Sine Wave to LVDS Converter
shows a plot of the phase difference between the output and
input, normalized to the phase difference for an 800mVP-P
signal, versus input amplitude. The phase difference across
a 16.47dB span (120mVP-P to 800mVP-P) is only 3.06°.
NORMALIZED PHASE DIFFERENCE, INPUT TO Q – Q(°)
The LTC6754 can be used to convert low level sine waves
to full scale LVDS signals as in Figure 13. The amplitude of
the incoming sinusoidal signal was varied from 100mVP-P
to 800mVP-P, with the frequency being 50MHz. Figure 14
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0
–0.50
100 170 240 310 380 450 520 590 660 730 800
INPUT AMPLITUDE (mVP–P)
6754 F14
Figure 14. Phase Difference Between the Output and Input
6754f
For more information www.linear.com/LTC6754
17
LTC6754
Typical Applications
Common Mode Rejecting Line Receiver
Differential electrical signals being transmitted over long
cables are often attenuated. Electrical noise on the cables
can take the form of common mode signals.
The LTC6754 comparators can be used to retrieve attenuated differential signals that have been corrupted by high
frequency common mode noise, as shown in Figure 15.
SMALL DIFFERENTIAL SIGNAL WITH
LARGE COMMON MODE COMPONENT
Figure 16 shows the inputs and outputs of an LTC6754
retrieving a 300MHz, 140mVP–P differential input signal
that has 1.3V of random, common mode noise superimposed on it. The supply used was 3.0V (VCCI and VCCO).
A small amount of modulation is seen at the output due
to a small amount of differential modulation at the inputs,
which causes cycle to cycle variations in propagation delay.
Q–Q
100mV/DIV
VCCO
+IN
–IN
+IN
–IN
Q–Q
VCCI
+
+IN, –IN
200mV/DIV
Q
0mV
100Ω
LTC6754
–
700mV
Q
VEE
6754 T01a
6754 F16
20ns/DIV
Figure 15. Common Mode Rejecting Line Receiver
Figure 16.
Logic Clock Source to LVDS Cable Driver and Receiver
Figure 17 shows a 250MHz 1.8V logic clock signal being
driven across 8 feet of differential Cat6 cable to generate
a 250MHz LVDS clock signal at the receiver end.
250MHz
1.8V
CLOCK
SOURCE
Both the cable driver and LVDS receiver are implemented
using LTC6754's. Figure 18 shows the input clock signal
to the cable driver and the outputs of the receiver.
3V
DRIVER
INPUT
49.9Ω
49.9Ω
+IN
49.9Ω
VREF –IN
= 450mV
+
3V
VCCI
VCCO
LTC6754
(DRIVER)
–
+IN
Q
VEE
RJ45
CAT6 CABLE 8ft
RJ45
Q
100Ω
–IN
+
VCCI
VCCO
Q
LTC6754
(RECEIVER)
–
VEE
6754 F11
100Ω
Q
6754 F11
Figure 17. Logic Clock Source to LVDS Cable Driver and Receiver
Q
RECEIVER OUTPUTS
VOCM = 1.25V
100mV/DIV
Q
DRIVER INPUT
1V/DIV
0V
1.25ns/DIV
6754 F18
Figure 18. LVDS Receiver Output, 250MHz
18
For more information www.linear.com/LTC6754
6754f
LTC6754
Typical Applications
Short Pulse to Differential Cable Driver and CMOS
Output Receiver
Figure 19 shows a low amplitude short duration pulse
being transmitted over 8 feet of Cat6 differential cable and
converted to a full level CMOS output signal. The pulse
is applied to the input of an LTC6754. A 150Ω resistor is
used along with the 1pF input capacitance of the LTC6754
to limit the rise time at the positive input of the LTC6754,
in order to minimize coupling between the input and other
nodes in the system.
The LTC6754 is used to drive 8 feet of cable terminated
in a 100Ω resistive load at the inputs of an LTC6752-2,
which generates a full scale CMOS logic signal at its output.
DIFFERENTIAL
PULSE TRANSMITTER
3V
PULSE INPUT
400mV
150Ω
0V
+IN
5ns
+
VCCI
VCCO
50Ω
Q
RJ45
LTC6754
VREF = 200mV
–IN
–
3V
VEE
CAT6 CABLE 8ft
RJ45
50Ω
Q
+IN
+
VCC
VDD
LTC6752-2
0.1µF
–IN
Q
–
CMOS
OUTPUT
VEE
6754 F11
6754 F19
Figure 19. Short Pulse to Differential Cable Driver and CMOS Output Receiver
CMOS OUTPUT
1V/DIV
0V
PULSE INPUT
200mV/DIV
0V
2ns/DIV
6754 F20
Figure 20. Pulse Input and Output
6754f
For more information www.linear.com/LTC6754
19
LTC6754
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
SC6 Package
6-Lead Plastic SC70
(Reference LTC DWG # 05-08-1638 Rev B)
0.47
MAX
0.65
REF
1.80 – 2.20
(NOTE 4)
1.00 REF
INDEX AREA
(NOTE 6)
1.80 – 2.40 1.15 – 1.35
(NOTE 4)
2.8 BSC 1.8 REF
PIN 1
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.10 – 0.40
0.65 BSC
0.15 – 0.30
6 PLCS (NOTE 3)
0.80 – 1.00
1.00 MAX
0.00 – 0.10
REF
GAUGE PLANE
0.15 BSC
0.26 – 0.46
0.10 – 0.18
(NOTE 3)
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
20
SC6 SC70 1205 REV B
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. DETAILS OF THE PIN 1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE INDEX AREA
7. EIAJ PACKAGE REFERENCE IS EIAJ SC-70
8. JEDEC PACKAGE REFERENCE IS MO-203 VARIATION AB
6754f
For more information www.linear.com/LTC6754
LTC6754
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UD Package
12-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1855 Rev Ø)
0.70 ±0.05
3.50 ±0.05
1.65 ±0.05
2.10 ±0.05 (4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
3.00 ± 0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
R = 0.115
TYP
0.75 ±0.05
11
12
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
1
2
1.65 ±0.10
(4-SIDES)
(UD12) QFN 0709 REV Ø
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.25 ±0.05
0.50 BSC
6754f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC6754
21
LTC6754
Typical Application
15 Bit PRBS 250Mbps Logic Signal to LVDS Converter Eye Diagram Test Setup
3.3V
1GHz
1k
200Ω
16.7Ω
FPGA
250Mbps
15bit PRBS
LTC2000
16.7Ω
40mA
SAMPLING
OSCILLOSCOPE
BY 4
3.3V
40mA
200Ω
VCCI
+IN
–IN
+
VCCO
Q
LTC6754
LTC6754
–
Q
TRGR
6in COAX
CH1
100Ω
CH2
6in COAX
VEE
DIFFERENTIAL
OUTPUT
200 mV/DIV
FUNCTION =
CH1 – CH2
6754 TA02a
1k
2ns/DIV
6754 TA02b
3.3V
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
2.9ns 280MHz CMOS Output Comparators
RR Inputs. Can drive 1.8V logic directly
(LTC6752-2/LTC6752-3/LTC6752-4)
LT1715
4ns 150MHz Dual Comparators
4.6mA at 3V
LT1720/LT1721
Dual/Quad 4.5ns Single Supply Comparators
4mA/Comparator
LT1711
High Speed Rail-to-Rail Comparators
3V/5V/±5V, 4.5ns at 20mV Overdrive
LT1116
12ns Single Supply Ground Sensing Comparator
Inputs Can Exceed Positive Supply Up to 15V Without Damaging Device
High Speed Comparators
Clock Buffers/Logic Converters
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Low Phase Noise, Dual Output
Buffer/Driver/Logic Converter
LVPECL/LVDS/CMOS Outputs, Additive Jitter 45 fsRMS
High Speed Operational Amplifiers
LTC6252/LTC6253/
LTC6254
Single/Dual/Quad 3.5mA 720 MHz
280V/μs, 2.75nV/√Hz, Rail-to-Rail I/O
LTC6268/LTC6269
Single/Dual 500MHz Ultra Low Bias Current
RR Outputs
LTC6268-10/LTC6269-10 Single/Dual 4GHz Ultra Low Bias Current
RR Outputs, Gain of 10 Stable
LTC6246/LTC6247/
LTC6248
90V/μs, 4.2nV/√Hz,Rail-to-Rail I/O
Single/Dual/Quad 1mA, 180MHz
22 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC6754
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC6754
6754f
LT 0815 • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2015