DATASHEET

5962-0625601, 5962-0625602
Data Sheet
November 3, 2011
1.4GHz Current Feedback Amplifiers with
Enable
The 5962-0625601QXC and 5962-0625602QXC are fully
DLA SMD compliant parts and the SMD data sheets are
available on the DLA website
(http://www.landandmaritime.dla.mil/Programs/MilSpec/Doc
Search.aspx). The 5962-0625601QXC is electrically
equivalent to the EL5166, the 5962-0625602QXC is
electrically equivalent to the EL5167. Reference equivalent
“EL” data sheet for additional information. The amplifiers are
of the current feedback variety and exhibit a very high
bandwidth of 1.4GHz at AV = +1 and 800MHz at AV = +2.
This makes these amplifiers ideal for today's high speed
video and monitor applications, as well as a number of RF
and IF frequency designs.
With a supply current of just 12mA and the ability to run from
a single supply voltage from 5V to 12V, these amplifiers offer
very high performance for little power consumption.
The 5962-0625601QXC also incorporates an enable and
disable function to reduce the supply current to 13µA typical
per amplifier. Allowing the CE pin to float or applying a low
logic level will enable the amplifier.
FN6491.2
Features
• Gain-of-1 bandwidth = 1.4GHz/gain-of-2
bandwidth = 800MHz
• 6000V/µs slew rate
• Single and dual supply operation from 5V to 12V
• Low noise = 1.5nV/√Hz
• 12mA supply current
• Fast enable/disable (5962-0625601QXC only)
Applications
• Video amplifiers
• Cable drivers
• RGB amplifiers
• Test equipment
• Instrumentation
• Current to voltage converters
Ordering Information
PART NUMBER
PART MARKING
PACKAGE
PKG.
DWG. #
5962-0625601QXC 06256 01QXC
10 Ld Flat Pack K10.A
5962-0625602QXC 06256 02QXC
10 Ld Flat Pack K10.A
NOTE: These Intersil Pb-free Hermetic packaged products employ
100% Au plate - e4 termination finish, which is RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
Pinouts
5962-0625602QXC
(10 LD FLAT PACK)
TOP VIEW
5962-0625601QXC
(10 LD FLAT PACK)
TOP VIEW
1
2
3
4
5
NC
NC
IN-
NC
IN+
CE
VS-
VS+
NC
OUT
1
10
1
9
2
8
3
7
4
6
5
NC
NC
IN-
NC
IN+
NC
VS-
VS+
NC
OUT
10
9
8
7
6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007, 2011. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
5962-0625601, 5962-0625602
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . 12.6V
Slewrate between VS+ and VS- . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 20mA
I into VIN+, VIN-, Enable Pins . . . . . . . . . . . . . . . . . . . . . . . . . ±4mA
Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V to VS+ +0.5V
Thermal Resistance (Typical)
θJA (°C/W)
θJC (°C/W)
Flat Pack Package (Notes 1, 2) . . . . . .
165
60
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . .-55°C to +125°C
Die Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144mW
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = -5V, RF = 392Ω for AV = 1, RF = 250Ω for AV = 2, RL = 150Ω, TA = +25°C
Unless Otherwise Specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
-3dB Bandwidth
AV = +1
1400
MHz
AV = +2
800
MHz
BW1
0.1dB Bandwidth
AV = +2
100
MHz
SR
Slew Rate
VO = -2.5V to +2.5V, AV = +2
6000
V/µs
tS
0.1% Settling Time
VOUT = -2.5V to +2.5V, AV = -1
8
ns
eN
Input Voltage Noise
1.7
nV/√Hz
iN-
IN- Input Current Noise
19
pA/√Hz
iN+
IN+ Input Current Noise
50
pA/√Hz
dG
Differential Gain Error (Note 3)
AV = +2
0.01
%
dP
Differential Phase Error (Note 3)
AV = +2
0.03
°
1.5
pF
INPUT CHARACTERISTICS
CIN
Input Capacitance
ENABLE (5962-0625601QXC ONLY)
tEN
Enable Time
170
ns
tDIS
Disable Time
1.25
µs
NOTE:
3. Standard NTSC test, AC signal amplitude = 286mV, f = 3.58MHz.
2
FN6491.2
November 3, 2011
5962-0625601, 5962-0625602
Pin Descriptions
5962-0625601QXCIS
(10 Ld FLAT PACK)
5962-0625602QXCIS
(10 ld FLAT PACK)
Pin Name
1, 5, 9, 10
1, 5, 8 , 9 ,10
NC
Not connected
2
2
IN-
Inverting input
Function
Equivalent Circuit
VS+
IN+
IN-
VSCIRCUIT 1
3
3
IN+
Non-inverting input
4
4
VS-
Negative supply
6
6
OUT
Output
(See circuit 1)
VS+
OUT
VSCIRCUIT 2
7
7
8
VS+
Positive supply
CE
Chip enable
VS+
CE
VSCIRCUIT 3
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
3
FN6491.2
November 3, 2011
5962-0625601, 5962-0625602
Ceramic Metal Seal Flatpack Packages (Flatpack)
K10.A MIL-STD-1835 CDFP3-F10 (F-4A, CONFIGURATION B)
10 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
e
A
INCHES
A
-A-
D
-BPIN NO. 1
ID AREA
b
E1
0.004 M
H A-B S
Q
D S
S1
0.036 M
H A-B S
D S
C
E
-D-
A
-C-
-HL
E2
E3
SEATING AND
BASE PLANE
c1
L
E3
(c)
b1
M
M
(b)
SECTION A-A
MIN
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.045
0.115
1.14
2.92
-
b
0.015
0.022
0.38
0.56
-
b1
0.015
0.019
0.38
0.48
-
c
0.004
0.009
0.10
0.23
-
c1
0.004
0.006
0.10
0.15
-
D
-
0.290
-
7.37
3
E
0.240
0.260
6.10
6.60
-
E1
-
0.280
-
7.11
3
E2
0.125
-
3.18
-
-
E3
0.030
-
0.76
-
7
2
e
LEAD FINISH
BASE
METAL
SYMBOL
0.050 BSC
1.27 BSC
-
k
0.008
0.015
0.20
0.38
L
0.250
0.370
6.35
9.40
-
Q
0.026
0.045
0.66
1.14
8
S1
0.005
-
0.13
-
6
M
-
0.0015
-
0.04
-
N
10
10
Rev. 0 3/07
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass
overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the
leads.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
4
FN6491.2
November 3, 2011
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