DATASHEET

HA-5221
T
UCT
R OD RODU C
P
E
P
T
E
E
L
T
O
U
O B S U B S TI T 2
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4
8
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A- 2
IBL DataHSheet
O SS
®
P
100MHz, Low Noise, Precision
Operational Amplifier
May 2003
FN2915.7
Features
• Gain Bandwidth Product . . . . . . . . . . . . . . . . . . . 100MHz
The HA-5221 is a single high performance dielectrically
isolated, op amp, featuring precision DC characteristics while
providing excellent AC characteristics. Designed for audio,
video, and other demanding applications, noise (3.4nV/√Hz at
1kHz), total harmonic distortion (<0.005%), and DC errors are
kept to a minimum.
The precision performance is shown by low offset voltage
(0.3mV), low bias currents (40nA), low offset currents
(15nA), and high open loop gain (128dB). The combination
of these excellent DC characteristics with the fast settling
time (0.4µs) makes the HA-5221 ideally suited for precision
signal conditioning.
The unique design of the HA-5221 gives it outstanding AC
characteristics not normally associated with precision op
amps, high unity gain bandwidth (35MHz) and high slew rate
(25V/µs). Other key specifications include high CMRR (95dB)
and high PSRR (100dB). The combination of these
specifications will allow the HA-5221 to be used in RF signal
conditioning as well as video amplifiers.
• Unity Gain Bandwidth. . . . . . . . . . . . . . . . . . . . . . . 35MHz
• Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V/µs
• Low Offset Voltage. . . . . . . . . . . . . . . . . . . . . . . . . 0.3mV
• High Open Loop Gain . . . . . . . . . . . . . . . . . . . . . . 128dB
• Low Noise Voltage at 1kHz . . . . . . . . . . . . . . . 3.4nV/√Hz
• High Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 56mA
• Low Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . 8mA
Applications
• Precision Test Systems
• Active Filtering
• Small Signal Video
• Accurate Signal Processing
• RF Signal Conditioning
Pinout
HA-5221 (CERDIP)
TOP VIEW
Part Number Information
PART NUMBER
(BRAND)
HA7-5221-5
TEMP.
RANGE (oC)
0 to 75
PACKAGE
8 Ld CERDIP
PKG.
NO.
F8.3A
-BAL 1
-IN
+IN 3
V-
1
8 +BAL
2
4
7 V+
+
6 OUT
5 NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HA-5221
Absolute Maximum Ratings
Thermal Information
Supply Voltage Between V+ and V- Terminals . . . . . . . . . . . . . 35V
Differential Input Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . 5V
Output Current Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Thermal Resistance (Typical, Note 2)
Operating Conditions
θJA (oC/W)
θJC (oC/W)
CERDIP Package. . . . . . . . . . . . . . . . .
115
28
Maximum Junction Temperature (Hermetic Package) . . . . . . . 175oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Temperature Range
HA-5221-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Input is protected by back-to-back zener diodes. See applications section.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
3. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
VSUPPLY = ±15V, Unless Otherwise Specified
Electrical Specifications
TEMP. (oC)
MIN
TYP
MAX
UNITS
25
-
0.30
0.75
mV
Full
-
0.35
1.5
mV
Average Offset Voltage Drift
Full
-
0.5
-
µV/oC
Input Bias Current
25
-
40
100
nA
Full
-
70
200
nA
25
-
15
100
nA
Full
-
30
150
nA
25
-
400
750
µV
Full
-
-
1500
µV
Common Mode Range
25
±12
-
-
V
Differential Input Resistance
25
-
70
-
kΩ
25
-
0.25
-
µVP-P
25
-
6.2
10
nV/√Hz
f = 100Hz
25
-
3.6
6
nV/√Hz
f = 1000Hz
25
-
3.4
4.0
nV/√Hz
25
-
4.7
8.0
pA/√Hz
f = 100Hz
25
-
1.8
2.8
pA/√Hz
f = 1000Hz
25
-
0.97
1.8
pA/√Hz
Note 4
25
-
<0.005
-
%
Note 5
25
106
128
-
dB
Full
100
120
-
dB
PARAMETER
TEST CONDITIONS
INPUT CHARACTERISTICS
Input Offset Voltage
Input Offset Current
Input Offset Voltage Match
Input Noise Voltage
f = 0.1Hz to 10Hz
Input Noise Voltage Density (Notes 3, 11) f = 10Hz
Input Noise Current Density (Notes 3, 11) f = 10Hz
THD+N
TRANSFER CHARACTERISTICS
Large Signal Voltage Gain
CMRR
VCM = ±10V
Full
86
95
-
dB
Unity Gain Bandwidth
-3dB
25
-
35
-
MHz
2
HA-5221
VSUPPLY = ±15V, Unless Otherwise Specified (Continued)
Electrical Specifications
TEMP. (oC)
MIN
TYP
MAX
UNITS
25
-
100
-
MHz
Full
1
-
-
V/V
RL = 333Ω
Full
±10
-
-
V
RL = 1kΩ
25
±12
±12.5
-
V
RL = 1kΩ
Full
±11.5
±12.1
-
V
VOUT = ±10V
Full
±30
±56
-
mA
25
-
10
-
Ω
Note 6
25
239
398
-
kHz
Slew Rate
Notes 7, 11
Full
15
25
-
V/µs
Rise Time
Notes 8, 11
Full
-
13
20
ns
Overshoot
Notes 8, 11
Full
-
28
50
%
Settling Time (Notes 9, 10)
0.1%
25
-
0.4
-
µs
0.01%
25
-
1.5
-
µs
VS = ±10V to ±20V
Full
86
100
-
dB
Full
-
8
11
mA
PARAMETER
TEST CONDITIONS
Gain Bandwidth Product
1kHz to 400kHz
Minimum Stable Gain
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Output Resistance
Full Power Bandwidth
TRANSIENT RESPONSE (Note 11)
POWER SUPPLY
PSRR
Supply Current
NOTES:
4. Refer to typical performance curve in data sheet.
5. AVCL = 10, fO = 1kHz, VO = 5VRMS, RL = 600Ω, 10Hz to 100kHz, minimum resolution of test equipment is 0.005%.
6. VOUT = 0 to ±10V, RL = 1kΩ, CL = 50pF.
Slew Rate
7. Full Power Bandwidth is calculated by: FPBW = ---------------------------, V PEAK = 10V .
2πV PEAK
8. VOUT = ±2.5V, RL = 1kΩ, CL = 50pF.
9. VOUT = ±100mV, RL = 1kΩ, CL = 50pF.
10. Settling time is specified for a 10V step and AV = -1.
11. See Test Circuits.
12. Guaranteed by characterization.
Test Circuits and Waveforms
VIN
+
VOUT
-
1kΩ
50pF
FIGURE 1. TRANSIENT RESPONSE TEST CIRCUIT
3
HA-5221
Test Circuits and Waveforms
(Continued)
100mV
2.5V
VIN
0V
0V
-100mV
-2.5V
2.5V
100mV
VOUT
0V
0V
-100mV
-2.5V
VOUT = ±100mV
Vertical Scale = 100mV/Div.,
Horizontal Scale = 200ns/Div.
VOUT = ±2.5V
Vertical Scale = 2V/Div.,
Horizontal Scale = 200ns/Div.
FIGURE 2. LARGE SIGNAL RESPONSE
FIGURE 3. SMALL SIGNAL RESPONSE
VSETTLE
5K
5K
2K
2K
VIN
+
VOUT
NOTES:
13. AV = -1.
14. Feedback and summing resistors must be matched (0.1%).
15. HP5082-2810 clipping diodes recommended.
16. Tektronix P6201 FET probe used at settling point.
FIGURE 4. SETTLING TIME TEST CIRCUIT
Application Information
Operation at Various Supply Voltages
The HA-5221 operates over a wide range of supply voltages
with little variation in performance. The supplies may be
varied from ±5V to ±15V. See typical performance curves for
variations in supply current, slew rate and output voltage
swing.
+15V
7
3
Offset Adjustment
RP
1
8
2
6
+
4
The following diagram shows the offset voltage adjustment
configuration for the HA-5221. By moving the potentiometer
wiper towards pin 8 (+BAL), the op amps output voltage will
increase; towards pin 1 (-BAL) decreases the output voltage.
A 20kΩ trim pot will allow an offset voltage adjustment of
about 10mV.
4
-15V
Capacitive Loading Considerations
When driving capacitive loads >80pF, a small resistor, 50Ω
to 100Ω, should be connected in series with the output and
inside the feedback loop.
HA-5221
Saturation Recovery
When an op amp is over driven, output devices can saturate
and sometimes take a long time to recover. By clamping the
input, output saturation can be avoided. If output saturation
can not be avoided, the maximum recovery time when
overdriven into the positive rail is 10.6µs. When driven into
the negative rail the maximum recovery time is 3.8µs.
Input Protection
The HA-5221 has built in back-to-back protection diodes
which limit the maximum allowable differential input voltage
to approximately 5V. If the HA-5221 is used in circuits where
the maximum differential voltage may be exceeded, then
current limiting resistors must be used. The input current
should be limited to a maximum of 10mA.
Typical Performance Curves
RLIMIT
2
12
9
AV = +1, RL = 1K, CL = 50pF
20
180
135
PHASE
90
45
0
1M
10M
3
GAIN
0
-3
-6
180
PHASE
90
45
10K
100M
100K
FREQUENCY (Hz)
3
GAIN
180
PHASE
135
90
45
0
10K
100K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 7. CLOSED LOOP GAIN vs FREQUENCY
5
0
100M
FIGURE 6. CLOSED LOOP GAIN vs FREQUENCY
CLOSED LOOP GAIN (dB)
AV = -1, RL = 1K, CL = 50pF
PHASE MARGIN (DEGREES)
GAIN (dB)
9
0
10M
1M
FREQUENCY (Hz)
FIGURE 5. OPEN LOOP GAIN AND PHASE vs FREQUENCY
6
135
80
60
40
20
AV = -1000
RL = 1K, CL = 50pF
AV = -100
AV = -10
0
AV = -10
AV = -100
180
135
90
AV = -1000
45
0
10K
100K
1M
10M
PHASE MARGIN (DEGREES)
100K
6
PHASE MARGIN (DEGREES)
40
GAIN (dB)
60
PHASE MARGIN (DEGREES)
GAIN (dB)
GAIN
10K
3
VS = ±15V, TA = 25oC
100
1K
VOUT
+
When designing with the HA-5221, good high frequency
(RF) techniques should be used when building a PC board.
Use of ground plane is recommended. Power supply
decoupling is very important. A 0.01µF to 0.1µF high quality
ceramic capacitor at each power supply pin with a 2.2µF to
10µF tantalum close by will provide excellent decoupling.
Chip capacitors produce the best results due to ease of
placement next to the op amp and basically no lead
inductance. If leaded capacitors are used, the leads should
be kept as short as possible to minimize lead inductance.
120
0
RLIMIT
PC Board Layout Guidelines
RL = 1K, CL = 50pF
80
6
∆VIN
100M
FREQUENCY (Hz)
FIGURE 8. VARIOUS CLOSED LOOP GAINS vs FREQUENCY
HA-5221
Typical Performance Curves
AV = +1, RL = 1K
AV = +1, RL = 1K
100
100
80
80
PSRR (dB)
CMRR (dB)
120
VS = ±15V, TA = 25oC (Continued)
60
40
20
0
-PSRR
60
40
20
+PSRR
0
10K
100K
1M
10M
100M
10K
100K
FIGURE 9. CMRR vs FREQUENCY
100M
300
RL = 1K
250
16
OFFSET VOLTAGE (µV)
OPEN LOOP GAIN (V/µV)
10M
FIGURE 10. PSRR vs FREQUENCY
20
18
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
14
12
10
8
6
200
150
100
50
0
4
-50
2
0
-60
-40
-20
0
20
40
60
80
100
-100
-60
120
-40
-20
TEMPERATURE (oC)
0
20
40
60
80
100
120
TEMPERATURE (oC)
FIGURE 11. OPEN LOOP GAIN vs TEMPERATURE
FIGURE 12. OFFSET VOLTAGE vs TEMPERATURE
(4 REPRESENTATIVE UNITS)
PEAK OUTPUT VOLTAGE (V)
14
BIAS CURRENT (nA)
160
140
120
100
80
60
40
20
0
-20
-40
-60
RL = 600Ω
13.5
13
12.5
12
11.5
11
10.5
10
-40
-20
0
20
40
60
80
TEMPERATURE (oC)
FIGURE 13. BIAS CURRENT vs TEMPERATURE
(4 REPRESENTATIVE UNITS)
6
100
120
-60
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (oC)
FIGURE 14. OUTPUT VOLTAGE SWING vs TEMPERATURE
HA-5221
VS = ±15V, TA = 25oC (Continued)
70
1.1
AV = +1, RL = 1K, CL = 50pF
OFFSET VOLTAGE CHANGE (µV)
SLEW RATE (NORMALIZED TO 1 AT 25oC)
Typical Performance Curves
1.05
1.0
0.95
0.9
0.85
0.8
-60
60
50
40
30
20
10
0
-40
-20
0
20
40
60
80
100
0
120
1
TEMPERATURE (oC)
FIGURE 15. SLEW RATE vs TEMPERATURE
3
4
5
FIGURE 16. OFFSET VOLTAGE WARM-UP DRIFT
(CERDIP PACKAGES)
8.5
36
34
32
8.25
SLEW RATE (V/µs)
SUPPLY CURRENT (mA)
2
TIME AFTER POWER UP (MINUTES)
8
7.75
AV = +1, RL = 2K, CL = 50pF
+SLEW RATE
30
28
26
24
22
-SLEW RATE
20
18
16
14
12
10
7.5
5
7
9
11
13
15
5
17
7
9
SUPPLY VOLTAGE (±V)
11
13
15
17
SUPPLY VOLTAGE (±V)
FIGURE 17. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 18. SLEW RATE vs SUPPLY VOLTAGE
15
10
5
16
24
14
21
12
18
10
15
8
12
6
9
4
VOLTAGE NOISE 6
2
CURRENT NOISE 3
0
0
5
7
9
11
13
SUPPLY VOLTAGE (±V)
15
17
FIGURE 19. OUTPUT VOLTAGE SWING vs SUPPLY VOLTAGE
7
1
10
100
1K
FREQUENCY (Hz)
FIGURE 20. NOISE CHARACTERISTICS
0
10K
CURRENT NOISE (pA/√Hz)
RL = 600Ω
VOLTAGE NOISE (nV/√Hz)
PEAK OUTPUT VOLTAGE SWING (V)
20
HA-5221
100
90
80
70
60
50
40
30
20
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-60
VS = ±15V, TA = 25oC (Continued)
CMRR AND PSRR (dB)
OFFSET CURRENT (nA)
Typical Performance Curves
-40
-20
0
20
40
60
TEMPERATURE (oC)
80
100
120
45
CMRR
-40
-20
0
20
40
60
80
100
120
130
40
100
35
80
BANDWIDTH
30
60
25
40
20
20
15
0
10
100
1000
LOAD CAPACITANCE (pF)
FIGURE 23. BANDWIDTH AND PHASE MARGIN vs LOAD
CAPACITANCE
Vertical Scale = 1mV/Div.; Horizontal Scale = 1s/Div.
AV = +25,000; EN = 0.168µVP-P RTI
FIGURE 25. 0.1Hz TO 10Hz NOISE
8
OUTPUT CURRENT (mA)
AV = +1, RL = 1K
PHASE MARGIN (DEGREE)
BANDWIDTH (MHz)
-PSRR
FIGURE 22. CMRR AND PSRR vs TEMPERATURE
120
1
+PSRR
TEMPERATURE (oC)
FIGURE 21. OFFSET CURRENT vs TEMPERATURE
(4 REPRESENTATIVE UNITS)
PHASE MARGIN
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
-60
110
90
70
50
0
1
2
3
4
TIME AFTER SHORT CIRCUIT (MINUTES)
FIGURE 24. SHORT CIRCUIT OUTPUT CURRENT vs TIME
Vertical Scale = 10mV/Div.; Horizontal Scale = 1s/Div.
AV = +25,000; EN = 1.5µVP-P RTI
FIGURE 26. 0.1Hz TO 1MHz
5
HA-5221
Typical Performance Curves
18
18
AV = +1, RL = 1K, CL = 15pF, THD ≤ 0.01%
VS = ±18
14
12
VS = ±15
10
8
6
VS = ±10
4
2
14
VS = ±18
VS = ±15
12
10
VS = ±10
8
6
4
VS = ±5
0
10K
AV = +1, THD ≤ 0.01%, f = 1kHz
16
PEAK OUTPUT VOLTAGE (V)
PEAK OUTPUT VOLTAGE (V)
16
VS = ±15V, TA = 25oC (Continued)
VS = ±5
2
100K
1M
0
10
10M
100
FIGURE 27. OUTPUT VOLTAGE SWING vs FREQUENCY
9.5
SUPPLY CURRENT (mA)
10K
FIGURE 28. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
10
9
8.5
8
7.5
7
6.5
6
-60
-40
-20
0
20
40
60
80
100
TEMPERATURE (oC)
FIGURE 29. SUPPLY CURRENT vs TEMPERATURE
9
1K
LOAD RESISTANCE (Ω)
FREQUENCY (Hz)
120
HA-5221
Die Characteristics
DIE DIMENSIONS:
SUBSTRATE POTENTIAL (POWERED UP):
72 mils x 94 mils
1840µm x 2400µm
VTRANSISTOR COUNT:
METALLIZATION:
62
Type: Al, 1% Cu
Thickness: 16kÅ ±2kÅ
PROCESS:
Bipolar Dielectric Isolation
PASSIVATION:
Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.)
Silox Thickness: 12kÅ ±2kÅ
Nitride Thickness: 3.5kÅ ±1.5kÅ
Metallization Mask Layout
HA-5221
V-
+IN
-IN
-BAL
+BAL
OUT
10
V+
HA-5221
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
LEAD FINISH
c1
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
-A-
BASE
METAL
E
M
-Bbbb S
C A-B S
-C-
S1
0.200
-
5.08
-
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.405
-
10.29
5
E
0.220
0.310
5.59
7.87
5
eA
e
ccc M
C A-B S
eA/2
c
aaa M C A - B S D S
D S
NOTES
-
b2
b
MAX
0.014
α
A A
MIN
b
A
L
MILLIMETERS
MAX
A
Q
SEATING
PLANE
MIN
M
(b)
D
BASE
PLANE
SYMBOL
b1
SECTION A-A
D S
INCHES
(c)
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
105o
90o
105o
-
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
α
90o
aaa
-
0.015
-
0.38
-
bbb
-
0.030
-
0.76
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
8
8
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
8
Rev. 0 4/94
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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11
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