DATASHEET

EL5181
®
Data Sheet
December 4, 2001
FN7178
8ns High-Speed Comparator
Features
The EL5181 comparator is designed
for operation in single supply and dual
supply applications with 5V to 12V
between VS+ and VS-. For single supplies, the inputs can
operate from 0.1V below ground for use in ground sensing
applications.
• 8ns Typ. propagation delay
The output side of the comparator can be supplied from a
single supply of 2.7V to 5V. The rail-to-rail output swing
enables direct connection of the comparator to both CMOS
and TTL logic circuits.
• Rail-to-rail outputs
The latch input of the EL5181 can be used to hold the comparator output value by applying a low logic level to the pin.
• Window comparator (EL5283)
The EL5181 is available in the 8-pin SO package and is
specified for operation over the full -40°C to +85°C temperature range. Also available are a dual (EL5281), a window
comparator (EL5283), and quad versions (EL5481 and
EL5482).
• +2.7V to +5V output supply
• True-to-ground input
• Active low latch
• Dual available (EL5281)
• Quad available (EL5481 & EL5482)
• Pin-compatible 4ns family available (EL5x85, EL5287 &
EL5486)
Applications
• Threshold detection
Ordering Information
PART
NUMBER
• 5V to 12V input supply
• High speed sampling circuits
PACKAGE
TAPE & REEL
PKG. NO.
• High speed triggers
EL5181CS
8-Pin SO
-
MDP0027
• Line receivers
EL5181CS-T7
8-Pin SO
7”
MDP0027
• PWM circuits
EL5181CS-T13
8-Pin SO
13”
MDP0027
• High speed V/F converters
Pinout
EL5181
(8-PIN SO)
TOP VIEW
1
VS+
1
IN+
2
IN-
3
VS-
4
+
-
L
A
T
C
H
8
VSD
7
OUT
6
GND
5
LATCH
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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EL5181
Absolute Maximum Ratings (TA = 25°C)
Analog Supply Voltage (V S+ to VS-) . . . . . . . . . . . . . . . . . . . +12.6V
Digital Supply Voltage (VSD to GND) . . . . . . . . . . . . . . . . . . . . .+7V
Differential Input Voltage . . . . . . . . . . .[(VS-) -0.2V] to [(VS+) +0.2V]
Common-mode Input Voltage . . . . . . .[(VS-) -0.2V] to [(VS+) +0.2V]
Latch Input Voltage . . . . . . . . . . . . . . . . . . . . -0.2V to [(V SD) +0.2V]
Storage Temperature Range . . . . . . . . . . . . . . . . . . -65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . . -40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
VS = ±5V, V SD = 5V, RL = 2.3kΩ, C L = 15pF, T A = 25°C, unless otherwise specified.
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
1
4
mV
INPUT
VOS
Input Offset Voltage
VCM = 0V, VO = 2.5V
IB
Input Bias Current
CIN
Input Capacitance
IOS
Input Offset Current
VCM
Input Voltage Range
CMRR
Common-mode Rejection Ratio
-5.1V < VCM < +2.75V
VOH
Output High Voltage
VIN > 250mV
VOL
Output Low Voltage
VIN > 250mV
tPD+
Positive Going Delay Time
tPD-
Negative Going Delay Time
-6
VCM = 0V, VO = 2.5V
-2.5
-3.5
µA
5
pF
0.5
(VS-) - 0.1
2.5
µA
(V S+) 2.25
V
65
90
dB
VSD - 0.6
VSD - 0.4
V
OUTPUT
GND +
0.25
GND + 0.5
V
VIN = 1V P-P, VOD = 50mV
8
12
ns
VIN = 1V P-P, VOD = 50mV
8
12
ns
DYNAMIC PERFORMANCE
SUPPLY
IS+
Positive Analog Supply Current
7
8.2
mA
IS-
Negative Analog Supply Current
5
6.5
mA
ISD
Digital Supply Current
Output high
4
5
mA
Output low
0.75
1
mA
PSRR
Power Supply Rejection Ratio
60
80
dB
LATCH
VLH
Latch Input Voltage High
VLL
Latch Input Voltage Low
ILH
Latch Input Current High
VLH = 3.0V
-30
-18
µA
ILL
Latch Input Current Low
VLL = 0.3V
-30
-24
µA
td+
Latch Disable to High Delay
6
ns
tD-
Latch Disable to Low Delay
6
ns
tS
Minimum Setup Time
2
ns
tH
Minimum Hold Time
1
ns
tPW(D)
Minimum Latch Disable Pulse Width
10
ns
2
2.0
0.8
V
V
EL5181
Typical Performance Curves
Negative Supply Current vs Temperature
Positive Supply Current vs Temperature
7.15
-4.4
7.1
-4.5
7.05
-4.6
IS- (mA)
IS+ (mA)
7
6.95
6.9
6.85
-4.7
-4.8
-4.9
-5
6.8
-5.1
6.75
6.7
-50
-30
-10
10
30
50
70
-5.2
-50
90
-30
-10
10
30
50
70
90
Temperature (°C)
Temperature (°C)
Positive Supply Current vs Supply Voltage
Negative Supply Current vs Negative Supply
Voltage
7
5.5
6
5
4
IS- (mA)
IS+ (mA)
5
3
VS- = -5V
VSD = 5V
VIN = 50mV
TA = 25°C
2
1
4.5
4
VS+ = 5V
VSD = 5V
VIN = 50mV
TA = 25°C
3.5
0
3
0
1
2
3
4
5
6
7
0
1
2
VS+ (V)
3
4
5
6
7
50
70
90
VS- (V)
Input Bias Current vs Temperature
Offset Voltage vs Temperature
6
0.7
0.6
5
0.5
0.4
VOS (mV)
IB (µA)
4
3
2
0.3
0.2
0.1
0
-0.1
1
-0.2
0
-50
-30
-10
10
30
Temperature (°C)
3
50
70
90
-0.3
-50
-30
-10
10
30
Temperature (°C)
EL5181
Typical Performance Curves
(Continued)
Propagation Delay vs Overdrive
Propagation Delay vs Load Capacitance
10
12
VS = ±5V
VSD = 5 V
VIN = 1V Step
RL = 2.2kΩ
Delay Time (ns)
9
8.5
VS = ±5V
VSD = 5V
RL = 2.2kΩ
VIN = 1V Step
VOD = 50mV
11
Delay Time (ns)
9.5
TPD+
8
7.5
7
TPD -
6.5
6
10
TPD+
9
8
TPD-
7
5.5
5
0
100
200
300
400
500
6
0
600
20
40
VOD (mV)
Propagation Delay vs Supply Voltage
100
120
10
VSD = VS+
VIN = 1V Step
VOD = 50mV
RL = 2.2kΩ
9
8.5
9.5
TPD+
9
8
Delay Time (ns)
9.5
TPD+
7.5
7
TPD -
6.5
8.5
8
7.5
6.5
5.5
5
4
4.5
5
5.5
6
0
6
TPD-
VS = ±5V
VSD = 5V
VIN = 3V Step
RL = 2.2kΩ
7
6
0.2
0.4
0.6
0.8
VS = ±5V
VSD = 5V
R L = 2.2kΩ
VIN = 5V Step
18
16
TPD+
9.5
9
TPD -
8.5
14
1.6
1.8
2
7.5
6
1
1.5
VOD (V)
4
2
2.5
3
TPD+
10
8
0.5
VS = ±5V
VSD = 5V
RL = 2.2kΩ
VIN = 1V Step
VOD = 50mV
12
8
7
0
1.4
20
Delay Time (ns)
10
1.2
Propagation Delay vs Source Resistance
Propagation Delay vs Overdrive
11
10.5
1
VOD (V)
±VS (V)
Delay Time (ns)
80
Propagation Delay vs Overdrive
10
Delay Time (ns)
60
CLOAD (pF)
4
0
TPD-
0.2
0.4
0.6
0.8
1
1.2
Source Resistance (kΩ)
1.4
1.6
EL5181
Typical Performance Curves
(Continued)
Output Low Voltage vs Load Current
Output High Voltage vs Load Current
0.31
4.75
VS = ±5V
VSD = 5V
VIN = 50mV
TA = 85°C
0.27
Output High Voltage (V)
Output Low Voltage (V)
4.7
TA = 25°C
0.23
TA = -40°C
0.19
VS = ±5V
VSD = 5V
VIN = -50mV
TA = -40°C
4.65
4.6
TA = 25°C
4.55
4.5
TA = 85°C
4.45
4.4
4.35
0.15
4.3
0
2
4
6
8
10
0
2
Load Current (mA)
4
6
8
10
Load Current (mA)
Package Power Dissipation vs Ambient Temperature
JEDEC JESD51-3 Low Effective Thermal Conductivity
Test Board
Digital Supply Current vs Input Switching
Frequency
30
0.7
VS = ±5V
0.6
Power Dissipation (W)
25
ISD (mA)
20
15
VSD = 5V
10
VSD = 3V
5
625mW
0.5
SO
16
8
0°
C
/W
0.4
0.3
0.2
0.1
0
0
0
5
10
15
20
25
30
35
40
45
50
0
25
Frequency (MHz)
VS = ±5V
VSDS= 5V
VO
VIN
VIN
2V
5
85
100
VIN = 3VP-P
FIN = 30MHz
VO
1V
75
125
Output with 30MHz Input
VIN = 3VP-P
Output with 30MHz Input
VIN = 1VP-P
VIN = 1VP-P
FIN = 30MHz
50
Ambient Temperature (°C)
20ns
2V
2V
20ns
VS = ±5V
VSD = 5V
150
EL5181
Timing Diagram
Compare
Compare
Latch
Enable
Input
1.4V
Latch
Latch
Differenti
al Input
Voltage
Latch
tPW(D)
tS
tH
VIN
VOS
VOD
tPD-
t D+
Comparator
Output
2.4V
Definition of Terms
TERM
DEFINITION
VOS
Input Offset Voltage - Voltage applied between the two input terminals to obtain CMOS logic threshold at the output
VIN
Input Voltage Pulse Amplitude - Usually set to 1V for comparator specifications
VOD
Input Voltage Overdrive - Usually set to 50mV and in opposite polarity to V IN for comparator specifications
tPD+
Input to Output High Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to
the CMOS logic threshold of an output low to high transition
tPD-
Input to Output Low Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to
the CMOS logic threshold of an output high to low transition
tD+
Latch Disable to Output High Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a
low to high transition to the point of the output crossing CMOS threshold in a low to high transition
tD-
Latch Disable to Output Low Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a
low to high transition to the point of the output crossing CMOS threshold in a high to low transition
tS
Minimum Setup Time - The minimum time before the negative transition of the latch signal that an input signal change must be
present in order to be acquired and held at the outputs
tH
Minimum Hold Time - The minimum time after the negative transition of the latch signal that an input signal must remain
unchanged in order to be acquired and held at the output
tPW (D)
Minimum Latch Disable Pulse Width - The minimum time that the latch signal must remain high in order to acquire and hold an
input signal change
6
EL5181
Pin Descriptions
PIN NUMBER
PIN NAME
FUNCTION
1
VS+
Positive supply voltage
2
IN+
Positive input
EQUIVALENT CIRCUIT
VS+
IN-
IN+
VS-
Circuit 1
3
IN-
Negative input
4
VS-
Negative supply voltage
5
LATCH
(Reference Circuit 1)
Latch input
VS+
VSD
LATCH
VS-
Circuit 2
6
GND
Digital ground
7
OUT
Output
VSD
VS+
OUT
VS-
Circuit 3
8
VSD
Digital Supply
7
EL5181
Applications Information
Power Supplies and Circuit Layout
The EL5181 comparator operates with single and dual supply with 5V to 12V between VS+ and VS-. The output side of
the comparator is supplied by a single supply from 2.7V to
5V. The rail to rail output swing enables direct connection of
the comparator to both CMOS and TTL logic circuits. As with
many high speed devices, the supplies must be well
bypassed. Elantec recommends a 4.7µF tantalum in parallel
with a 0.1µF ceramic. These should be placed as close as
possible to the supply pins. Keep all leads short to reduce
stray capacitance and lead inductance. This will also minimize unwanted parasitic feedback around the comparator.
The device should be soldered directly to the PC board
instead of using a socket. Use a PC board with a good,
unbroken low inductance ground plane. Good ground plane
construction techniques enhance stability of the
comparators.
Input Voltage Considerations
The EL5181 input range is specified from 0.1V below VS- to
2.25V below VS+. The criterion for the input limit is that the
output still responds correctly to a small differential input signal. The differential input stage is a pair of PNP transistors,
therefore, the input bias current flows out of the device.
When either input signal falls below the negative input voltage limit, the parasitic PN junction formed by the substrate
and the base of the PNP will turn on, resulting in a significant
increase of input bias current. If one of the inputs goes above
the positive input voltage limit, the output will still maintain
the correct logic level as long as the other input stays within
the input range. However, the propagation delay will
increase. When both inputs are outside the input voltage
range, the output becomes unpredictable. Large differential
voltages greater than the supply voltage should be avoided
to prevent damages to the input stage.
Input Slew Rate
Most high speed comparators oscillate when the voltage of
one of the inputs is close to or equal to the voltage on the
other input due to noise or undesirable feedback. For clean
output waveform, the input must meet certain minimum slew
rate requirements. In some applications, it may be helpful to
apply some positive feedback (hysteresis) between the output and the positive input. The hysteresis effectively causes
one comparator's input voltage to move quickly past the
other, thus taking the input out of the region where oscillation
occurs. For the EL5181, the propagation delay increases
when the input slew rate increases for low overdrive voltages. With high overdrive voltages, the propagation delay
does not change much with the input slew rate.
Latch Pin Dynamics
The EL5181 contains a “transparent” latch for each channel.
The latch pin is designed to be driven with either a TTL or
CMOS output. When the latch is connected to a logic high
level or left floating, the comparator is transparent and immediately responds to the changes at the input terminals. When
the latch is switched to a logic low level, the comparator output remains latched to its value just before the latch’s high8
to-low transition. To guarantee data retention, the input signal must remain the same state at least 1ns (hold time) after
the latch goes low and at least 2ns (setup time) before the
latch goes low. When the latch goes high, the new data will
appear at the output in approximately 6ns (latch propagation
delay).
Hysteresis
Hysteresis can be added externally. The following two methods can be used to add hysteresis.
Inverting comparator with hysteresis:
VREF
R3
R2
+
R1
VIN
-
R3 adds a portion of the output to the threshold set by R 1 and
R2. The calculation of the resistor values are as follows:
Select the threshold voltage VTH and calculate R1 and R2.
The current through R1/R2 bias string must be many times
greater than the input bias current of the comparator:
R1
V TH = VREF × --------------------R1 + R2
Let the hysteresis be VH, and calculate R3:
VO
R 3 = -------× ( R 1 || R 2 )
VH
where:
VO =V SD-0.8V (swing of the output)
Recalculate R2 to maintain the same value of VTH:

 VTH  V TH -0.5VSD
R 2 1 = ( ( V REF )-  V TH ) ÷  ---------- + ----------------------------------- 
R3

 R1 

Non inverting comparator with hysteresis:
R3
R1
+
VIN
VREF
-
R3 adds a portion of the output to the positive input. Note that
the current through R 3 should be much greater than the input
bias current in order to minimize errors. The calculation of
the resistor values as follows:
Pick the value of R1. R1 should be small (less than 1kΩ) in
order to minimize the propagation delay time.
Choose the hysteresis VH and calculate R 3:
R1
R 3 = ( V SD -0.8 ) × ------V
H
EL5181
Check the current through R3 and make sure that it is much
greater than the input bias current as follows:
0.5VSD -V REF
I = --------------------------------------R3
The above two methods will generate hysteresis of up to a
few hundred millivolts. Beyond that, the impedance of R3 is
low enough to affect the bias string and adjustment of R1
may be required.
Threshold Detector
The inverting input is connected to a reference voltage and
the non-inverting input is connected to the input. As the input
passes the V REF threshold, the comparator's output
changes state. The non-inverting and inverting inputs may
be reversed.
VIN
+
VREF
-
VOUT
Power Dissipation
When switching at high speeds, the comparator's drive capability is limited by the rise in junction temperature caused by
the internal power dissipation. For reliable operation, the
junction temperature must be kept below TJMAX (125°C).
An approximate equation for the device power dissipation is
as follows. Assume the power dissipation in the load is very
small:
P DISS = ( VS × IS + V SD × I SD )
where:
VS is the analog supply voltage from V S+ to VSIS is the analog quiescent supply current per comparator
VSD is the digital supply voltage from VSD to ground
ISD is the digital supply current per comparator
I SD strongly depends on the input switching frequency.
Please refer to the performance curve to choose the input
driving frequency. Having obtained the power dissipation,
the maximum junction temperature can be determined as
follows:
TJMAX = T MAX + Θ JA × PDISS
Crystal Oscillator
A simple crystal oscillator using one comparator of an
EL5181 is shown below. The resistors R1 and R 2 set the
bias point at the comparator's non-inverting input. Resistors
R3, R4, and C 1 set the inverting input node at an appropriate
DC average voltage based on the output. The crystal's path
provides resonant positive feedback and stable oscillation
occurs. Although the EL5181 will give the correct logic output
when an input is outside the common mode range, additional
delays may occur when it is so operated. Therefore, the DC
bias voltages at the inputs are set about 500mV below the
center of the common mode range and the 200Ω resistor
attenuates the feedback to the non-inverting input. The circuit will operate with most AT-cut crystal from 1MHz to 8MHz
over a 2V to 7V supply range. The output duty cycle for this
circuit is roughly 50% at 5V VCC , but it is affected by the tolerances of the resistors. The duty cycle can be adjusted by
changing V CC value.
1MHz to 8MHz
5V
200Ω
R1
5kΩ
where:
TMAX is the maximum ambient temperature
R2
θJA is the thermal resistance of the package
1.5kΩ
+
VOUT
R3
C1
R4
0.01µF
2kΩ
2kΩ
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9
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