DATASHEET

HA-4900, HA-4902, HA-4905
Data Sheet
June 28, 2012
FN2855.5
Precision Quad Comparators
Features
The HA-4900 series are monolithic, quad, precision comparators
offering fast response time, low offset voltage, low offset current
and virtually no channel-to-channel crosstalk for applications
requiring accurate, high speed, signal level detection. These
comparators can sense signals at ground level while being operated
from either a single +5V supply (digital systems) or from dual
supplies (analog networks) up to ±15V. The HA-4900 series
contains a unique current driven output stage which can be
connected to logic system supplies (VLOGIC+ and VLOGIC-) to
make the output levels directly compatible (no external
components needed) with any standard logic or special system
logic levels. In combination analog/digital systems, the design
employed in the HA-4900 series input and output stages prevents
troublesome ground coupling of signals between analog and digital
portions of the system.
• Fast Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130ns
These comparators’ combination of features make them ideal
components for signal detection and processing in data acquisition
systems, test equipment and microprocessor/analog signal
interface networks.
• Window Detector
For military grade product, refer to the HA-4902/883 data sheet.
• Logic System Interfaces
Pinout
Ordering Information
HA-4900, HA-4902 (CERDIP)
HA-4905 (PDIP, CERDIP, SOIC)
TOP VIEW
2
4
-IN 1
+IN 1
3
4
+
-IN 2
7
OUT 2
8
+
15 -IN 4
14 +IN 4
13 V+
3
6
-
1
V- 5
+IN 2
• Low Offset Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10nA
• Single or Dual Voltage Supply Operation
• Selectable Output Logic Levels
• Active Pull-Up/Pull-Down Output Circuit. No External Resistors Required
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Threshold Detector
• Zero Crossing Detector
• Analog Interfaces for Microprocessors
• High Stability Oscillators
PART
NUMBER
PART
MARKING
TEMP
RANGE
(oC)
PACKAGE
PKG.
DWG. #
HA1-4900-2
HA1-4900-2
-55 to 125 16 Ld CERDIP
F16.3
HA1-4902-2
HA1-4902-2
-55 to 125 16 Ld CERDIP
F16.3
HA1-4905-5
HA1-4905-5
0 to 75
16 Ld CERDIP
F16.3
HA3-4905-5
HA3-4905-5
0 to 75
16 Ld PDIP
E16.3
HA9P4905-5
HA9P4905-5
0 to 75
16 Ld SOIC
M16.3
HA9P4905-5Z
(See Note)
HA9P49055Z
0 to 75
16 Ld SOIC
(Pb-free)
M16.3
16 OUT 4
VL+ 1
OUT 1
• Low Offset Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0mV
+
-2
+
12 +IN 3
-
11 -IN 3
10 OUT 3
9 VL-
1
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 1999, 2005, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
HA-4900, HA-4902, HA-4905
Absolute Maximum Ratings
Thermal Information
Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . . . . . . . . . 33V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Voltage Between VLOGIC+ and VLOGIC- . . . . . . . . . . . . . . . . . . . . . . .18V
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Power Dissipation (Notes 1, 2)
Thermal Resistance (Typical, Note 3)
θJA (oC/W) θJC (oC/W)
CERDIP Package . . . . . . . . . . . . . . . . . . . .
85
25
PDIP Package . . . . . . . . . . . . . . . . . . . . . . .
90
N/A
SOIC Package . . . . . . . . . . . . . . . . . . . . . . .
100
N/A
Maximum Junction Temperature (Ceramic Package) . . . . . . . . . . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range
HA-4900-2, HA-4902-2 . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
HA-4905-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC
Die Characteristics
Back Side Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VNumber of Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Die Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 mils x 105 mils
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Maximum power dissipation, including output load, must be designed to maintain the junction temperature below 175oC for ceramic packages, and below
150oC for plastic packages.
2. Total Power Dissipation (T.P.D.) is the sum of individual dissipation contributions of V+, V- and VLOGIC shown in curves of Power Dissipation vs Supply
Voltages (see Performance Curves). The calculated T.P.D. is then located on the graph of Maximum Allowable Package Dissipation vs Ambient Temperature
to determine ambient temperature operating limits imposed by the calculated T.P.D. (See Performance Curves). For instance, the combination of +15V, -15V,
+5V, 0V (V+, V-, VLOGIC+, VLOGIC-) gives a T.P.D. of 350mW, the combination +15V, -15V, +15V, 0V gives a T.P.D. of 450mW.
3. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
VSUPPLY = ±15V, VLOGIC+ = 5V, VLOGIC- = GND
HA-4902-2
-55oC to 125oC
HA-4900-2
-55oC to 125oC
HA-4905-5
0oC to 75oC
TEMP
(oC)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
25
-
2
3
-
2
5
-
4
7.5
mV
Full
-
-
4
-
-
8
-
-
10
mV
25
-
10
25
-
10
35
-
25
50
nA
Full
-
-
35
-
-
45
-
-
70
nA
25
-
50
75
-
50
150
-
100
150
nA
Full
-
-
150
-
-
200
-
-
300
nA
25
-
-
VIO +
0.3
-
-
VIO +
0.5
-
-
VIO +
0.5
mV
Full
-
-
VIO +
0.4
-
-
VIO +
0.6
-
-
VIO +
0.7
mV
Full
V-
-
(V+) 2.4
V-
-
(V+) 2.6
V-
-
(V+) 2.4
V
25
-
250
-
-
250
-
-
250
-
MΩ
Large Signal Voltage Gain
25
-
400
-
-
400
-
-
400
-
kV/V
Response Time (tPD(0))
(Note 7)
25
-
130
200
-
130
200
-
130
200
ns
Response Time (tPD(1))
(Note 7)
25
-
180
215
-
180
215
-
180
215
ns
PARAMETER
INPUT CHARACTERISTICS
Offset Voltage (Note 4)
Offset Current
Bias Current (Note 5)
Input Sensitivity (Note 6)
Common Mode Range
Differential Input Resistance
TRANSFER CHARACTERISTICS
OUTPUT CHARACTERISTICS
Output Voltage Level
2
HA-4900, HA-4902, HA-4905
Electrical Specifications
VSUPPLY = ±15V, VLOGIC+ = 5V, VLOGIC- = GND (Continued)
HA-4902-2
-55oC to 125oC
HA-4900-2
-55oC to 125oC
HA-4905-5
0oC to 75oC
TEMP
(oC)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Logic “Low State” (VOL)
(Note 8)
Full
-
0.2
0.4
-
0.2
0.4
-
0.2
0.4
V
Logic “High State” (VOH)
(Note 8)
Full
3.5
4.2
-
3.5
4.2
-
3.5
4.2
-
V
ISINK
Full
3.0
-
-
3.0
-
-
3.0
-
-
mA
ISOURCE
Full
3.0
-
-
3.0
-
-
3.0
-
-
mA
PARAMETER
Output Current
POWER SUPPLY CHARACTERISTICS
Supply Current, IPS (+)
25
-
6.5
20
-
6.5
20
-
7
20
mA
Supply Current, IPS (-)
25
-
4
8
-
4
8
-
5
8
mA
Supply Current, IPS (Logic)
25
-
3.5
4
-
3.5
4
-
3.5
4
mA
VLOGIC+ (Note 2)
Full
0
-
+15.0
0
-
+15.0
0
-
+15.0
V
VLOGIC- (Note 2)
Full
-15.0
-
0
-15.0
-
0
-15.0
-
0
V
Supply Voltage Range
NOTES:
4. Minimum differential input voltage required to ensure a defined output state.
5. Input bias currents are essentially constant with differential input voltages up to ±9V. With differential input voltages from ±9V to ±15V, bias current on the
more negative input can rise to approximately 500μA. This will also cause higher supply currents.
6. VCM = 0V. Input sensitivity is the worst case minimum differential input voltage required to guarantee a given output logic state. This parameter includes the
effects of offset voltage and voltage gain.
7. For tPD(1); 100mV input step, -10mV overdrive. For tPD(0); -100mV input step, 10mV overdrive. Frequency ≈ 100Hz; Duty Cycle ≈ 50%; Inverting input
driven. See Figure 1 for Test Circuit. All unused inverting inputs tied to +5V.
8. For VOH and VOL: ISINK = ISOURCE = 3.0mA. For other values of VLOGIC; VOH (Min) = VLOGIC + -1.5V.
Test Circuit and Waveform
+15V
+5V
tPD(1)
tPD(0)
OVERDRIVE
VOUT
DUT
VTH = 0V
+
INPUT
100mV
100mV
VTH = 0V
OVERDRIVE
-15V
OUTPUT
1.5V
1.5V
tPD(1)
tPD(0)
t=0
FIGURE 1.
3
t=0
HA-4900, HA-4902, HA-4905
Schematic Diagram
R1
500Ω
R9
4kΩ
PR1
200kΩ
R10
4kΩ
Q1
Q11
Q2
R2
13kΩ
R3
1kΩ
R4
1kΩ
Q12
Q13
Q14
D11A
R6
2.5kΩ
R7
2.5kΩ
Q15
D4B
D4A
Q26
Q23
Q9D
Q20
Q36
Q5
BIAS 3
Q18
+IN
Q21
Q17
BIAS 4
D9A
Q9B
Q9A
Q9C
R20C
1kΩ
R20B
1kΩ
R20A
1kΩ
D29B
D35
-IN
Q22
Q33
Q30
Q34
R24
14kΩ
R22
100Ω
Q32
OUT
MN6
R23 MN5
100Ω
Q31
R15
8kΩ
MN2
Q10
R20D
1kΩ
Q29
D39
R16
540Ω
BIAS 1
VLOGIC+
R12
Q29A 8kΩ
Q38 Q28
Q37
Q7
Q4
R11
8kΩ
Q24 Q25
D45
Q19
BIAS 2
R18
664Ω
Q16
Q3
Q4C
V+
R5
360Ω
R21
1kΩ
R17
19kΩ
MN1
R14
5kΩ
VLOGICMN4
MN3
V-
ONE FOURTH ONLY
Applying the HA-4900 Series Comparators
Supply Connections
This device is exceptionally versatile in working with most available
power supplies. The voltage applied to the V+ and V- terminals
determines the allowable input signal range; while the voltage applied
to the VL+ and VL- determines the output swing. In systems where
dual analog supplies are available, these would be connected to V+
and V-, while the logic supply and return would be connected to
VLOGIC+ and VLOGIC -. The analog and logic supply commons can
be connected together at one point in the system, since the comparator
is immune to noise on the logic supply ground. A negative output
swing may be obtained by connecting VL+ to ground and VL- to a
negative supply. Bipolar output swings (15VP-P, Max) may be
obtained using dual supplies. In systems where only a single logic
supply is available (+5V to 15V), V+ and VLOGIC+ may be
connected together to the positive supply while V- and VLOGIC- are
grounded. If an input signal could swing negative with respect the Vterminal, a resistor should be connected in series with the input to limit
input current to < 5mA since the C-B junction of the input transistor
would be forward biased.
Unused Inputs
Inputs of unused comparator sections should be tied to a differential
voltage source to prevent output “chatter.”
Crosstalk
Simultaneous high frequency operation of all other channels in the
package will not affect the output logic state of a given channel,
provided that its differential input voltage is sufficient to define a
given logic state (ΔVIN ≥ ±VOS). Low level or high impedance
input lines should be shielded from other signal sources to reduce
crosstalk and interference.
Power Supply Decoupling
4
Decouple all power supply lines with 0.01μF ceramic capacitors to
ground line located near the package to reduce coupling between
channels or from external sources.
Response Time
Fast rise time (<200ns) input pulses of several volts amplitude may
result in delay times somewhat longer than those illustrated for
100mV steps. Operating speed is optimized by limiting the
maximum differential input voltage applied, with resistor-diode
clamping networks.
Typical Applications
Data Acquisition System
In this circuit the HA-4900 series is used in conjunction with a D
to A converter to form a simple, versatile, multi-channel analog
input for a data acquisition system. In operation the processor first
sends an address to the D to A, then the processor reads the digital
word generated by the comparator outputs. To perform a simple
comparison, the processor sets the D to A to a given reference
level, then examines one or more comparator outputs to determine
if their inputs are above or below the reference. A window
comparison consists of two such cycles with 2 reference levels set
by the D to A. One way to digitize the inputs would be for the
processor to increment the D to A in steps. The D to A address, as
each comparator switches, is the digitized level of the input. While
stairstepping the D to A is slower than successive approximation,
all channels are digitized during one staircase ramp.
HA-4900, HA-4902, HA-4905
LATCH
Window Detector
INTERFACE
MEMORY
ANALOG
INPUTS
INTERFACE
D/A
+15V
MICROPROCESSOR
COMPARATORS
ANALOG INPUT MODULE
The high switching speed, low offset current and low offset
voltage of the HA-4900 series makes this window detector circuit
extremely well suited to applications requiring fast, accurate,
decision-making. The circuit above is ideal for industrial process
system feedback controllers or “out-of-limit” alarm indicators.
INPUT
+
HIGH REF
-
HIGH
IN
WINDOW
-15V
The HA-4900 series comparators can be used as versatile logic
interface devices as shown in the circuits above. Negative logic
devices may also be interfaced with appropriate supply
connections. If separate supplies are used for V- and VLOGIC-,
these logic level translators will tolerate several volts of ground
line differential noise.
1/4 HD-74C02
+
LOW REF
LOW
1/2 HA-4900
V+
+5.0V
+5V TO +15V
VL+
+5.0V
4.7kΩ
+
1/4
HA-4900
+
1/4
HA-4900
-
10kΩ
1N914s
Oscillator/Clock Generator
This self-starting fixed frequency oscillator circuit gives excellent
frequency stability. R1 and C1 comprise the frequency determining
network while R2 provides the regenerative feedback. Diode D1
enhances the stability by compensating for the difference between
VOH and VSUPPLY. In applications where a precision clock
generator up to 100kHz is required, such as in automatic test
equipment, C1 may be replaced by a crystal.
10kΩ
+
1/4
HA-4900
+
1/4
HA-4900
R2
150kΩ
V+
-
-
1N914
TTL TO CMOS
D1
+
1/4
HA-4900
RS-232 To CMOS Line Receiver
This RS-232 type line receiver to drive CMOS logic uses a Schmitt
trigger feedback network to give about 1V input hysteresis for
added noise immunity. A possible problem in an interface which
connects two equipments, each plugged into a different AC
receptacle, is that the power line voltage may appear at the receiver
input when the interface connection is made or broken. The two
diodes and a 3W input resistor will protect the inputs under these
conditions.
+10V
1/4
HA-4900
+
56kΩ
51kΩ
1N4001s
1kΩ
5
V+
150kΩ
CMOS TO TTL
1kΩ
+5.0V
PROCESSOR
Logic Level Translators
4.7kΩ
3W
VL+
150kΩ
-
C1
1
f ≈ ---------------------2.1R 1 C 1
R1
50kΩ
Schmitt Trigger (Zero Crossing Detector With Hysteresis)
This circuit has a 100mV hysteresis which can be used in
applications where very fast transition times are required at the
output even though the signal input is very slow. The hysteresis
loop also reduces false triggering due to noise on the input. The
waveforms below show the trip points developed by the hysteresis
loop.
HA-4900, HA-4902, HA-4905
+15V
+5V
VOH
1/4
HA-4900
+
VOH ≈ 4.2V
R2
2kΩ
VTRIP+
0V
-15V
VTRIP-
R3
13kΩ
R1
100Ω
-15V
INPUT TO OUTPUT WAVEFORM SHOWING HYSTERESIS TRIP
POINTS
Typical Performance Curves
TA = 25oC, VS = ±15V, VLOGIC+ = 5V, VLOGIC- = 0V, Unless Otherwise Specified
INPUT OFFSET CURRENT (nA)
80
60
40
20
15
10
5
0
0
-55
-25
0
25
50
75
100
-55
125
-25
TEMPERATURE (oC)
0
25
60
40
20
-12
-9
-6
-3
0
+3
+6
+9
+12
+15
COMMON MODE INPUT VOLTAGE
FIGURE 4. INPUT BIAS CURRENT vs COMMON MODE INPUT VOLTAGE (VDIFF = 0V)
6
75
100
125
FIGURE 3. INPUT OFFSET CURRENT vs TEMPERATURE
80
0
-15
50
TEMPERATURE (oC)
FIGURE 2. INPUT BIAS CURRENT vs TEMPERATURE
INPUT BIAS CURRENT (nA)
INPUT BIAS CURRENT (nA)
100
HA-4900, HA-4902, HA-4905
Typical Performance Curves
10
SUPPLY CURRENT (mA)
7
VS = ±15V
VLOGIC+ = 5V
VLOGIC- = GND
IPSL, VOUT = H
6
IPS+, VOUT = L
8
SUPPLY CURRENT (mA)
12
TA = 25oC, VS = ±15V, VLOGIC+ = 5V, VLOGIC- = 0V, Unless Otherwise Specified (Continued)
IPS+, VOUT = H
6
IPS-, VOUT = L
4
IPS-, VOUT = H
IPSL, VOUT = L
5
IPS+, VOUT = H
4
IPS+, VOUT = L
3
IPSL, VOUT = L
2
2
0
-50
-25
0
V+ = 5V, V- = GND
VLOGIC+ = 5V
VLOGIC- = GND
1
IPSL, VOUT = H
25
50
75
100
0
125
-50
TEMPERATURE (oC)
FIGURE 5. SUPPLY CURRENT vs TEMPERATURE (FOR ±15V
SUPPLIES AND +5V LOGIC SUPPLY)
0
25
50
TEMPERATURE (oC)
75
100
125
FIGURE 6. SUPPLY CURRENT vs TEMPERATURE (FOR SINGLE
+5V OPERATION)
5
5
OVERDRIVE = 20mV
3
OVERDRIVE = 5mV
4
OVERDRIVE = 2mV
2
OVERDRIVE = 20mV
VOUT (V)
4
3
OVERDRIVE = 5mV
2
1
1
0
0
0
+100mV
OVERDRIVE = 2mV
VIN
VIN
VOUT (V)
-25
0
-100mV
0
100
200
TIME (ns)
300
0
400
100
200
TIME (ns)
300
400
FIGURE 7. RESPONSE TIME FOR VARIOUS INPUT OVERDRIVES
2.0
250
CERDIP
POWER DISSIPATION (mW)
PACKAGE DISSIPATION (W)
1.75
1.50
1.25
1.0
PDIP
0.75
0.50
SOIC
200
150
V+
100
V-
50
0.25
VLOGIC+
0
0
0
25
50
75
100
125
TEMPERATURE (oC)
FIGURE 8. MAXIMUM PACKAGE DISSIPATION vs AMBIENT
TEMPERATURE
7
0
2
4
6
8
10
SUPPLY VOLTAGE (V)
12
14
FIGURE 9. POWER DISSIPATION vs SUPPLY VOLTAGE (NO
LOAD CONDITION)
HA-4900, HA-4902, HA-4905
Dual-In-Line Plastic Packages (PDIP)
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
N
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AE
D
BASE
PLANE
A2
-CSEATING
PLANE
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M C A B S
C
L
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
B1
0.045
0.070
1.15
1.77
8, 10
eA
C
0.008
0.014
C
D
0.735
0.775
18.66
eB
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.
e
0.204
0.100 BSC
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
eA
0.300 BSC
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95.
eB
-
4. Dimensions A, A1 and L are measured with the package seated in JEDEC
seating plane gauge GS-3.
L
0.115
N
0.355
19.68
2.54 BSC
7.62 BSC
0.430
-
0.150
2.93
16
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to
datum -C- .
10.92
3.81
16
5
6
7
4
9
Rev. 0 12/93
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must
be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will
have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
8
HA-4900, HA-4902, HA-4905
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
LEAD FINISH
c1
-D-
-A-
BASE
METAL
SYMBOL
E
M
-Bbbb S
C A-B S
-C-
0.58
3
1.14
1.65
-
0.045
0.58
1.14
4
0.018
0.20
0.46
2
0.008
0.015
0.20
-
0.840
0.014
0.023
b2
0.045
0.065
b3
0.023
c
0.008
c1
D
E
0.220
α
aaa M C A - B S
c
e
D S
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be measured
at the centroid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial
lead paddle. For this configuration dimension b3 replaces dimension
b2.
5. This dimension allows for off-center lid, meniscus, and glass overrun.
6. Dimension Q shall be measured from the seating plane to the base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
9
0.36
b1
eA/2
10. Controlling dimension: INCH.
2
0.36
eA
D S
-
0.66
0.026
A A
ccc M C A - B S
5.08
0.200
A
e
-
0.014
b2
b
MAX
b
L
S1
MIN
A
Q
SEATING
PLANE
MAX
M
(b)
D
BASE
PLANE
MILLIMETERS
MIN
b1
SECTION A-A
D S
INCHES
(c)
0.310
5.59
0.100 BSC
NOTES
0.38
3
21.34
5
7.87
5
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
α
90o
105o
90o
-
7
105o
-
aaa
-
0.015
-
0.38
-
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
N
16
16
8
Rev. 0 4/94
HA-4900, HA-4902, HA-4905
Small Outline Plastic Packages (SOIC)
M16.3 (JEDEC MS-013-AA ISSUE C)
N
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
-B1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.3977
0.4133
10.10
10.50
3
E
0.2914
0.2992
7.40
7.60
4
e
α
B S
0.050 BSC
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
10
-
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
α
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
1.27 BSC
H
N
NOTES:
MILLIMETERS
16
0°
16
8°
0°
7
8°
Rev. 1 6/05
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