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EL5411T
Features
The EL5411T is a high voltage rail-to-rail input-output
amplifier with low power consumption. The EL5411T
contains four amplifiers. Each amplifier exhibits beyond
the rail input capability, rail-to-rail output capability and
is unity gain stable.
• 60MHz (-3dB) Bandwidth
The maximum operating voltage range is from 4.5V to
19V. It can be configured for single or dual supply
operation, and typically consumes only 3mA per
amplifier. The EL5411T has an output short circuit
capability of ±300mA and a continuous output current
capability of ±70mA.
The EL5411T features a high slew rate of 100V/µs, and
fast settling time. Also, the device provides common
mode input capability beyond the supply rails, rail-to-rail
output capability, and a bandwidth of 60MHz (-3dB). This
enables the amplifiers to offer maximum dynamic range
at any supply voltage. These features make the EL5411T
an ideal amplifier solution for use in TFT-LCD panels as a
VCOM driver or static gamma buffer, and in high speed
filtering and signal conditioning applications. Other
applications include battery power and portable devices,
especially where low power consumption is important.
The EL5411T is available in a 14 Ld HTSSOP and a
space saving thermally enhanced 16 Ld 4mmx4mm
TQFN package. The device operates over an ambient
temperature range of -40°C to +85°C.
• 4.5V to 19V Maximum Supply Voltage Range
• 100V/µs Slew Rate
• 3mA Supply Current (per Amplifier)
• ±70mA Continuous Output Current
• ±300mA Output Short Circuit Current
• Unity-gain Stable
• Beyond the Rails Input Capability
• Rail-to-rail Output Swing
• Built-in Thermal Protection
• -40°C to +85°C Ambient Temperature Range
• Pb-Free (RoHS Compliant)
Applications
• TFT-LCD Panels
• VCOM Amplifiers
• Static Gamma Buffers
• Drivers for A/D Converters
• Data Acquisition
• Video Processing
• Audio Processing
• Active Filters
• Test Equipment
• Battery-powered Applications
• Portable Equipment
Pin Configurations
EL5411T
(14 LD HTSSOP)
TOP VIEW
VOUTA 1
13 NC
14 VOUTD
15 VOUTA
16 NC
EL5411T
(16 LD 4X4 TQFN)
TOP VIEW
VINA- 1
VINA- 2
12 VIND-
VINA+ 2
11 VIND+
THERMAL
PAD
VS+ 3
10 VS9 VINC+
VINC- 8
VOUTC 7
VOUTB 6
VINB- 5
VINB+ 4
THERMAL PAD
CONNECTS TO VS-
August 3, 2010
FN6837.2
1
14 VOUTD
VINA+ 3
13 VIND+
+
VS+ 4
11 VS-
VINB+ 5
VINB- 6
VOUTB 7
12 VIND+
10 VINC+
+
-
+
-
9 VINC8 VOUTC
THERMAL PAD
CONNECTS TO VS-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL5411T
60MHz Rail-to-Rail Input-Output Operational Amplifier
EL5411T
Pin Descriptions
EL5411T
(14 LD
HTSSOP)
EL5411T
(16 LD
TQFN)
PIN
NAME
1
15
VOUTA
Amplifier A output
(Reference Circuit 1)
2
1
VINA-
Amplifier A inverting input
(Reference Circuit 2)
3
2
VINA+
Amplifier A non-inverting input
(Reference Circuit 2)
4
3
VS+
5
4
VINB+
Amplifier B non-inverting input
(Reference Circuit 2)
6
5
VINB-
Amplifier B inverting input
(Reference Circuit 2)
7
6
VOUTB
Amplifier B output
(Reference Circuit 1)
8
7
VOUTC
Amplifier C output
(Reference Circuit 1)
9
8
VINC-
Amplifier C inverting input
(Reference Circuit 2)
10
9
VINC+
Amplifier C non-inverting input
(Reference Circuit 2)
11
10
VS-
12
11
VIND+
Amplifier D non-inverting input
(Reference Circuit 2)
13
12
VIND-
Amplifier D inverting input
(Reference Circuit 2)
14
14
VOUTD
Amplifier D output
(Reference Circuit 1)
13, 16
NC
pad
Thermal Pad
pad
FUNCTION
EQUIVALENT CIRCUIT
Positive power supply
Negative power supply (connects to GND
for single supply operation)
Not connected
Functions as a heat sink.
Connects to most negative potential, VS-
VS+
VS+
VOUT
VIN
VS-
GND
VS-
CIRCUIT 1
CIRCUIT 2
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
PACKAGE
(Pb-Free)
PKG. DWG. #
EL5411TIREZ
5411TIRE Z
14 Ld HTSSOP
M14.173A
EL5411TILZ
5411TIL Z
16 Ld TQFN
L16.4x4F
NOTES:
1. Add “T7” or “T13” suffix for Tape and Reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for EL5411T. For more information on MSL please see
techbrief TB363.
2
FN6837.2
EL5411T
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage between VS+ and VS- . . . . . . . . . . . .+19.8V
Input Voltage Range (VINx+, VINx-) . VS- - 0.5V, VS+ + 0.5V
Input Differential Voltage (VINx+ - VINx-) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . (VS+ + 0.5V)-(VS- - 0.5V)
Maximum Continuous Output Current . . . . . . . . . . . ±70mA
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . 3000V
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
14 Ld HTSSOP (Notes 4, 5) . . .
38
8
16 Ld TQFN (Notes 4, 5) . . . . .
40
8.5
Storage Temperature . . . . . . . . . . . . . . . . -65°C to +150°C
Ambient Operating Temperature . . . . . . . . . -40°C to +85°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C
Power Dissipation . . . . . . . . . . . . . . . See Figures 32 and 33
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = -5V, RL = 1k to 0V, TA = +25°C, Unless Otherwise Specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
17
mV
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
VCM = 0V
3.5
TCVOS
Average Offset Voltage Drift
(Note 6)
14 LD HTSSOP package
26
µV/°C
16 LD TQFN package
4
µV/°C
IB
Input Bias Current
VCM = 0V
2
RIN
Input Impedance
1
G
CIN
Input Capacitance
2
pF
CMIR
Common-Mode Input Range
CMRR
Common-Mode Rejection Ratio
For VIN from -5.5V to 5.5V
50
73
dB
AVOL
Open-Loop Gain
-4.5V VOUTx 4.5V
62
78
dB
-5.5
60
+5.5
nA
V
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -5mA
VOH
Output Swing High
IL = +5mA
ISC
Short-Circuit Current
VCM = 0V, Source: VOUTx short to VS-,
Sink: VOUTx short to VS+
IOUT
Output Current
-4.94
4.85
-4.85
V
4.94
V
±300
mA
±70
mA
POWER SUPPLY PERFORMANCE
(VS+) - (VS-)
Supply Voltage Range
IS
Supply Current
VCM = 0V, No load
PSRR
Power Supply Rejection Ratio
Supply is moved from ±2.25V to ±9.5V
4.5
11
60
19
V
15
mA
75
dB
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 7)
-4.0V VOUTx 4.0V, 20% to 80%
100
V/µs
tS
Settling to +0.1% (Note 8)
AV = +1, VOUTx = 2V step,
RL = 1k1k (probe), CL = 1.5pF
85
ns
BW
-3dB Bandwidth
RF = 1kCL = 1.5pF
60
MHz
GBWP
Gain-Bandwidth Product
AV = -10, RF = 1kRG = 100
RL = 1k1k (probe), CL = 1.5pF
32
MHz
3
FN6837.2
EL5411T
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = -5V, RL = 1k to 0V, TA = +25°C, Unless Otherwise Specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
PM
Phase Margin
AV = -10, RF = 1kRG = 100
RL = 1k1k (probe), CL = 1.5pF
50
°
CS
Channel Separation
f = 5MHz
90
dB
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = 0V, RL = 1k to 2.5V, TA = +25°C, Unless Otherwise Specified.
DESCRIPTION
CONDITION
MIN
TYP
MAX UNIT
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
VCM = 2.5V
3.5
TCVOS
Average Offset Voltage Drift
(Note 6)
14 LD HTSSOP package
23
µV/°C
16 LD TQFN package
3
µV/°C
IB
Input Bias Current
VCM = 2.5V
2
RIN
Input Impedance
1
G
CIN
Input Capacitance
2
pF
CMIR
Common-Mode Input Range
CMRR
Common-Mode Rejection Ratio
For VIN from -0.5V to 5.5V
45
68
dB
AVOL
Open-Loop Gain
0.5V VOUTx 4.5V
62
82
dB
-0.5
17
60
+5.5
mV
nA
V
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -4.2mA
VOH
Output Swing High
IL = +4.2mA
ISC
Short-circuit Current
VCM = 2.5V, Source: VOUTx short to VS-,
Sink: VOUTx short to VS+
IOUT
Output Current
60
4.85
150
mV
4.94
V
±110
mA
±70
mA
POWER SUPPLY PERFORMANCE
(VS+) - (VS-)
Supply Voltage Range
IS
Supply Current
VCM = 2.5V, No load
PSRR
Power Supply Rejection Ratio
Supply is moved from 4.5V to 19V
4.5
12
60
19
V
15
mA
75
dB
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 7)
1V VOUTx 4V, 20% to 80%
75
V/µs
tS
Settling to +0.1% (Note 8)
AV = +1, VOUTx = 2V step,
RL = 1k1k (probe), CL = 1.5pF
90
ns
BW
-3dB Bandwidth
RF = 1kCL = 1.5pF
60
MHz
GBWP
Gain-Bandwidth Product
AV = -10, RF = 1kRG = 100
RL = 1k1k (probe), CL = 1.5pF
32
MHz
PM
Phase Margin
AV = -10, RF = 1kRG = 100
RL = 1k1k (probe), CL = 1.5pF
50
°
CS
Channel Separation
f = 5MHz
90
dB
4
FN6837.2
EL5411T
Electrical Specifications
PARAMETER
VS+ = +18V, VS- = 0V, RL = 1k to 9V, TA = +25°C, Unless Otherwise Specified.
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
17
mV
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
VCM = 9V
3.5
TCVOS
Average Offset Voltage Drift
(Note 6)
14 LD HTSSOP package
21
µV/°C
16 LD TQFN package
5
µV/°C
IB
Input Bias Current
VCM = 9V
2
RIN
Input Impedance
1
G
CIN
Input Capacitance
2
pF
CMIR
Common-Mode Input Range
CMRR
Common-Mode Rejection Ratio
For VIN from -0.5V to 18.5V
53
75
dB
AVOL
Open-Loop Gain
0.5V VOUTx 17.5V
62
104
dB
-0.5
60
+18.5
nA
V
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -6mA
VOH
Output Swing High
IL = +6mA
ISC
Short-circuit Current
VCM = 9V, Source: VOUTx short to VS-,
Sink: VOUTx short to VS+
IOUT
Output Current
80
17.85
150
mV
17.92
V
±300
mA
±70
mA
POWER SUPPLY PERFORMANCE
(VS+) - (VS-)
Supply Voltage Range
IS
Supply Current
VCM = 9V, No load
PSRR
Power Supply Rejection Ratio
Supply is moved from 4.5V to 19V
4.5
12.3
60
19
V
15
mA
75
dB
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 7)
1V VOUTx 17V, 20% to 80%
100
V/µs
tS
Settling to +0.1% (Note 8)
AV = +1, VOUTx = 2V step,
RL = 1k1k (probe), CL = 1.5pF
100
ns
BW
-3dB Bandwidth
RF = 1kCL = 1.5pF
60
MHz
GBWP
Gain-Bandwidth Product
AV = -10, RF = 1kRG = 100
RL = 1k1k (probe), CL = 1.5pF
32
MHz
PM
Phase Margin
AV = -10, RF = 1kRG = 100
RL = 1k1k (probe), CL = 1.5pF
50
°
CS
Channel Separation
f = 5MHz
90
dB
NOTES:
6. Measured over -40°C to +85°C ambient operating temperature range. See the typical TCVOS production distribution shown in
the “Typical Performance Curves” on page 6.
7. Typical slew rate is an average of the slew rates measured on the rising (20% to 80%) and the falling (80% to 20%) edges
of the output signal.
8. Settling time measured as the time from when the output level crosses the final value on rising/falling edge to when the output
level settles within a ±0.1% error band. The range of the error band is determined by: Final Value(V)±[Full Scale(V)*0.1%].
5
FN6837.2
EL5411T
Typical Performance Curves
TYPICAL
PRODUCTION
DISTRIBUTION
VS = ±5V
TA = +25°C
800
700
600
500
400
300
200
100
0
-15-13-11 -9 -7 -5 -3 -1 1
3
5
7
16
QUANTITY (AMPLIFIERS)
QUANTITY (AMPLIFIERS)
900
12
10
8
6
4
2
0
9 11 13 15
3
INPUT OFFSET VOLTAGE (mV)
15
10
5
0
0
1
2
3
4
5
6
7
8
INPUT OFFSET VOLTAGE (mV)
QUANTITY (AMPLIFIERS)
TYPICAL
PRODUCTION
DISTRIBUTION
20
15
33
39
45
51
57
VS = ±5V
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-50
9 10 11 12 13 14 15
0
50
100
150
TEMPERATURE (°C)
FIGURE 3. INPUT OFFSET VOLTAGE DRIFT (TQFN)
FIGURE 4. INPUT OFFSET VOLTAGE vs TEMPERATURE
VS = ±5V
7.5
7.0
6.5
0
50
100
150
TEMPERATURE (°C)
FIGURE 5. INPUT BIAS CURRENT vs TEMPERATURE
6
OUTPUT HIGH VOLTAGE (V)
4.96
8.0
INPUT BIAS CURRENT (nA)
27
-0.5
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
6.0
-50
21
FIGURE 2. INPUT OFFSET VOLTAGE DRIFT (HTSSOP)
0.0
VS = ±5V
-40°C to +85°C
9
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
FIGURE 1. INPUT OFFSET VOLTAGE DISTRIBUTION
25
TYPICAL
PRODUCTION
DISTRIBUTION
VS = ±5V
-40°C to +85°C
14
VS = ±5V
IOUT = +5mA
4.94
4.92
4.90
4.88
-50
0
50
100
150
TEMPERATURE (°C)
FIGURE 6. OUTPUT HIGH VOLTAGE vs TEMPERATURE
FN6837.2
EL5411T
Typical Performance Curves (Continued)
-4.91
120
VS = ±5V
IOUT = -5mA
OPEN LOOP GAIN (dB)
OUTPUT LOW VOLTAGE (V)
-4.90
-4.92
-4.93
-4.94
-4.95
-4.96
-50
0
50
100
VS = ±5V
RL = 1k
100
80
60
40
20
-50
150
0
50
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 7. OUTPUT LOW VOLTAGE vs TEMPERATURE
2.85
SUPPLY CURRENT (mA)
SLEW RATE (V/µs)
120
110
100
90
80
70
60
-50
0
50
100
150
VS = ±5V
NO LOAD
INPUTS AT GND
2.80
2.75
2.70
2.65
-50
0
50
SLEW RATE (V/µs)
SUPPLY CURRENT (mA)
140
TA = +25°C
NO LOAD
INPUTS AT GND
3.0
2.5
2.0
2.5
3.5
4.5
5.5
6.5
7.5
8.5
SUPPLY VOLTAGE (±V)
FIGURE 11. SUPPLY CURRENT PER AMPLIFIER vs
SUPPLY VOLTAGE
7
150
FIGURE 10. SUPPLY CURRENT PER AMPLIFIER vs
TEMPERATURE
FIGURE 9. SLEW RATE vs TEMPERATURE
3.5
100
TEMPERATURE (°C)
TEMPERATURE (°C)
4.0
150
FIGURE 8. OPEN-LOOP GAIN vs TEMPERATURE
130
VS = ±5V
RL = 1k
100
9.5
TA = +25°C
AV = 1
RL = 1k
CL = 8pF
120
100
80
60
40
2
4
6
10
8
SUPPLY VOLTAGE (±V)
FIGURE 12. SLEW RATE vs SUPPLY VOLTAGE
FN6837.2
EL5411T
Typical Performance Curves (Continued)
100
120
100
80
60
40
2
4
6
80
160
GAIN
60
PHASE
40
VS = ±5V
RF = 5k
RG = 100
RL = 1k
CL = 8pF
20
0
100
SUPPLY VOLTAGE (±V)
100
200
10
40
80
40
VS = ±5V
RF = 1k
RG = 100
RL = 1k|| 1k(PROBE)
CL = 1.5pF
100
1k
10k
100k
6
4
GAIN (dB)
120
GAIN
PHASE (°)
OPEN LOOP GAIN (dB)
160
-20
10
10M
-40
100M
560
150
1M
47pF
0
-5
-10
-15
-20
100k
1M
10M
FREQUENCY (Hz)
100M
FIGURE 17. FREQUENCY RESPONSE FOR VARIOUS CL
8
100M
FIGURE 16. FREQUENCY RESPONSE FOR VARIOUS RL
10pF
5
10M
FREQUENCY (Hz)
450
100pF
-40
100M
0
-10
100k
OUTPUT IMPEDANCE ()
GAIN (dB)
10
10M
-2
-8
1M
1M
1k
-6
20
1000pF
100k
2
FREQUENCY (Hz)
VS = ±5V
AV = 1
RL = 1k
10k
-4
0
FIGURE 15. OPEN LOOP GAIN AND PHASE vs
FREQUENCY
15
1k
VS = ±5V
AV = 1
CL = 1.5pF
RL || 1k(PROBE)
8
80
0
0
FIGURE 14. OPEN LOOP GAIN AND PHASE vs
FREQUENCY
PHASE
20
40
FREQUENCY (Hz)
FIGURE 13. OPEN LOOP GAIN vs SUPPLY VOLTAGE
60
120
80
-20
10
10
8
200
PHASE (°)
TA = +25°C
RL = 1k
OPEN LOOP GAIN (dB)
OPEN LOOP GAIN (dB)
140
400
350
300
VS = ±5V
AV = 1
RL = OPEN
VOUTx = +15dBm
250
200
150
100
50
0
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 18. CLOSED LOOP OUTPUT IMPEDANCE vs
FREQUENCY
FN6837.2
EL5411T
12
-30
10
-40
DISTORTION (dBc)
MAXIMUM OUTPUT SWING (VP-P)
Typical Performance Curves (Continued)
8
6
4
2
VS = ±5V
AV = 1
RL = 1k
DISTORTION <1%
0
10k
100k
1M
10M
-50
-60
3rd HD
-70
VS = ±5V
AV = 2
RL = 1k
fIN= 1MHz
-80
-90
100M
2nd HD
2
0
FREQUENCY (Hz)
FIGURE 19. MAXIMUM OUTPUT SWING vs
FREQUENCY
0
-10
-10
VS = ±5V
TA = +25°C
-40
-50
-60
-30
-40
-50
-60
-70
-70
-80
-80
-90
1k
-90
1k
100k
1M
10M
100M
PSRR+
PSRR10k
1M
10M
100M
FIGURE 22. PSRR vs FREQUENCY
FIGURE 21. CMRR vs FREQUENCY
1000
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
-20
TA = +25°C
-40
100
XTALK(dB)
VOLTAGE NOISE (nV/Hz)
10
-20
-30
10
MEASURED CH A TO D, OR B TO C
OTHER COMBINATIONS YIELD
IMPROVED REJECTION
-60
-80
-100
-120
1
100
8
0
VS = ±5V
TA = +25°C
VINx = -10dBm
10k
6
FIGURE 20. HARMONIC DISTORTION vs VOP-P
PSRR (dB)
CMRR (dB)
-20
4
OUTPUT VOLTAGE (VOP-P)
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 23. INPUT VOLTAGE NOISE SPECTRAL
DENSITY vs FREQUENCY
9
100M
-140
10k
VS = ±5V
AV = 1
VINx = 0dBm
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 24. CHANNEL SEPARATION vs FREQUENCY
FN6837.2
EL5411T
Typical Performance Curves (Continued)
80
5
VS = ±5V
TA = +25°C
AV = 1
RL = 1k
VINx = ±50mV
4
3
STEP SIZE (V)
OVERSHOOT (%)
100
60
40
2
VS = ±5V
TA = +25°C
AV = 1
RL= 1k|| 1k(PROBE)
CL =1.5pF
1
0
-1
-2
-3
20
-4
0
10
100
-5
70
1k
80
SETTLING TIME (ns)
LOAD CAPACITANCE (pF)
FIGURE 25. SMALL-SIGNAL OVERSHOOT vs LOAD
CAPACITANCE
FIGURE 26. STEP SIZE vs SETTLING TIME
VS = ±5V
TA = +25°C
AV = 1
RL= 1k|| 1k(PROBE)
CL = 1.5pF
50mV/DIV
1V/DIV
6V STEP
90
VS = ±5V
TA = +25°C
AV = 1
RL= 1k|| 1k(PROBE)
CL = 1.5pF
100mV STEP
50ns/DIV
50ns/DIV
FIGURE 27. LARGE SIGNAL TRANSIENT RESPONSE
FIGURE 28. SMALL SIGNAL TRANSIENT RESPONSE
EL5411T
(14 LD HTSSOP shown)
1
VOUTA
CLA
RLA
VOUTA
VOUTD
14
0
2
3
VINA+
RLD
0
VINA-
VIND-
VINA+
VIND+
13
12
VIND+
49.9
49.9
4
VS+ +
4.7µF
Vs+
Vs-
0.1µF
5
VINB+
49.9
6
0
VOUTB
CLB
VOUTD
CLD
7
11
0.1µF
VINB+
VINBVOUTB
VINC+
VINCVOUTC
+
VS4.7µF
10
VINC+
49.9
9
0
8
VOUTC
RLC
RLB
CLC
THERMAL PAD
CONNECTED TO VS-
FIGURE 29. BASIC TEST CIRCUIT
10
FN6837.2
EL5411T
Operating Voltage, Input and Output
Capability
The EL5411T can operate on a single supply or dual
supply configuration. The EL5411T operating voltage
ranges from a minimum of 4.5V to a maximum of 19V.
This range allows for a standard 5V (or ±2.5V) supply
voltage to dip to -10%, or a standard 18V (or ±9V) to
rise by +5.5% without affecting performance or
reliability.
The input common-mode voltage range of the EL5411T
extends 500mV beyond the supply rails. Also, the
EL5411T is immune to phase reversal. However, if the
common mode input voltage exceeds the supply voltage
by more than 0.5V, electrostatic protection diodes in the
input stage of the device begin to conduct. Even though
phase reversal will not occur, to maintain optimal
reliability it is suggested to avoid input overvoltage
conditions. Figure 30 shows the input voltage driven
500mV beyond the supply rails and the device output
swinging between the supply rails.
The EL5411T output typically swings to within 50mV of
positive and negative supply rails with load currents of
±5mA. Decreasing load currents will extend the output
voltage range even closer to the supply rails. Figure 31
shows the input and output waveforms for the device in a
unity-gain configuration. Operation is from ±5V supply
with a 1k load connected to GND. The input is a 10VP-P
sinusoid and the output voltage is approximately 9.9VP-P.
Refer to the “Electrical Specifications” Table beginning on
page 3 for specific device parameters. Parameter
variations with operating voltage, loading and/or
temperature are shown in the “Typical Performance
Curves” on page 6.
11
OUTPUT
INPUT
10µs/DIV
FIGURE 30. OPERATION WITH BEYOND-THE-RAILS
INPUT
VS = ±5V, TA = +25°C, AV = 1,
VINx = 10VP-P, RL = 1kto GND
INPUT
The EL5411T features a high slew rate of 100V/µs, and
fast settling time. Also, the device provides common
mode input capability beyond the supply rails, rail-to-rail
output capability, and a bandwidth of 60MHz (-3dB). This
enables the amplifiers to offer maximum dynamic range
at any supply voltage.
OUTPUT
The EL5411T is a high voltage rail-to-rail input-output
amplifier with low power consumption. The EL5411T
contains four amplifiers. Each amplifier exhibits beyond
the rail input capability, rail-to-rail output capability and
is unity gain stable.
1V/DIV
Product Description
VS = ±2.5V, TA = +25°C, AV = 1,
VINx = 6VP-P, RL = 1kto GND
5V/DIV
Applications Information
10µs/DIV
FIGURE 31. OPERATION WITH RAIL-TO-RAIL INPUT
AND OUTPUT
Output Current
The EL5411T is capable of output short circuit currents of
300mA (source and sink), and the device has built-in
protection circuitry which limits the short circuit current
to ±300mA (typical).
To maintain maximum reliability, the continuous output
current should never exceed ±70mA. This ±70mA limit is
determined by the characteristics of the internal metal
interconnects. Also, see “Power Dissipation” on page 12
for detailed information on ensuring proper device
operation and reliability for temperature and load
conditions.
Unused Amplifiers
It is recommended that any unused amplifiers be
configured as a unity gain follower. The inverting input
should be directly connected to the output and the
non-inverting input tied to the ground.
FN6837.2
EL5411T
Driving Capacitive Loads
• ISMAX = Maximum supply current per amplifier
A snubber is a shunt load consisting of a resistor in series
with a capacitor. An optimized snubber can improve the
phase margin and the stability of the EL5411T. The
advantage of a snubber circuit is that it does not draw
any DC load current or reduce the gain.
Another method to reduce peaking is to add a series output
resistor (typically between 1 to 10). Depending on the
capacitive loading, a small value resistor may be the most
appropriate choice to minimize any reduction in gain.
Power Dissipation
With the high-output drive capability of the EL5411T
amplifiers, it is possible to exceed the +150°C absolute
maximum junction temperature under certain load
current conditions. It is important to calculate the
maximum power dissipation of the EL5411T in the
application. Proper load conditions will ensure that the
EL5411T junction temperature stays within a safe
operating region.
The maximum power dissipation allowed in a package is
determined according to Equation 1:
T JMAX – T AMAX
P DMAX = -------------------------------------------- JA
(EQ. 1)
(ISMAX = EL5411T quiescent current ÷ 4)
• VOUT = Output voltage
• ILOAD = Load current
Device overheating can be avoided by calculating the
minimum resistive load condition, RLOAD, resulting in
the highest power dissipation. To find RLOAD set the two
PDMAX equations equal to each other and solve for
VOUT/ILOAD. Reference the package power dissipation
curves, Figures 32 and 33, for further information.
JEDEC JESD51-3 LOW EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
1.2
POWER DISSIPATION (W)
As load capacitance increases, the -3dB bandwidth will
decrease and peaking can occur. Depending on the
application, it may be necessary to reduce peaking and
to improve device stability. To improve device stability a
snubber circuit or a series resistor may be added to the
output of the EL5411T.
0.6
HTSSOP14
JA = +140°C/W
0.4
0.2
0.0
0
25
50
75 85
100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 32. PACKAGE POWER DISSIPATION vs
AMBIENT TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY (4-LAYER) TEST BOARD - EXPOSED
DIE PAD SOLDERED TO PCB PER JESD51-5
• TJMAX = Maximum junction temperature
• TAMAX = Maximum ambient temperature
• PDMAX = Maximum power dissipation allowed
The total power dissipation produced by an IC is the total
quiescent supply current times the total power supply
voltage, plus the power dissipation in the IC due to the
loads, or:
(EQ. 2)
when sourcing, and:
(EQ. 3)
POWER DISSIPATION (W)
4.0
• JA = Thermal resistance of the package
P DMAX = i  V S  I SMAX +  V OUT i – V S -   I LOAD i 
TQFN16
JA = +130°C/W
0.8 893mW
where:
P DMAX = i  V S  I SMAX +  V S + – V OUT i   I LOAD i 
962mW
1.0
3.29W
3.5
3.0
HTSSOP14
JA = +38°C/W
3.13W
2.5
TQFN16
JA = +40°C/W
2.0
1.5
1.0
0.5
0.0
0
25
50
75 85
100
125
150
AMBIENT TEMPERATURE (°C)
when sinking,
FIGURE 33. PACKAGE POWER DISSIPATION vs
AMBIENT TEMPERATURE
where:
• i = 1 to 4
(1, 2, 3, 4 corresponds to Channel A, B, C, D respectively)
• VS = Total supply voltage (VS+ - VS-)
• VS+ = Positive supply voltage
• VS- = Negative supply voltage
12
FN6837.2
EL5411T
Thermal Shutdown
The EL5411T has a built-in thermal protection which
ensures safe operation and prevents internal damage to
the device due to overheating. When the die temperature
reaches +165°C (typical) the device automatically shuts
OFF the outputs by putting them in a high impedance
state. When the die cools by +15°C (typical) the device
automatically turns ON the outputs by putting them in a
low impedance (normal) operating state.
Power Supply Bypassing and Printed Circuit
Board Layout
The EL5411T can provide gain at high frequency, so good
printed circuit board layout is necessary for optimum
performance. Ground plane construction is highly
recommended, trace lengths should be as short as
possible and the power supply pins must be well
bypassed to reduce any risk of oscillation.
13
For normal single supply operation (the VS- pin is
connected to ground) a 4.7µF capacitor should be placed
from VS+ to ground, then a parallel 0.1µF capacitor
should be connected as close to the amplifier as possible.
One 4.7µF capacitor may be used for multiple devices.
For dual supply operation the same capacitor
combination should be placed at each supply pin to
ground.
It is highly recommended that EL5411T exposed thermal
pad packages should always have the pad connected to
the lowest potential, VS-, to optimize thermal and
operating performance. PCB vias should be placed below
the device’s exposed thermal pad to transfer heat to the
VS- plane and away from the device.
FN6837.2
EL5411T
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
8/3/10
FN6837.2
Converted to New Intersil Data Sheet Template.
Changed Theta JC for 16 Ld TQFN in “Thermal Information” on page 3 from “9” to
“8.5”
Corrected Theta JA Note 4 from "JA is measured in free air with the component
mounted on a high effective thermal conductivity test board." to "JA is measured
in free air with the component mounted on a high effective thermal conductivity
test board with “direct attach” features."
Numbered notes in “Ordering Information” on page 2 and added MSL Note 3.
Moved “Ordering Information” from page 1 to page 2 and “Pin Configurations”
from page 2 to page 1. Moved “Pin Descriptions” from page 11 to page 2.
Added “Products” on page 14.
Updated “Package Outline Drawing” on page 15 (M14.173A). Added land pad for
exposed die attach pad.
10/8/09
FN6837.1
Updated Ordering Information by removing “contact factory for availability”.
add "vs FREQUENCY" to the plot titles in Fig 14,15,18,21,22,23,24:
Fig 21: changed y-axis label to read "CMRR (dB)"
Fig 22: changed y-axis label to read "PSRR (dB)"
Fig 26: changed label to read "STEP SIZE vs SETTLING TIME"
Changed 1st sentence in pages 1 and 12 from “The EL5411T is a low power, high
voltage rail-to-rail input-output amplifier” to “The EL5411T is a high voltage railto-rail input-output amplifier with low power consumption”.
Updated package outline drawing M14.173A to add land pattern and move
dimensions from table onto drawing
8/21/09
FN6837.0
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: EL5411T
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at
http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
FN6837.2
EL5411T
Package Outline Drawing
L16.4x4F
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 04/09
4X 1.95
4.00
12X 0.65
A
B
13
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
16
1
4.00
12
2 . 70 ± 0 . 05
9
(4X)
4
0.15
8
5
0.10 M C A B
16X 0 . 4 ± 0 . 05
4 0.30 ± 0 . 05
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 75 ± 0 . 05
C
0.08 C
SIDE VIEW
( 3 . 8 TYP )
( 12X 0 . 65 )
( 2 . 70 TYP )
C
0 . 2 REF
5
( 16X 0 .30 )
0 . 00 MIN.
0 . 05 MAX.
( 16 X 0 . 6 )
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
15
FN6837.2
EL5411T
Package Outline Drawing
M14.173A
14 LEAD HEAT-SINK THIN SHRINK SMALL OUTLINE PACKAGE (HTSSOP)
Rev 2, 10/09
A
1
3
3.20 ±0.10
5.00 ±0.10
14
SEE
DETAIL "X"
8
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3.00 ±0.10
3
1
7
0.20 C B A
B
0.65
EXPOSED THERMAL PAD
0.09-0.20
END VIEW
TOP VIEW
BOTTOM VIEW
1.00 REF
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
0.25 +0.05/-0.06
0.10 C
0.10
GAUGE
PLANE
0.25
5
0°- 8°
0.05 MIN
0.15 MAX
CBA
SIDE VIEW
0.60 ±0.15
DETAIL "X"
(3.20)
NOTES:
(1.45)
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
(5.65)
(3.00)
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.80mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead is 0.07mm.
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153, variation AB-1.
(0.35 TYP)
(0.65 TYP)
TYPICAL RECOMMENDED LAND PATTERN
16
FN6837.2