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EL5211T
Features
The EL5211T is a high voltage rail-to-rail input-output
amplifier with low power consumption. The EL5211T
contains two amplifiers. Each amplifier exhibits beyond
the rail input capability, rail-to-rail output capability and
is unity gain stable.
• 60MHz (-3dB) Bandwidth
The maximum operating voltage range is from 4.5V to
19V. It can be configured for single or dual supply
operation, and typically consumes only 3mA per
amplifier. The EL5211T has an output short circuit
capability of ±300mA and a continuous output current
capability of ±65mA.
The EL5211T features a high slew rate of 100V/µs, and
fast settling time. Also, the device provides common
mode input capability beyond the supply rails, rail-to-rail
output capability, and a bandwidth of 60MHz (-3dB). This
enables the amplifiers to offer maximum dynamic range
at any supply voltage. These features make the EL5211T
an ideal amplifier solution for use in TFT-LCD panels as a
VCOM driver or static gamma buffer, and in high speed
filtering and signal conditioning applications. Other
applications include battery power and portable devices,
especially where low power consumption is important.
The EL5211T is available in a thermally enhanced 8 Ld
HMSOP package, and a thermally enhanced 8 Ld DFN
package. Both feature a standard operational amplifier
pinout. The device operates over an ambient
temperature range of -40°C to +85°C.
• 4.5V to 19V Maximum Supply Voltage Range
• 100V/µs Slew Rate
• 3mA Supply Current (per Amplifier)
• ±65mA Continuous Output Current
• ±300mA Output Short Circuit Current
• Unity-gain Stable
• Beyond the Rails Input Capability
• Rail-to-rail Output Swing
• Built-in Thermal Protection
• -40°C to +85°C Ambient Temperature Range
• Pb-Free (RoHS Compliant)
Applications*(see page 13)
• TFT-LCD Panels
• VCOM Amplifiers
• Static Gamma Buffers
• Drivers for A/D Converters
• Data Acquisition
• Video Processing
• Audio Processing
• Active Filters
• Test Equipment
• Battery-powered Applications
• Portable Equipment
10
+15V
+15V
EL5211T
+
VS+
0.1µF
VINA-
VOUTB
VINA+
VINB-
0
4
4.7µF
PANEL
CAPACITANCE
VINB+
FIGURE 1. TYPICAL TFT-LCD VCOM APPLICATION
1
2
1kΩ
0
-2
-6
TFT-LCD
PANEL
May 12, 2010
FN6893.0
VS = ±5V
AV = 1
CL = 1.5pF
RL || 1kΩ (PROBE)
-4
0
VS-
6
GAIN (dB)
VOUTA
8
PANEL
CAPACITANCE
560Ω
150Ω
-8
-10
100k
1M
10M
FREQUENCY (Hz)
100M
FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS RL
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL5211T
60MHz Rail-to-Rail Input-Output Operational Amplifier
EL5211T
Pin Configuration
EL5211T
(8 LD DFN)
TOP VIEW
EL5211T
(8 LD HMSOP)
TOP VIEW
VOUTA 1
VINA- 2
8 VS+
+
VINA+ 3
+
VS- 4
VOUTA 1
7 VOUTB
VINA- 2
6 VINB-
VINA+ 3
8 VS+
PD
6 VINB-
VS- 4
5 VINB+
7 VOUTB
5 VINB+
THERMAL PAD IS ELECTRICALLY
CONNECTED TO VS-
THERMAL PAD IS ELECTRICALLY
CONNECTED TO VS-
Pin Descriptions
PIN NUMBER
(HMSOP, DFN)
PIN
NAME
1
VOUTA
FUNCTION
EQUIVALENT CIRCUIT
Amplifier A output
(Reference Circuit 1)
2
VINA-
Amplifier A inverting input
(Reference Circuit 2)
3
VINA+
Amplifier A non-inverting input
(Reference Circuit 2)
4
VS-
5
VINB+
Negative power supply
Amplifier B non-inverting input
(Reference Circuit 2)
6
VINB-
Amplifier B inverting input
(Reference Circuit 2)
7
VOUTB
Amplifier B output
(Reference Circuit 1)
8
VS+
Pad
PD
Positive power supply
Functions as a heat sink. Electrically connected to
VS-. Connect the thermal pad to VS- plane on the
PCB for optimum thermal performance.
VS+
VS+
VOUTx
VINx
VS-
GND
VS-
CIRCUIT 1
CIRCUIT 2
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
PACKAGE
(Pb-Free)
PKG.
DWG. #
EL5211TILZ-T13 (Note 1)
11T
8 Ld DFN
L8.2x3
EL5211TIYEZ
BBBNA
8 Ld HMSOP
MDP0050
EL5211TIYEZ-T7 (Note 1)
BBBNA
8 Ld HMSOP
MDP0050
EL5211TIYEZ-T13 (Note 1)
BBBNA
8 Ld HMSOP
MDP0050
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for EL5211T. For more information on MSL please see
techbrief TB363.
2
FN6893.0
May 12, 2010
EL5211T
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage between VS+ and VS- . . . . . . . . . . . .+19.8V
Input Voltage Range (VINx+, VINx-) . . . VS- - 0.5V, VS+ + 0.5V
Input Differential Voltage (VINx+ - VINx-) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . (VS+ + 0.5V)-(VS- - 0.5V)
Maximum Continuous Output Current . . . . . . . . . . . ±65mA
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . 3000V
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
8 Ld HMSOP (Notes 4, 5) . . . . . . .
62
13
8 Ld DFN (Notes 4, 5). . . . . . . . . .
58
8
Storage Temperature . . . . . . . . . . . . . . . . -65°C to +150°C
Ambient Operating Temperature . . . . . . . . . -40°C to +85°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C
Power Dissipation . . . . . . . . . . . . . . . See Figures 34 and 35
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = -5V, RL = 1k to 0V, TA = +25°C, Unless Otherwise Specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
5
18
mV
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
VCM = 0V
TCVOS
Average Offset Voltage Drift (Note 6)
8 Ld HMSOP package
13
µV/°C
8 Ld DFN package
9
µV/°C
VCM = 0V
2
IB
Input Bias Current
RIN
Input Impedance
1
G
CIN
Input Capacitance
2
pF
CMIR
Common-Mode Input Range
CMRR
Common-Mode Rejection Ratio
For VIN from -5.5V to 5.5V
50
73
dB
AVOL
Open-Loop Gain
-4.5V VOUTx 4.5V
62
78
dB
-5.5
60
+5.5
nA
V
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -5mA
VOH
Output Swing High
IL = +5mA
ISC
Short-Circuit Current
VCM = 0V, Source: VOUTx short to VS-,
Sink: VOUTx short to VS+
IOUT
Output Current
4.85
-4.95 -4.85
V
4.95
V
±300
mA
±65
mA
POWER SUPPLY PERFORMANCE
(VS+) - (VS-)
Supply Voltage Range
IS
Supply Current
VCM = 0V, No load
PSRR
Power Supply Rejection Ratio
Supply is moved from ±2.25V to ±9.5V
4.5
5.5
60
19
V
7.5
mA
75
dB
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 7)
-4.0V VOUTx 4.0V, 20% to 80%
100
V/µs
tS
Settling to +0.1% (Note 8)
AV = +1, VOUTx = 2V step,
RL = 1k1k (probe), CL = 1.5pF
85
ns
BW
-3dB Bandwidth
RL = 1kCL = 1.5pF
60
MHz
3
FN6893.0
May 12, 2010
EL5211T
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = -5V, RL = 1k to 0V, TA = +25°C, Unless Otherwise Specified. (Continued)
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
GBWP
Gain-Bandwidth Product
AV = -10, RF = 1kRG = 100
RL = 1k1k (probe), CL = 1.5pF
32
MHz
PM
Phase Margin
AV = -10, RF = 1kRG = 100
RL = 1k1k (probe), CL = 1.5pF
50
°
CS
Channel Separation
f = 5MHz
90
dB
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = 0V, RL = 1k to 2.5V, TA = +25°C, Unless Otherwise Specified.
DESCRIPTION
CONDITION
MIN
TYP
MAX UNIT
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
VCM = 2.5V
TCVOS
Average Offset Voltage Drift (Note 6)
8 Ld HMSOP package
5
18
mV
11
µV/°C
8 Ld DFN package
8
µV/°C
VCM = 2.5V
2
IB
Input Bias Current
RIN
Input Impedance
1
G
CIN
Input Capacitance
2
pF
CMIR
Common-Mode Input Range
CMRR
Common-Mode Rejection Ratio
For VIN from -0.5V to 5.5V
45
68
dB
AVOL
Open-Loop Gain
0.5V VOUTx 4.5V
62
82
dB
-0.5
60
+5.5
nA
V
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -4.2mA
VOH
Output Swing High
IL = +4.2mA
ISC
Short-circuit Current
VCM = 2.5V, Source: VOUTx short to VS-,
Sink: VOUTx short to VS+
IOUT
Output Current
60
4.85
150
mV
4.94
V
±110
mA
±65
mA
POWER SUPPLY PERFORMANCE
(VS+) - (VS-)
Supply Voltage Range
IS
Supply Current
VCM = 2.5V, No load
PSRR
Power Supply Rejection Ratio
Supply is moved from 4.5V to 19V
4.5
6.0
60
19
V
7.5
mA
75
dB
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 7)
1V VOUTx 4V, 20% to 80%
75
V/µs
tS
Settling to +0.1% (Note 8)
AV = +1, VOUTx = 2V step,
RL = 1k1k (probe), CL = 1.5pF
90
ns
BW
-3dB Bandwidth
RL = 1kCL = 1.5pF
60
MHz
GBWP
Gain-Bandwidth Product
AV = -10, RF = 1kRG = 100
RL = 1k1k (probe), CL = 1.5pF
32
MHz
PM
Phase Margin
AV = -10, RF = 1kRG = 100
RL = 1k1k (probe), CL = 1.5pF
50
°
CS
Channel Separation
f = 5MHz
90
dB
4
FN6893.0
May 12, 2010
EL5211T
Electrical Specifications
PARAMETER
VS+ = +18V, VS- = 0V, RL = 1k to 9V, TA = +25°C, Unless Otherwise Specified.
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
7
18
mV
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
VCM = 9V
TCVOS
Average Offset Voltage Drift (Note 6)
8 Ld HMSOP package
14
µV/°C
8 Ld DFN package
11
µV/°C
IB
Input Bias Current
RIN
Input Impedance
1
G
CIN
Input Capacitance
2
pF
CMIR
Common-Mode Input Range
CMRR
Common-Mode Rejection Ratio
For VIN from -0.5V to 18.5V
53
75
dB
AVOL
Open-Loop Gain
0.5V VOUTx 17.5V
62
104
dB
VCM = 9V
2
-0.5
60
+18.5
nA
V
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -6mA
VOH
Output Swing High
IL = +6mA
ISC
Short-circuit Current
VCM = 9V, Source: VOUTx short to VS-,
Sink: VOUTx short to VS+
IOUT
Output Current
80
150
17.85 17.92
mV
V
±300
mA
±65
mA
POWER SUPPLY PERFORMANCE
(VS+) - (VS-)
Supply Voltage Range
IS
Supply Current
VCM = 9V, No load
PSRR
Power Supply Rejection Ratio
Supply is moved from 4.5V to 19V
4.5
6.0
60
19
V
7.5
mA
75
dB
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 7)
1V VOUTx 17V, 20% to 80%
100
V/µs
tS
Settling to +0.1% (Note 8)
AV = +1, VOUTx = 2V step,
RL = 1k1k (probe), CL = 1.5pF
100
ns
BW
-3dB Bandwidth
RL = 1kCL = 1.5pF
60
MHz
GBWP
Gain-Bandwidth Product
AV = -10, RF = 1kRG = 100
RL = 1k1k (probe), CL = 1.5pF
32
MHz
PM
Phase Margin
AV = -10, RF = 1kRG = 100
RL = 1k1k (probe), CL = 1.5pF
50
°
CS
Channel Separation
f = 5MHz
90
dB
NOTES:
6. Measured over -40°C to +85°C ambient operating temperature range. See the typical TCVOS production distribution shown in
the “Typical Performance Curves” on page 6.
7. Typical slew rate is an average of the slew rates measured on the rising (20% to 80%) and the falling (80% to 20%) edges
of the output signal.
8. Settling time measured as the time from when the output level crosses the final value on rising/falling edge to when the output
level settles within a ±0.1% error band. The range of the error band is determined by: Final Value(V)±[Full Scale(V)*0.1%].
5
FN6893.0
May 12, 2010
EL5211T
Typical Performance Curves
10
TYPICAL
PRODUCTION
DISTRIBUTION
VS = ±5V
TA = +25°C
400
350
300
250
200
150
100
50
0
6
5
4
3
2
1
0
TYPICAL
PRODUCTION
DISTRIBUTION
8
6
4
2
0
2
6
10 14 18 22 26 30 34 38
INPUT OFFSET VOLTAGE DRIFT (|µV|/°C)
FIGURE 4. INPUT OFFSET VOLTAGE DRIFT (HMSOP)
VS = ±5V
5
0
-5
-10
-50
6
10 14 18 22 26 30 34 38
INPUT OFFSET VOLTAGE DRIFT (|µV|/°C)
FIGURE 5. INPUT OFFSET VOLTAGE DRIFT (DFN)
0
50
100
TEMPERATURE (°C)
150
FIGURE 6. INPUT OFFSET VOLTAGE vs TEMPERATURE
4
4.95
OUTPUT HIGH VOLTAGE (V)
VS = ±5V
3
2
1
0
-50
2
10
VS = ±5V
-40°C to +85°C
10
TYPICAL
PRODUCTION
DISTRIBUTION
7
INPUT OFFSET VOLTAGE (mV)
QUANTITY (AMPLIFIERS)
12
INPUT BIAS CURRENT (nA)
8
-12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12
INPUT OFFSET VOLTAGE (mV)
FIGURE 3. INPUT OFFSET VOLTAGE DISTRIBUTION
VS = ±5V
-40°C to +85°C
9
QUANTITY (AMPLIFIERS)
QUANTITY (AMPLIFIERS)
450
0
50
100
150
TEMPERATURE (°C)
FIGURE 7. INPUT BIAS CURRENT vs TEMPERATURE
6
VS = ±5V
IOUT = +5mA
4.94
4.93
4.92
-50
0
50
100
TEMPERATURE (°C)
150
FIGURE 8. OUTPUT HIGH VOLTAGE vs TEMPERATURE
FN6893.0
May 12, 2010
EL5211T
Typical Performance Curves (Continued)
VS = ±5V
IOUT = -5mA
OPEN LOOP GAIN (dB)
OUTPUT HIGH VOLTAGE (V)
-4.92
-4.93
-4.94
-4.95
-4.96
-4.97
-50
0
50
100
VS = ±5V
RL = 1kΩ
100
80
60
40
-50
150
0
TEMPERATURE (°C)
FIGURE 9. OUTPUT LOW VOLTAGE vs TEMPERATURE
SUPPLY CURRENT (mA)
SLEW RATE (V/µs)
150
2.95
VS = ±5V
RL = 1kΩ
140
120
100
80
60
-50
0
50
100
TEMPERATURE (°C)
4.0
SLEW RATE (V/µs)
3.0
2.5
8.5
FIGURE 13. SUPPLY CURRENT PER AMPLIFIER vs
SUPPLY VOLTAGE
7
2.85
2.80
2.75
0
50
100
TEMPERATURE (°C)
150
140
3.5
4.5
5.5
6.5
7.5
SUPPLY VOLTAGE (±V)
2.90
FIGURE 12. SUPPLY CURRENT PER AMPLIFIER vs
TEMPERATURE
TA = +25°C
NO LOAD
INPUT AT GND
3.5
VS = ±5V
NO LOAD
INPUT AT GND
2.70
-50
150
FIGURE 11. SLEW RATE vs TEMPERATURE
SUPPLY CURRENT (mA)
100
FIGURE 10. OPEN-LOOP GAIN vs TEMPERATURE
160
2.0
2.5
50
TEMPERATURE (°C)
9.5
120
100
80
TA = +25°C
AV = 1
RL = 1kΩ
CL = 8pF
60
40
2
4
6
8
SUPPLY VOLTAGE (±V)
10
FIGURE 14. SLEW RATE vs SUPPLY VOLTAGE
FN6893.0
May 12, 2010
EL5211T
Typical Performance Curves (Continued)
100
120
100
80
60
40
2
4
6
8
SUPPLY VOLTAGE (±V)
80
-20
10
VS = ±5V
RF = 1kΩ, RG = 100Ω
RL = 1kΩ || 1kΩ
(PROBE)
CL = 1.5pF
-20
10
100
1k
40
10k 100k 1M
FREQUENCY (Hz)
10M
-2
100pF
47pF
10pF
5
0
-5
VS = ±5V
AV = 1
RL = 1kΩ
-20
100k
1M
10M
FREQUENCY (Hz)
100M
FIGURE 19. FREQUENCY RESPONSE FOR VARIOUS CL
8
560Ω
-6
150Ω
-10
100k
1M
10M
FREQUENCY (Hz)
100M
FIGURE 18. FREQUENCY RESPONSE FOR VARIOUS RL
OUTPUT IMPEDANCE (Ω)
GAIN (dB)
0
-4
-40
100M
15
-15
-40
100M
1kΩ
2
1000
1000pF
10M
-8
20
-10
4
0
FIGURE 17. OPEN LOOP GAIN AND PHASE
10
10k 100k 1M
FREQUENCY (Hz)
VS = ±5V
AV = 1
CL = 1.5pF
RL || 1kΩ (PROBE)
6
GAIN (dB)
80
PHASE (°)
OPEN LOOP GAIN (dB)
120
40
1k
0
10
8
GAIN
100
40
FIGURE 16. OPEN LOOP GAIN AND PHASE
160
0
VS = ±5V
RF = 5kΩ, RG = 100Ω
RL = 1kΩ
CL = 8pF
0
200
20
80
20
PHASE
80
120
PHASE
40
FIGURE 15. OPEN LOOP GAIN vs SUPPLY VOLTAGE
60
160
GAIN
60
10
100
200
PHASE (°)
TA = +25°C
RL = 1kΩ
OPEN LOOP GAIN (dB)
OPEN LOOP GAIN (dB)
140
100
VS = ±5V
RF = 2kΩ
RL = 50Ω
SOURCE = 0dBm
10
1
0.1
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
FIGURE 20. CLOSED LOOP OUTPUT IMPEDANCE
FN6893.0
May 12, 2010
EL5211T
12
-30
10
-40
DISTORTION (dBc)
MAXIMUM OUTPUT SWING (VP-P)
Typical Performance Curves (Continued)
8
6
4
VS = ±5V
AV = 1
RL = 1kΩ
DISTORTION <1%
2
0
10k
100k
1M
10M
FREQUENCY (Hz)
-60
3rd HD
-70
VS = ±5V
AV = 2
RL = 1kΩ
fIN = 1MHz
-90
0
100M
2
0
VS = ±5V
TA = +25°C
VINx = -10dBm
-10
-20
VS = ±5V
-10 T = +25°C
A
-20
PSRR (dB)
-30
-40
-50
-60
-30
-40
-50
-60
-70
PSRR+
-70
-80
1k
10k
100k
1E+06
1E+07
-80
1k
1E+08
PSRR10k
100k
FREQUENCY (Hz)
1000
1E+06
1E+07
1E+08
FREQUENCY (Hz)
FIGURE 23. CMRR
FIGURE 24. PSRR
-20
TA = +25°C
-40
CROSSTALK (dB)
VOLTAGE NOISE (nV/√Hz)
10
4
6
8
OUTPUT VOLTAGE (VOP-P)
FIGURE 22. HARMONIC DISTORTION vs VOP-P
0
CMRR (dB)
-50
-80
FIGURE 21. MAXIMUM OUTPUT SWING vs FREQUENCY
-90
2nd HD
100
10
VS = ±5V
AV = 1
VINx = 0dBm
-60
-80
-100
1
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 25. INPUT VOLTAGE NOISE SPECTRAL
DENSITY
9
100M
-120
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 26. CHANNEL SEPARATION
FN6893.0
May 12, 2010
EL5211T
Typical Performance Curves (Continued)
80
5
VS = ±5V
TA = +25°C
AV = 1
RL = 1kΩ
VINx = ±50mV
VS = ±5V
TA = +25°C
AV = 1
RL= 1kΩ || 1kΩ
(PROBE)
CL =1.5pF
4
3
STEP SIZE (V)
OVERSHOOT (%)
100
60
40
20
2
1
0
-1
-2
-3
-4
0
10
100
LOAD CAPACITANCE (pF)
-5
70
1k
90
FIGURE 28. STEP SIZE vs SETTLING TIME
1V/DIV
50mV/DIV
FIGURE 27. SMALL-SIGNAL OVERSHOOT vs LOAD
CAPACITANCE
6V STEP
80
SETTLING TIME (ns)
VS = ±5V
TA = +25°C
AV = 1
RL= 1kΩ || 1kΩ
(PROBE)
CL = 1.5pF
VS = ±5V
TA = +25°C
AV = 1
RL= 1kΩ|| 1kΩ
(PROBE)
CL = 1.5pF
100mV STEP
50ns/DIV
50ns/DIV
FIGURE 29. LARGE SIGNAL TRANSIENT RESPONSE
FIGURE 30. SMALL SIGNAL TRANSIENT RESPONSE
EL5211T
(8LD MSOP/DFN shown)
1 VOUTA
VOUTA
CLA
RLA
Vs+ 8
VS+
+
0.1µF
4.7µF
RFA
2 VINA-
VOUTB
7
VOUTB
RGA
3
VINA+
VINA+
VINB-
6
RFB
RLB
CLB
RGB
49.9
4
VS4.7µF
+
Vs-
VINB+
5
0.1µF
VINB+
49.9
THERMAL PAD
CONNECTED TO VS-
FIGURE 31. BASIC TEST CIRCUIT
10
FN6893.0
May 12, 2010
EL5211T
Applications Information
VS = ±2.5V, TA = +25°C, AV = 1, VINx = 6VP-P, RL = 1kΩ to GND
The EL5211T can operate on a single supply or dual
supply configuration. The EL5211T operating voltage
ranges from a minimum of 4.5V to a maximum of 19V.
This range allows for a standard 5V (or ±2.5V) supply
voltage to dip to -10%, or a standard 18V (or ±9V) to
rise by +5.5% without affecting performance or
reliability.
The input common-mode voltage range of the EL5211T
extends 500mV beyond the supply rails. Also, the
EL5211T is immune to phase reversal. However, if the
common mode input voltage exceeds the supply voltage
by more than 0.5V, electrostatic protection diodes in the
input stage of the device begin to conduct. Even though
phase reversal will not occur, to maintain optimal
reliability it is suggested to avoid input overvoltage
conditions. Figure 32 shows the input voltage driven
500mV beyond the supply rails and the device output
swinging between the supply rails.
The EL5211T output typically swings to within 50mV of
positive and negative supply rails with load currents of
±5mA. Decreasing load currents will extend the output
voltage range even closer to the supply rails. Figure 33
shows the input and output waveforms for the device in a
unity-gain configuration. Operation is from ±5V supply
with a 1k load connected to GND. The input is a 10VP-P
sinusoid and the output voltage is approximately 9.9VP-P.
Refer to the “Electrical Specifications” Table beginning on
page 3 for specific device parameters. Parameter
variations with operating voltage, loading and/or
temperature are shown in the “Typical Performance
Curves” on page 6.
Output Current
The EL5211T is capable of output short circuit currents of
300mA (source and sink), and the device has built-in
protection circuitry which limits the output current to
±300mA (typical).
11
10µs/DIV
FIGURE 32. OPERATION WITH BEYOND-THE-RAILS
INPUT
VS = ±5V, TA = +25°C, AV = 1, VINx = 10VP-P, RL = 1kΩ to GND
INPUT
Operating Voltage, Input and Output
Capability
INPUT
OUTPUT
The EL5211T features a high slew rate of 100V/µs, and
fast settling time. Also, the device provides common
mode input capability beyond the supply rails, rail-to-rail
output capability, and a bandwidth of 60MHz (-3dB). This
enables the amplifiers to offer maximum dynamic range
at any supply voltage.
OUTPUT
5V/DIV
The EL5211T is a high voltage rail-to-rail input-output
amplifier with low power consumption. The EL5211T
contains four amplifiers. Each amplifier exhibits beyond
the rail input capability, rail-to-rail output capability and
is unity gain stable.
1V/DIV
Product Description
10µs/DIV
FIGURE 33. OPERATION WITH RAIL-TO-RAIL INPUT
AND OUTPUT
To maintain maximum reliability, the continuous output
current should never exceed ±65mA. This ±65mA limit is
determined by the characteristics of the internal metal
interconnects. Also, see “Power Dissipation” on page 12
for detailed information on ensuring proper device
operation and reliability for temperature and load
conditions.
Unused Amplifiers
It is recommended that any unused amplifiers be
configured as a unity gain follower. The inverting input
should be directly connected to the output and the
non-inverting input tied to the ground.
Thermal Shutdown
The EL5211T has a built-in thermal protection which
ensures safe operation and prevents internal damage to
the device due to overheating. When the die temperature
reaches +165°C (typical), the device automatically shuts
OFF the outputs by putting them in a high impedance
state. When the die cools by +15°C (typical), the device
automatically turns ON the outputs by putting them in a
low impedance (normal) operating state.
FN6893.0
May 12, 2010
EL5211T
Driving Capacitive Loads
• VS- = Negative supply voltage
As load capacitance increases, the -3dB bandwidth will
decrease and peaking can occur. Depending on the
application, it may be necessary to reduce peaking and
to improve device stability. To improve device stability a
snubber circuit or a series resistor may be added to the
output of the EL5211T.
• ISMAX = Maximum supply current per amplifier
Another method to reduce peaking is to add a series
output resistor (typically between 1 to 10). Depending
on the capacitive loading, a small value resistor may be
the most appropriate choice to minimize any reduction in
gain.
Power Dissipation
With the high-output drive capability of the EL5211T
amplifiers, it is possible to exceed the +150°C absolute
maximum junction temperature under certain load
current conditions. It is important to calculate the
maximum power dissipation of the EL5211T in the
application. Proper load conditions will ensure that the
EL5211T junction temperature stays within a safe
operating region.
The maximum power dissipation allowed in a package is
determined according to Equation 1:
T JMAX – T AMAX
P DMAX = -------------------------------------------- JA
• VOUT = Output voltage
• ILOAD = Load current
Device overheating can be avoided by calculating the
minimum resistive load condition, RLOAD, resulting in
the highest power dissipation. To find RLOAD set the two
PDMAX equations equal to each other and solve for
VOUT/ILOAD. Reference the package power dissipation
curves, Figures 34 and 35, for further information.
1.0
POWER DISSIPATION (W)
A snubber is a shunt load consisting of a resistor in series
with a capacitor. An optimized snubber can improve the
phase margin and the stability of the EL5211T. The
advantage of a snubber circuit is that it does not draw
any DC load current or reduce the gain.
(ISMAX = EL5211T quiescent current ÷ 2)
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
781mW
0.8
DFN8
JA = +160°C/W
694mW
0.6
HMSOP8
JA = +180°C/W
0.4
0.2
0.0
0
25
50
75 85
100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 34. PACKAGE POWER DISSIPATION vs
AMBIENT TEMPERATURE
(EQ. 1)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY (4-LAYER) TEST BOARD - EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
where:
• TJMAX = Maximum junction temperature
• TAMAX = Maximum ambient temperature
• JA = Thermal resistance of the package
• PDMAX = Maximum power dissipation allowed
The total power dissipation produced by an IC is the total
quiescent supply current times the total power supply
voltage, plus the power dissipation in the IC due to the
loads, or:
P DMAX = i  V S  I SMAX +  V S + – V OUT i   I LOAD i 
(EQ. 2)
POWER DISSIPATION (W)
2.8
2.4
P DMAX = i  V S  I SMAX +  V OUT i – V S -   I LOAD i 
(EQ. 3)
when sinking,
where:
• i = 1 to 2
(1, 2 corresponds to Channel A, B respectively)
• VS = Total supply voltage (VS+ - VS-)
• VS+ = Positive supply voltage
12
DFN8
JA = +58°C/W
2.02W
1.6
1.2
0.8
HMSOP8
JA = +62°C/W
0.4
0.0
0
when sourcing, and:
2.16W
2.0
25
50
75 85
100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 35. PACKAGE POWER DISSIPATION vs
AMBIENT TEMPERATURE
Power Supply Bypassing and Printed Circuit
Board Layout
The EL5211T can provide gain at high frequency, so good
printed circuit board layout is necessary for optimum
performance. Ground plane construction is highly
recommended, trace lengths should be as short as
FN6893.0
May 12, 2010
EL5211T
possible and the power supply pins must be well
bypassed to reduce any risk of oscillation.
For normal single supply operation (the VS- pin is
connected to ground) a 4.7µF capacitor should be placed
from VS+ to ground, then a parallel 0.1µF capacitor
should be connected as close to the amplifier as possible.
One 4.7µF capacitor may be used for multiple devices.
For dual supply operation, the same capacitor
combination should be placed at each supply pin to
ground.
It is highly recommended that EL5211T exposed thermal
pad packages should always have the pad connected to
the lowest potential, VS-, to optimize thermal and
operating performance. PCB vias should be placed below
the device’s exposed thermal pad to transfer heat to the
VS- plane and away from the device.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
5/12/10
FN6893.0
Initial Release.
2/24/10
FN6893.0
Pre-release data sheet submitted for formatting.
Products
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Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
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*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: EL5211T
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13
FN6893.0
May 12, 2010
EL5211T
Package Outline Drawing
L8.2x3
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 3/10
2.00
A
2X 1.50
PIN 1
INDEX AREA
6
PIN #1
INDEX AREA
6X 0.50
1
1.80 +0.10/-0.15
3.00
B
(4X)
0.15
8
8X 0.40 ±0.10
TOP VIEW
1.65 +0.10/-0.15
8X 0.25 +0.07/-0.05 4
0.10 M C A B
BOTTOM VIEW
SEE DETAIL "X"
0.90 ±0.10
0.10 C
(1.65)
(1.50)
(8X 0.60)
C
BASE PLANE
SEATING PLANE
0.08 C
0.05 MAX
SIDE VIEW
(2.80)(1.80)
0.20 REF
C
(6X 0.50)
0.05 MAX
(8X 0.25)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.25mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
7.
Compies to JEDEC MO-229 VCED-2.
either a mold or mark feature.
14
FN6893.0
May 12, 2010
EL5211T
HMSOP (Heat-Sink MSOP) Package Family
E
B
0.25 M C A B
E1
MDP0050
HMSOP (HEAT-SINK MSOP) PACKAGE FAMILY
MILLIMETERS
1
N
SYMBOL
D
(N/2)+1
(N/2)
PIN #1
I.D.
A
TOP VIEW
E2
EXPOSED
THERMAL PAD
D1
BOTTOM VIEW
HMSOP8 HMSOP10
TOLERANCE
NOTES
A
1.00
1.00
Max.
-
A1
0.075
0.075
+0.025/-0.050
-
A2
0.86
0.86
±0.09
-
b
0.30
0.20
+0.07/-0.08
-
c
0.15
0.15
±0.05
-
D
3.00
3.00
±0.10
1, 3
D1
1.85
1.85
Reference
-
E
4.90
4.90
±0.15
-
E1
3.00
3.00
±0.10
2, 3
E2
1.73
1.73
Reference
-
e
0.65
0.50
Basic
-
L
0.55
0.55
±0.15
-
L1
0.95
0.95
Basic
-
N
8
10
Reference
Rev. 1 2/07
e
NOTES:
H
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
C
SEATING
PLANE
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
0.08 M C A B
b
0.10 C
N LEADS
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
SIDE VIEW
L1
A
c
END VIEW
SEE DETAIL "X"
A2
GAUGE
0.25 PLANE
L
3° ±3°
A1
DETAIL X
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in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
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15
FN6893.0
May 12, 2010
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