DATASHEET

X9470
IGNS
E W DES
N
R
O
F
N DED
EM ENT
COMME
RE PL AC
D
E
N OT R E
D
N
E
enter at
MM
Data
Sheet
PRELIMINARY
port C
p
u
S
O R E CO
l
N
a
m/tsc
nic
our Tech r www.intersil.co
t
c
ta
n
o
c
o
TERSIL
1-888-IN
®
March 8, 2005
FN8204.0
RF Power Amplifier (PA) Bias Controller
DESCRIPTION
FEATURES
The Intersil X9470 RF PA Bias Controller contains all of
the necessary analog components to sense the PA
drain current through an external sense resistor and
automatically control the gate bias voltage of an
LDMOS PA. The external sense resistor voltage is amplified by an instrumentation amplifier and the output of
the amplifier along with an external reference voltage is
fed to the inputs of a comparator. The comparator output indicates which direction the LDMOS gate bias voltage will move in the next calibration cycle. System
calibration is accomplished by enabling the X9470 and
providing a clock to the SCL pin. The LDMOS drain current can be maintained constant over temperature and
aging changes by periodic calibration. The VOUT pin
can be used to monitor the average power by tracking
the drain current. Up to eight X9470 or additional Intersil Digital Potentiometers can be controlled via a twowire serial bus.
• Programmable Bias Controller IC for Class A
and AB LDMOS Power Amplifiers
• Adaptive System on Chip Solution
• Bias Current Calibration to better than ±4%
using Reference Trim DCP
• Automatic Bias Point Tracking and Calibration
— IDQ Sensing and Tracking
—Programmable Instrumentation Amplifier to
Scale Wide Range of IDQ
—Programmable Gate Bias Driver
—All Programmable settings are Nonvolatile
—All Settings Recalled at Power-up.
• 28V Maximum VDD
• 2 Wire Interface for Programming Bias Setting
and Optimizing IDQ Set Point
• Bias Level Comparator
• Shutdown Control pin for PA Signal
• Slave address to allow for multiple devices
• 24-pin TSSOP Package
• Applications: Cellular Base Stations (GSM,
UMTS, CDMA, EDGE), TDD applications, Pointto-multipoint, and other RF power transmission
systems
TYPICAL APPLICATION
RWREF RHREF RLREF
INC/DEC
A2
VOUT
VDD
V+
VSENSE+
RREF
VREF
A1
∆V
Comparator
A0
SDA
AGND
Vbias
control
RBIAS
VBIAS
+
VBIAS (Unbuffered)
Control &
Status Registers
EEPROM
VCC
choke
VREF
control
SCL
VSS
CS
1
RSENSE
Instrumentation
Amplifier
VP
I2C
interface
VSENSE–
CBULK
–
FILTER
RF
out
RF PA in
Matching
RF Impedance
RHBIAS RWBIAS RLBIAS
SHDN
Class A Example
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9470
PIN CONFIGURATION
TSSOP
Vsense+
1
RHREF
RLREF
2
3
RWREF
AGND
4
5
VSS
CS
SCL
6
7
8
SDA
9
10
RHBIAS
RWBIAS
RLBIAS
24
23
22
X9470
11
12
21
20
19
18
17
16
15
14
13
VsenseSHDN
INC/DEC
VOUT
V+
VCC
VCC
VBIAS
VSS
A2
A1
A0
ORDERING INFORMATION
Part Number
Temperature Range
Package
X9470V24I
-40°C TO 85°C
24-Lead TSSOP
PIN DESCRIPTIONS
TSSOP pin
Symbol
1
2
VSENSE+
RHREF
3
RLREF
4
RWREF
5
6
7
AGND
VSS
CS
8
SCL
9
10
SDA
RHBIAS
11
RWBIAS
12
RLBIAS
13
A0
14
A1
15
A2
16
17
18
19
20
21
22
VSS
VBIAS
VCC
VCC
V+
VOUT
INC/DEC
23
24
SHDN
VSENSE-
Brief Description
Positive sense voltage input terminal
Upper Terminal of Potentiometer, called the RREF potentiometer. The voltage applied to this pin will determine
the upper voltage limit of the adjustment for the Up/Down threshold of the comparator.
Lower Terminal of Potentiometer, called the RREF potentiometer. The voltage applied to this pin will determine
the lower voltage limit of the adjustment for the Up/Down threshold of the comparator.
Wiper Terminal of Potentiometer, called the RREF potentiometer. The voltage on this pin will be the threshold
for the Up/Down comparator. Also referred to as the VREF of the comparator.
Analog ground to allow single point grounding external to the package to minimize digital noise.
System (Digital) Ground Reference
Chip Select. This input enables bias calibration adjustments to the RBIAS potentiometer. CMOS input with internal pull-down.
Dual function. Function 1: The increment control input. Increments or decrements the RBIAS potentiometer.
Function 2: Serial Data Clock Input. Requires external pull-up.
Serial Data Input. Bi-directional 2-wire interface. Requires external pull-up.
Upper Terminal of Potentiometer, called the RBIAS potentiometer. The voltage applied to this pin will determine
the upper limit of the bias voltage to the PA (or VBIAS pin).
Wiper Terminal of Potentiometer, called the RBIAS potentiometer. This voltage is the equivalent to the unbuffered voltage that will appear at the VBIAS pin.
Lower Terminal of Potentiometer, called the RBIAS potentiometer. The voltage applied to this pin will determine
the lower limit of the bias voltage to the PA (or VBIAS pin).
External address pin which allows for a hardware slave address selection of this device.
This pin has an internal pull-down.
External address pin which allows for a hardware slave address selection of this device.
This pin has an internal pull-down.
External address pin which allows for a hardware slave address selection of this device.
This pin has an internal pull-down.
System (Digital) Ground Reference
This is the bias output voltage pin and is used to drive the filter network to the PA gate.
System (Digital) Supply Voltage
System (Digital) Supply Voltage
Positive voltage supply for the instrumentation amplifier and other analog circuits.
Instrumentation Amplifier output that is 20x or 50x the voltage across the Rsense pins.
Status output that indicates the state of the comparator. When this pin is HIGH, the RBIAS potentiometer
will increment; when the pin is LOW, the RBIAS potentiometer will decrement. This pin is open drain and
requires external resistor pull-up.
Shutdown the output op amp. When SHDN is active (HIGH), the VBIAS pin is pulled LOW.
Negative sense voltage Input terminal
2
FN8204.0
March 8, 2005
X9470
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Voltage on V+ (referenced to AGND) ...................... 7V
Voltage on VCC (reference to VSS) ........................ 7V
Voltage on all RH, RW, RL pins
(reference to AGND): ........................................... 7V
Voltage on Vsense+ or
Vsense- (reference to AGRND).......................... 30V
Voltage on SDA, CS, SCL, SHDN
(reference to AGND) ............... -0.3V to (Vcc + 0.3V)
Current into Output Pin:.......................................... ±5mA
Continuous Power Dissipation: ....................... 500mW
Operating Temperature range:.............. -40°C to +85°C
Junction Temperature: ..........................................150°C
Storage Temperature ........................ -65°C to +150°C
Lead Temperature (Soldering, 10 seconds): ..... 300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those listed in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.
ELECTRICAL CHARACTERISTICS
INSTRUMENTATION AMPLIFIER
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; TA = -40°C to +85°C, unless
otherwise noted.)
Limits
Symbol
VIN
(10)
Parameter
Common Mode Input Voltage on
VSENSE+ and VSENSE- pins
Min. Typ. Max. Units
20
28
Test Conditions/Notes
V
Gain 1
Gain from VSENSE to VOUT(2)
20
V/V
Measured with Status
Register bit SR0 = 0
Gain 2
Gain from VSENSE to VOUT(2)
50
V/V
Measured with Status
Register bit SR0 = 1
VRANGE1
Differential voltage sense range between
VSENSE+ and VSENSE- for gain 1
60
90
mV
Gain = 20
VRANGE2
Differential voltage sense range between
VSENSE+ and VSENSE- for gain 2
40
60
mV
Gain = 50
VOS
Input Offset Voltage
0.5
mV
VSENSE = 40mV to 90mV
TA = 25°C
Av1
Gain 1 Error
Gain = 20 (4)
1.5
%
VSENSE = 60mV to 90mV
TA = 25 to 85°C, Gain = 20
Av2
Gain 2 Error
Gain = 50 (4)
1.5
%
VSENSE = 40mV to 60mV
TA = 25 to 85°C, Gain = 50
Avt1
Total Error, Gain 1
Gain = 20 (5)
%
VSENSE = 60mV to 90mV
TA = 85°C, Gain = 20
%
VSENSE = 60mV to 90mV
TA = 25 to 85°C, Gain = 20
%
VSENSE = 40mV to 60mV
TA = 85°C, Gain = 50
10
%
VSENSE = 40mV to 60mV
TA = 25 to 85°C, Gain = 50
2
%
Avt1 or Avt2
0.2
V/µS
-6
1.5
6
10
Avt2
At
SR(10)
Total Error, Gain 2
Gain = 50 (5)
Long Term Drift
Slew Rate of Instrumentation Amp
3
-6
1.5
6
∆VSENSE = 20mV step,
Cout = 10pF Measured at
VOUT(1,3)
FN8204.0
March 8, 2005
X9470
ELECTRICAL CHARACTERISTICS
INSTRUMENTATION AMPLIFIER (CONTINUED)
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; TA = -40°C to +85°C, unless
otherwise noted.)
Limits
Symbol
Parameter
Tsettle(10)
CMRR
PSRR
Min. Typ. Max. Units
Setting time of Instrumentation Amp
5.0
µS
∆VSENSE = 20mV step, Cout =
10pF, settling to 1% of final value
Measured at VOUT(1,3)
Common Mode Rejection Ratio
40
dB
For both Gain 1 and Gain 2
Power Supply Rejection Ratio
VOUT Range
VOUT
Noise(10)
Test Conditions/Notes
55
VOUT Voltage Swing
dB
For both Gain 1 and Gain 2
0.3
1.8
V
Gain = 20
0.3
3.0
V
Gain = 50
3
mV
Gain = 20
VOUT Voltage Noise, rms
IVSENSE(10)
VSENSE+, VSENSE- Input Bias
Current
250
µA
TA = 25°C
CVSENSE(10)
VSENSE+, VSENSE- Input
Capacitance
10
pF
Each Input
COMPARATOR
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; TA = -40°C to +85°C, unless
otherwise noted.)
Limits
Symbol
Parameter
VOL
Output Voltage Low on the INC/DEC pin
Io(10)
Output sink Current
Min.
Typ.
Max. Units
Test Conditions/Notes
0.4
V
3
mA
INC/DEC pin, open drain
IOL = 1mA
Vos(10)
Input Hysteresis
20
mV
Vcc = 5 V
Tpd(10)
Response Time for propagation delay
2
µS
INC/DEC pin with 2kΩ pull up
VREF DCP CIRCUIT BLOCK
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; TA = -40°C to +85°C, unless
otherwise noted.)
Limits
Symbol
RTOTAL
Parameter
End to End Resistance
Min.
Typ.
Max.
Units
8
10
12
kΩ
Number Taps or Positions
Test Conditions/Notes
64
VRH
RHREF Terminal Voltage
AGND
V+
V
AGND = 0V
VRL
RLREF Terminal Voltage
AGND
V+
V
AGND = 0V
VRW
RWREF Terminal Voltage
AGND
V+
V
AGND = 0V
Power
Rating(10)
Resolution(10)
2.5
mW
1.6
%
Linearity(6)
-0.2
+0.2
MI(8)
Relative Linearity(7)
-0.2
+0.2
MI(8)
Absolute
4
RTOTAL =10kΩ
FN8204.0
March 8, 2005
X9470
VREF DCP CIRCUIT BLOCK
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; TA = -40°C to +85°C, unless
otherwise noted.)
Limits
Symbol
Parameter
RTOTAL Temperature
Ratiometric Temperature
CIN
(10)
Min.
Typ.
Coefficient(10)
Max.
±300
Coefficient(10)
Test Conditions/Notes
ppm/°C
-20
+20
Potentiometer Capacitances on RHREF
and RLREF
Units
10
ppm/°C
pF
BIAS ADJUSTMENT DCP CIRCUIT BLOCK
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; TA = -40°C to +85°C, unless
otherwise noted.)
Limits
Symbol
RTOTAL
Parameter
End to End Resistance Variation
Min.
Typ.
Max.
Units
8
10
12
kΩ
with ±20% variation
Number Taps or Positions
Test Conditions/Notes
256
VRH
Voltage at the RHBIAS Terminal Voltage
AGND
V+
V
AGND = 0V
VRL
Voltage at the RLBIAS Terminal Voltage
AGND
V+
V
AGND = 0V
VRW
Voltage at the RWBIAS Terminal Voltage
AGND
V+
V
AGND = 0V
Power
Rating(10)
Resolution(10)
Absolute Linearity(6)
Relative Linearity(7)
RTOTAL Temperature
CIN
mW
0.4
%
-1.0
+1.0
MI(8)
-1.0
+1.0
MI(8)
Coefficient(10)
Ratiometric Temperature
(10)
2.5
±300
Coefficient(10)
ppm/°C
-50
50
Potentiometer Capacitances on RHBIAS
and RLBIAS
RTOTAL =10 KΩ
10
ppm/°C
pF
VBIAS OUTPUT VOLTAGE FOLLOWER
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; TA = -40°C to +85°C, unless
otherwise noted.)
Limits
Symbol
VOS
Parameter
Min.
Typ.
Max.
Units
Test Conditions/Notes
Input Offset Voltage
10
mV
VOSDRIFT(10)
Offset Voltage Temperature
Coefficient
10
µV/°C
TA = -40 to +85°C
SR
Output Slew Rate on VBIAS
0.5
V/µS
RL = 10kΩ, 1nF, ∆VBIAS =
20mV
VBIAS
Voltage Output Swing
TS(10)
Settling Time
tSHDN
Time for SHDN pin (delay) valid
PSRR
Power Supply Rejection Ratio
5
1.5
VCC - 0.5
2
0.1
45
55
1.0
V
IOUT = ±10mA
µs
Final value ±1%, RL = 10kΩ,
1nF, ∆VBIAS = 20mV
µs
dB
VCC supply VCC = 4.75 to
5.25V
FN8204.0
March 8, 2005
X9470
VBIAS OUTPUT VOLTAGE FOLLOWER
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; TA = -40°C to +85°C, unless
otherwise noted.)
Limits
Symbol
Parameter
Input Voltage Range
CL(10)
CIN(10)
ROUT(10)
Min.
Typ.
1.5
Max.
Units
VCC - 0.5
V
Load Capacitance
1
nF
Capacitances on Shutdown Pin
10
pF
Output Impedance
3
Ω
Test Conditions/Notes
at 5MHz, 1nF load
D.C. OPERATING CHARACTERISTICS
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; TA = -40°C to +85°C, unless
otherwise noted.)
Limits
Symbol
ICC1(9)
ICC2(9)(10)
ISB(9)
Parameter
Min.
Typ.
Max.
Units
V+ Active Current
1
3
mA
VCC Active Current
5
25
mA
Standby Supply Current
(VCC, V+)
1.5
CS = VCC - 0.3V, and SCL
@ max. tCYC, SDA = VCC 0.3V, SHDN inactive
mA
CS = VIL, and SCL inactive
(no clock), SDA =VIL, SHDN
active
VIN = VSS to VCC
ILI
CS, SDA, SCL, SHDN RH, RL, RW,
INC/DEC VOUT, Input Leakage
-10
10
µA
VIH(10)
CS, SDA, SCL, SHDN, A0, A1, A2
HIGH Voltage
VCC x 0.7
VCC + 0.5
V
VIL(10)
CS, SDA, SCL, SHDN, A0, A1, A2
LOW Voltage
-0.5
VCC x 0.3
V
CIN(10)
CS, SDA, SCL, SHDN, A0, A1, A2
Capacitance
10
Test Conditions
pF
VCC = 5V, VIN = VSS,
TA = 25°C, f = 1MHz
Notes: (1) VOUT is a high impedance output intended for light loads only.
(2) Gain at VOUT is set to 20 by default.
(3) Value given is for VOUT. The VBIAS output will depend on the VBIAS potentiometer which is initially loaded with a zero value, then followed by the loading of the final value from E2 memory.
(4) Gain Error excludes the contribution of the input offset voltage error.
(5) Total Error includes the contributions of gain error and input offset voltage error.
(6) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage = (Vw(n)(actual) - Vw(n)(expected))
(7) Relative Linearity is a measure of the error in step size between taps = VW(n+1) - [Vw(n) + Ml]
(8) 1 Ml = Minimum Increment = RTOT/63 or RTOT/255.
(9) Typical values are for TA = 25°C and nominal supply voltage, VCC = 5V.
(10) This parameter is not 100% tested.
6
FN8204.0
March 8, 2005
X9470
BIAS ADJUSTMENT CIRCUIT BLOCK
A.C. OPERATING CHARACTERISTICS
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; TA = -40°C to +85°C, unless
otherwise noted.)
Limits
Symbol
Parameter
Min.
Typ.(9)
Max.
Units
tCl
CS to SCL Setup
tlD
Vsense Change to INC/DEC Change
tlL
SCL LOW Period
1.5
µs
tlH
SCL HIGH Period
1.5
µs
SCL Inactive to CS Inactive
100
tlC
(10)
tIW(10)(11)
µs
ns
µs
3
SCL Cycle Time
(10)
ns
5
SCL to VBIAS Change
tCYC
t R, t F
100
µs
3
SCL Input Rise and Fall Time
500
ns
A.C. TIMING
CS
tCYC
tCI
tIL
tIH
tIC
90%
90%
10%
SCL
tID
tF
tR
INC/DEC
tIW
VBIAS
(Vsense+ –
Vsense-)
Note:
(11) MI in the A.C. timing diagram refers to the minimum incremental change in the VBIAS output due to a change in the wiper position.
7
FN8204.0
March 8, 2005
X9470
AC SPECIFICATIONS
Symbol
Parameter
fSCL
Max.
Unit
400
kHz
SCL Clock Frequency
0
(10)
Pulse width Suppression Time at inputs
50
(10)
SCL LOW to SDA Data Out Valid
0.1
Time the bus must be free before a new transmission can start
1.3
µs
tLOW
Clock LOW Time
1.3
µs
tHIGH
Clock HIGH Time
0.6
µs
tSU:STA
Start Condition Setup Time
0.6
µs
tHD:STA
Start Condition Hold Time
0.6
µs
tSU:DAT
Data In Setup Time
200
ns
tHD:DAT
Data In Hold Time
200
ns
tSU:STO
Stop Condition Setup Time
0.6
µs
Data Output Hold Time
50
ns
tIN
tAA
tBUF
tDH
tR
Note:
Min.
(10)
(10)
(10)
ns
0.9
µs
+.1Cb(12)
300
ns
300
ns
400
pF
SDA and SCL Rise Time
20
tF(10)
SDA and SCL Fall Time
20 +.1Cb(12)
Cb(10)
Capacitive load for each bus line
(12) Cb = total capacitance of one bus line in pF.
TIMING DIAGRAMS
Bus Timing
tHIGH
tF
SCL
tLOW
tR
tSU:DAT
tSU:ST
SDA IN
tHD:DAT
tHD:STA
tSU:STO
tAA
tDH
tBUF
SDA OUT
Write Cycle Timing
SCL
SDA
8th Bit of Last Byte
ACK
tWC
Stop
Condition
8
Start
Condition
FN8204.0
March 8, 2005
X9470
Power-up Timing
Symbol
tr VCC
Note:
(10)
Parameter
VCC Power-up rate
Min.
Max.
Unit
0.2
50
V/ms
Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are not 100% tested.
Proper recall of stored wiper setting requires a VCC power-up ramp that is monotonic and with noise or glitches < 100mV. It is important to
correctly sequence voltages in an LDMOS amplifier circuit. For the X9470 typical application, the VCC, then V+ pins should be powered
before the VDD of the LDMOS to prevent LDMOS damage. Under no circumstances should the VDD be applied to the LDMOS device
before VCC and V+ are applied to the X9470.
DCP Default Power-up Tap Positions (shipped from factory)
VREF DCP
0
Bias Adjust DCP
0
Nonvolatile Write Cycle Timing
Symbol
tWC
Note:
Parameter
(10)
Write Cycle Time
Min.
Typ.(1)
Max.
Unit
5
10
ms
tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
9
FN8204.0
March 8, 2005
X9470
DETAILED PIN DESCRIPTIONS
Supply Pins
Digital Supplies VCC, VSS
The positive power supply and ground for the DCP
digital control sections. VSS is normally tied to digital
ground. The X9470 is provided with separate digital
and analog power supply pins to better isolate digital
noise from the analog section.
Analog Supplies V+, AGND
The positive analog supply and ground for the Instrumentation Amplifier (IA). The analog supply ground is
kept separate to allow an external single point connection. V+ can be a separate supply voltage from VCC, or
VCC can be filtered before connection to V+.
Bias Adjustment Circuit Block Pins
RHBIAS , RLBIAS , and RWBIAS for VBIAS Adjustments.
These pins are the connections to a Intersil Digitally
Controlled Potentiometer (XDCP™) or RBIAS potentiometer. RHBIAS is connected to the most positive reference, and the RLBIAS is connected to the least
positive reference voltage. The potentiometer has a
resolution of 256-taps and typical RTOTAL of 10kΩ. So
for example, to provide 4mV resolution, the voltage difference applied to the RHBIAS and RLBIAS pins must
be 1.024V. The RWBIAS value can be stored in nonvolatile memory and recalled upon power-up.
Serial Clock (SCL).
This is a dual function input pin. The state of the CS
pin determines the functionality.
Function 1: SCL is a negative edge-triggered control
pin of the RBIAS potentiometer. Toggling SCL will
either increment or decrement the wiper in the
direction indicated by the logic level on the INC/DEC
pin. CS must be high for this function.
Function 2: SCL is the serial bus clock for serial bus
interface. CS must be low for this function.
Chip Select (CS). Calibration Enable.
The CS input is the enable bias adjustments. When
the CS is HIGH (enabled) and a SCL pulse is present,
the wiper position on the RBIAS potentiometer will
automatically update with either an increment or decrement of one tap position according to INC/DEC signal from the comparator.
10
When CS is LOW (disabled), the wiper counter of the
XDCP will hold the last wiper position until CS is
enabled again and the wiper position is updated.
INC/DEC Monitor Pin
The Up or Down Monitor pin (INC/DEC) indicates the
state of the comparator. This signal indicates that the
Instrumentation Amplifier output voltage is higher or
lower than the voltage level set by the RWREF pin. The
output is used to indicate the direction that the gate
bias voltage needs to move to reach the target bias
voltage.
Sense and Scale Block Pins
VSENSE+ and VSENSEThese are the input pins to the IA circuit. These pins
are used to determine the change in voltage across
the the external drain sense resistor of an RF power
amplifier.
RHREF , RLREF, and RWREF. PA Bias Set Point.
The PA Bias reference voltage is controlled by a 64tap (10kΩ typical RTOTAL) potentiometer, called the
RREF potentiometer. The voltages applied to RHREF
and RLREF will determine the range of adjustment of
the reference voltage level (VREF) for the Comparator. The resolution of the comparator reference is the
difference of the voltages applied to RHREF and RLREF
divided by 63. The position of the wiper (RWREF) is
controlled via serial bus. The RWREF value can be
stored in non-volatile memory and recalled upon
power-up.
RWREF is also an input signal used as a scaling voltage (VREF) to set the appropriate IDQ of an RF power
amplifier. VREF can be derived from an external voltage divider or from a baseband processor or similar
microcontroller. VREF can be set permanently or
changed dynamically using the potentiometer for various PA operating points.
VOUT
This pin is the output of the IA, which reflects a 20x or
50x gain of the input signal (voltage across the Vsense
pins). It can be used to indicate the magnitude of the
drain current envelope when RF is present.
FN8204.0
March 8, 2005
X9470
TYPICAL APPLICATION
Output Block Pins
VBIAS
The VBIAS is the gate bias voltage output. It is buffered
with a unity gain amplifier and is capable of driving 1nF
(typical) capacitive loads.
This pin is intended to be connected through an RF filter to the gate of an LDMOS power transistor. The
voltage of VBIAS is determined by the XDCP’s value of
the RBIAS resistor.
Other Pins
SHDN
SHDN is an input pin that is used to shutdown the
VBIAS output voltage follower. When the SHDN pin is
HIGH, the VBIAS pin is pulled to VSS. When the device
is shutdown, the current RBIAS wiper position will be
maintained in the wiper counter register. When shutdown is disabled, the wiper returns to the same wiper
position before shutdown was invoked. Note that when
the device is taken out of shutdown mode (SHDN
goes from HIGH to LOW), the CS input must be cycled
once to enable calibration.
SDA
Serial bus data input/output. Bi-directional. External
pullup is required.
A0, A1, A2
Serial bus slave address pins. These pins are used to
defined a hardware slave address. This will allow up to
8 of the X9470’s to be shared on one two-wire bus.
These are useful if several X9470’s are used to control
the bias voltages of several LDMOS Power Transistors in a single application. Default hardware slave
address is “000” if left unconnected due to internal
pull-down resistor.
The X9470 can be used along with a microprocessor
and transmit control chips to control and coordinate
FET biasing (see Figure 1). The CS, SCL, and SDA signals are required to control the X9470 Bias Adjustment
Circuit Block. An internal RWREF voltage is provided via
a programmable voltage divider between the RHREF
and RLREF pins and is used to set the voltage reference
of the comparator. The shutdown (SHDN) and bias voltage indicators (INC/DEC) are additional functions that
offer FET control, monitoring, and protection.
Typically, the closed loop setup of the X9470 allows for
final calibration of a power amplifier at production test.
The CS and SCL pins are used to perform this calibration function. Once in a base station, the amplifier can
then be re-calibrated any time that there is no RF signal
present. The bias setting block can also be used open
loop to adjust gate bias or can be shutdown using the
SHDN pin. The sense and scale block can be used for
amplifier power monitoring diagnostics as well.
The range of the drain bias current operating point of
the LDMOS FET is set by an external reference
across the reference potentiometer. The wiper of the
potentiometer sets the trip point for comparison with
VP , the amplified voltage across RSENSE, the drain
resistor. The output of the comparator causes the
RBIAS potentiometer to increment or decrement automatically on the next SCL clock cycle. This RBIAS
potentiometer is configured as a voltage divider with a
buffered wiper output which drives the gate voltage of
an external LDMOS FET.
Once the optimum bias point is reached, the RBIAS
value is latched into a wiper counter register. Again,
the VBIAS gate voltage can be updated continuously or
periodically depending on the system requirements.
Both terminals of the RBIAS potentiometer are accessible and can be driven by external reference voltages to
achieve a desired IDQ vs. gate voltage resolution, as
well as supporting temperature compensation circuitry.
In summary, the X9470 provides full flexibility on setting the operating bias point and range of an external
RF power amplifier for GSM, EDGE, UMTS, CDMA or
other similar applications.
11
FN8204.0
March 8, 2005
X9470
Figure 1. Typical Application
RWREF RHREF RLREF
INC/DEC
A2
VOUT
VDD
V+
VSENSE+
RREF
VREF
A1
∆V
Comparator
A0
SDA
AGND
choke
VREF
control
SCL
RBIAS
Vbias
control
VBIAS
VBIAS (Unbuffered)
Control &
Status Registers
EEPROM
VCC
CS
VSS
RSENSE
Instrumentation
Amplifier
VP
I2C
interface
VSENSE–
CBULK
RHBIAS RWBIAS RLBIAS
X9470 FUNCTIONAL DESCRIPTION
This section provides detail description of the following:
– Sense and Scale Block Description
– Bias Adjustment Control Block Description
+
–
FILTER
RF PA in
Matching
RF Impedance
Class A Example
SHDN
The output of the IA is also available at the pin Vout to
enable drain current monitoring. The gain at Vout is
fixed at a factor of K2, lower than K1 so that high IDQ
currents will not cause saturation of the Vout signal.
The equation for Vout is given as:
– Output Block Description
∆V = IDQ * RSENSE
– Bias Adjustment and Storage Description
VOUT = K2 * ∆V
SENSE AND SCALE BLOCK
The Sense and Scale Circuit Block (Figure 2) implements an instrumentation amplifier whose inputs
(VSENSE+ and VSENSE-) are across an external sense
resistor in the drain circuit of an RF Power FET. VSENSE+
is connected to VDD, the drain voltage source for the RF
power FET, and VSENSE- pin is connected to the other
end the external sense resistor.
An internal instrumentation amplifier (IA) will sense the
∆V and amplify it by a gain factor of K1 (see Equation
1). The resulting output is compared with VREF at the
comparator. VREF can be a fixed reference voltage or
adjusted by using the 64-tap digital potentiometer. The
output of the comparator is used to increment or decrement the RBIAS potentiometer in the Bias Adjustment Circuit Block. The gain factor K1 is designed
such that the Sense and Scale Block will set the Bias
Adjustment Circuit Block to operate in a given voltage
range (mV) vs. drain current adjustment (mA).
VREF
(1)
IDQ ≅
K1 * RSENSE
RF
out
K2 is fixed to 20x for the Vout pin
BIAS ADJUSTMENT CIRCUIT BLOCK
There are three sections of this block (Figure 3): the
input control, counter and decode section (1), the
resistor array (2); and the non-volatile register (3). The
input control section operates just like an up/down
counter. The input of the counter is driven from the
output of the comparator in the Sense and Scale Block
and is clocked by the SCL signal. The output of this
counter is decoded to select one of the taps of a 256tap digital potentiometer.
K1 is fixed 50x for the internal comparator input.
12
FN8204.0
March 8, 2005
X9470
Figure 2. Sense and Scale Block Diagram
VDD
INC/DEC
RWREF RHREF
RLREF
VOUT
VSENSE+ RSENSE
VSENSE–
IDQ
}
Cint~2pF ±10%
∆V
VREF
Comparator
INC/DEC
10kΩ
64-tap
K2 = 20X
~1kΩ
K1 = 50X
choke
Precision
I-Amp
RF
PA
Out
Vgate
RF PA in
The wiper of the digital potentiometer acts like its
mechanical equivalent and does not move beyond the
last position. That is, the counter does not wrap
around when clocked to either extreme. The electronic
switches in the potentiometer operate in a “make
before break” mode when the wiper changes tap positions. If the wiper is moved several positions, multiple
taps are connected to the wiper for tIW (SCL to
RWBIAS change).
Storing Bias Resistor Values in Memory. Wiper values are stored to VOLATILE memory automatically
when CS is HIGH and INC/DEC either transitions from
HIGH to LOW or from LOW to HIGH. Wiper values are
stored to NON-VOLATILE memory during Byte Write
or as described in the following section.
Table 1. Mode Selection
SDA
CS*
H
H
H
VBIAS is incremented
one tap position.
H
H
L
VBIAS is decremented
one tap position.
Important note: the factory setting of the wiper counter
register is the ZERO-position (0 of 255 taps). This is
the default wiper position.
H
H
X
Bias Adjustment Block Instructions and Programming. The SCL, INC/DEC (internal signal) and CS
inputs control the movement of the wiper along the
resistor array. (See Table 1) With CS set HIGH, the
device is selected and enabled to respond to the
INC/DEC and SCL inputs. HIGH to LOW transitions on
SCL will increment or decrement RBIAS (depending on
the state of the INC/DEC input). The INC/DEC input is
derived from the output of the comparator of the
Sense and Scale Block.
X
L
X
13
SCL
INC /
DEC
When the device is powered-up, the X9470 will load
the last saved value from the non-volatile memory into
the WCR. Note that the current wiper position can be
saved into non-volatile memory register by using the
SCL and CS pins as shown in Figure 4.
Mode
or
Lock Wiper Position.
Save to volatile
memory. (BiasLock™)
X
Open Loop.
* When coming out of shutdown, the CS pin must be cycled once before bias
adjustment is enabled.
FN8204.0
March 8, 2005
X9470
Figure 3. Bias Adjustment Block Diagram
Gate Bias
Op Amp
–
VBIAS (unbuffered)
RWBIAS
2
RHBIAS
RBIAS
RLBIAS
XDCP
Memory and Control
WCR (Rbias)
External pin/signal
Internal node/signal
3
to LDMOS gate
+
10kΩ
256-tap
Legend
VBIAS
Bias Register
non-volatile
SHDN
INC/DEC is logic HIGH or LOW
from Sense/Scale Block
and is used to increment or
decrement the Rbias resistor
(XDCP) to adjust the gate voltage.
Power-On Recall
(POR)
SCL
INC
U/D
CS
1
INC/DEC
Note:
1) WCR = Wiper Control Register
CS
NON-VOLATILE STORE OF THE BIAS POSITION
The following procedure will store the values for the
Rref and Rbias wiper positions in Non-Volatile memory. This sequence is intended to be performed after a
BiasLock calibration sequence to simplify storage. If
BiasLock has not been achieved, then the Rbias wiper
position may change when the CS pin is brought high
and SCL begins clocking. See Figure 4 for the actual
sequence.
1. Set the WEL bit with a write command (02h to register 0Fh)
2. Peform a calibration and achieve BiasLock. Leave
CS pin high.
3. Write the address byte only (START, followed by
device/slave address and a 0 for a write, see page
19).
4. Perform a STOP command.
5. With SCL still low, bring the CS low. The falling
edge of the CS will initiate the NV write.
The WEL bit may be reset afterwards to prevent further NV writes.
INC/DEC FUNCTION
The INC/DEC pin is an open-drain logic output that
tracks the activity of the increment/decrement comparator. A logic HIGH at INC/DEC indicates that the IDQ
did not rise up to the desired setting indicated by VREF
while a logic LOW at the INC/DEC pin indicates that
the IDQ is higher than the desired setting.
14
INC/DEC is used as an internal control signal as well.
As an example, when INC/DEC is LOW, the Bias
Adjustment Circuit Block will start to move the Rbias
resistor wiper towards the RLBIAS terminal end when
CS is HIGH and SCL is clocking. Consequently, the
VBIAS voltage will decrease, and the IDQ decreases to
meet the desired VREF setting.
The INC/DEC signal can also be used to detect a
damaged RF power FET. For instance, If INC/DEC
stays HIGH during and after a calibration sequence it
may indicate that the RF power FET has failed. This
indicator can also be used with a level sense on the
VOUT pin to perform diagnostics.
SHUTDOWN MECHANISM
This hardware control shutdown pin (SHDN) will pull
the voltage of VBIAS to VSS with an internal pull down
resistor. When shutdown is disabled (VBIAS is active
when SHDN is LOW), the VBIAS voltage will move to
the previous desired bias voltage.
It will take less than a microsecond to enable the internal output buffer depending on the loading condition at
the VBIAS pin.
OUTPUT (VBIAS)
VBIAS is a buffered output of RWBIAS (wiper output). It
can deliver a high current for driving up to typically 1nF
capacitive loading with stable performance and fast
settling time.
FN8204.0
March 8, 2005
X9470
A single pole filter should be placed in between the
VBIAS output and the RF input signal to isolate any
high frequency noise.
Figure 4. Non-Volatile Store of the Bias Position
Set WEL
bit
CS
Calibration
Set
and Bias Lock Address Byte
1
2
3
Stop
4
Initiates
high voltage write
cycle
5
SCL
SDA
tWR
RBIAS non-volatile register
Non-volatile Write of RBIAS and RREF value Using SDA, SCL and CS pins
X9470 PRINCIPLES OF OPERATION
The X9470 is a Bias Controller that contains all the
necessary analog components for closed-loop DC
bias control of LDMOS Transistors in RF Applications.
The X9470 provides a mechanism to periodically set
DC bias operating points of Class A or AB-type amplifiers to account for VGS drift and temperature variations. The following is an example of X9470 operation.
The X9470 incorporates an instrumentation amplifier,
comparator and buffer amplifier along with resistor
arrays and their associated registers and counters. The
serial interface provides direct communication between
the host and the X9470. This section provides a
detailed example of how the X9470 can be used to calibrate and dynamically set the optimum bias operating
point of an RF power amplifier (see Figure 5):
– State 0: Power-on Monitor Mode
– State 1: DC-bias Setting When No RF is Present
[Calibration]
– State 2: Calibration Disable When RF is Present
– State 3: PA Standby Mode. Dynamic Adjustment for
VGS drift and Temperature variation
Stored in
Non-volatile
memory
State 0: Monitor Mode
The VOUT and INC/DEC outputs of the X9470 can be
used for monitoring and diagnostic purposes. Since
VOUT has a lower gain (20x, default) than the internal
IA output, it can handle higher drain sense current
while keeping the output below the rail. This allows normal PA power monitoring, and over-current sensing using an external comparator. The INC/DEC pin can be
monitored during calibration to see if there is no
change, which indicates LDMOS functional problems.
Note that the INC/DEC status is also available in the
status register for software status reads.
State 1: DC-bias Setting When No RF is Present
[Calibration]
At calibration, the DC bias operating point of the
LDMOS Power Amplifier must be set. As soon as the
Bias Adjustment Circuit Block is enabled (CS enabled,
SDA high, and SCL pulse provided), the X9470 will
automatically calibrate the external Power Amplifier by
continually sampling the drain current of the external
Power Amplifier and make adjustments to the gate
voltage of the amplifier (See Figure 6).
– State 4: Power Off (Shutdown) Mode [Turn off the
Power Amplifier]
15
FN8204.0
March 8, 2005
X9470
Figure 5. Operating modes X9470
State 0
PA
Monitor Mode
PA Enabled, Vout and INC/DEC Monitored for status
State 1
PA
Calibration Mode
Choose Vref to scale IDQ, perform calibration,
Latch bias point for DC bias current in wiper counter
State 2
PA
Transmit Mode
Disable Bias Adjustment,
State 3
PA
Standby Mode
Recalibrate bias point for drift and temperature.
Rbias resistor will automatically increment or decrement
for optimal operating point continuously
State 4
PA
Off Mode
When no RF signal is present, the instrumentation
amplifier of the X9470 senses the drain current as a
voltage drop, ∆V, across an external drain Rsense
resistor. The ∆V is amplified and compared to an
external scaling voltage, VREF . Any difference
between ∆V and VREF results in a resistive increment
or decrement of the internal RBIAS potentiometer.
The RBIAS potentiometer is used as a voltage divider
with the RHBIAS and RLBIAS terminals setting the
upper and lower voltage limits of the unbuffered
RWBIAS voltage. The resolution of the RBIAS potentiometer resistor is 0.4% of the difference of voltage
across the RHBIAS and RLBIAS terminals. The RTOTAL
is typically 10kΩ with 256-taps. So, for example, if the
difference between the RHBIAS and RLBIAS terminals
is 1.024V, then the step accuracy is 4mV.
The voltage at the RWBIAS pin is then fed into the VBIAS
voltage follower. The VBIAS pin is a buffered output that is
used to drive the gate of an LDMOS transistor.
The scaling voltage, VREF, set by the RREF potentiometer, sets the calibrated operating point of the LDMOS
Amplifier.
16
Turn off PA
On edge transitions of the INC/DEC signal, the X9470
will latch the current wiper position - this is known as
“Bias Lock™” mode. This is shown in Figure 6. When
BiasLock occurs, the comparator hysteresis will allow
INC/DEC to change state only after the IA output
changes by more than 20mV. This will prevent toggling
of the VBIAS output unless the drain bias current is constantly changing.
State 2: DC-bias Disable When RF is Present
(optional)
When an RF signal is present, the X9470 is put into
standby mode (open loop). The X9470 is in standby
mode when the CS pin is disabled so that the RBIAS
potentiometer holds the last wiper position. The presence of an RF signal at the input of a Class A or AB
amplifier increases the current across the Rsense resistor. Over a period of time, the temperature of the
LDMOS also increases and the LDMOS also experiences VGS drift. Therefore the DC biasing point that
was set during State 1 (calibration) is not optimal.
Adjustments to the gate voltage will need to be made
to optimize the operation of the LDMOS PA. This is
done in State 3.
FN8204.0
March 8, 2005
X9470
State 3: PA Standby Mode, DC Bias Adjustment
[Compensation for VGS Drift and Temperature
Variation]
When the Power Amplifier is in Standby Mode the
X9470 allows for dynamic adjustment of the DC biasing point to take into account both VGS drift and temperature variation. Dynamic biasing is achieved with
the X9470 by using the CS, and SCL pins. For example, the SCL pin can be a steady clock and the CS pin
can be used as a control signal to enable/disable the
Bias Adjustment Block.
Figure 6 illustrates how the X9470 can be used for
dynamic biasing. Upon the presence of an RF signal,
the CS pin is pulled LOW. This will prevent the X9470
from changing the VBIAS voltage during IDQ peak currents. Once the RF signal is no longer present, the CS
pin can be enabled (closed loop), SDA high and the
X9470 Bias Adjustment Circuit moves the VBIAS voltage (the gate voltage of the FET) to meet the average
IDQ bias point for optimum amplifier performance.
State 4: Power Off Mode
During power saving or power-off modes the X9470
can be shut down via the SHDN pin. This pin pulls the
output of the VBIAS pin LOW.
Figure 6. Dynamic Biasing Technique: Automatic DC Bias Operating Point Adjustment
State 0
Monitor
Mode
State 1
Calibration
(no RF present)
State 3
Recalibrate bias
point for drift
and temperature
State 2
RF present
RF signal
VREF
State 4
shut
down
Set Operating Range Scale for Bias Adjustment
Bias Adjustment ON
CS
Bias Adjustment ON
Bias Adjustment OFF
SCL
INC/DEC
Saves wiper position to
volatile memory
BiasLock
BiasLock
SHDN
6
VBIAS
3
Rbias default is
zero point of Rtotal
2
Latch Rbias DC point
in calibration vs VREF
Shut
down
4
RF present
Turn off
Bias
Adjustment
Rbias increase/decrease
after RF present due to
temperature increase &
VGS-threshold drift
5
IDQ vs. gate
voltage bias
optimized
1
Automatic Bias Adjustment
17
FN8204.0
March 8, 2005
X9470
X9470 STATUS REGISTER (SR) AND CONTROL REGISTER (CR) INFORMATION
Table 2. Status Register (SR)
Byte
Addr
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
0F hex
SHDN
INC/DEC
0
CS
0
0
WEL
Gain
STATUS REGISTER (SR)
SR1: WEL: Write Enable Latch—Volatile
The Status Register is located at address 0F<hex>.
This is a register used to control the write enable
latches, and monitor status of the SHDN, INC/DEC,
and CS pin. This register is separate from the Control
Register.
The WEL bit controls the access to the registers during a write operation. This bit is a volatile latch that
powers up in the LOW (disabled) state. While the WEL
bit is set LOW, Nonvolatile writes to the registers will
be ignored, and all writes to registers will be volatile.
The WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the Status Register. Once
this write operation is completed and a STOP command is issued, nonvolatile writes will then occur for all
NOVRAM registers and control bits. Once set, the,
WEL bit remains set until either reset to 0 (by writing a
“0” to the WEL bit and zeroes to the other bits of the
Status Register) or until the part powers up again.
SR7: SHDN: Vbias SHDN Flag. Read Only—Volatile. The bit keeps status of the shutdown pin, SHDN.
When this bit is HIGH, the SHDN pin is active and the
VBIAS output is disabled. When this bit is LOW, the
SHDN pin is low and VBIAS output is enabled.
SR6: INC/DEC : Read Only—Volatile. This bit keeps
status of the INC/DEC pin. When this bit is HIGH the
counter is in increment mode, when this bit is LOW the
counter is in decrement mode.
SR0: Gain - NOVRAM
Selects VOUT and IA gain. When SR0=0, VOUT
gain = 20x, IA gain = 50x. When SR0 = 1, VOUT
gain = 50x, and IA gain = 20x. Default setting is 0.
SR4: CS: Read Only—Volatile. This bit keeps status
on the CS pin. When this bit is HIGH, the X9470 is in
closed loop mode (Rbias adjustment enabled). When
this bit is LOW the x9470 is in open loop mode (no
Rbias adjustments).
CONTROL REGISTERS (CR)
The control registers are organized for byte operations. Each byte has a unique byte address as shown
in Table 3 below.
SR2, SR3, SR5: Read only
For internal test usage, should be set to 0 during SR
writes.
Table 3. Control Registers (CR)
Byte
Bit
Addr.
<HEX>
Description
Reg
Name
7
6
5
4
3
2
1
0
Memory Type
00 hex
DCP for Vbias
Vbias
Vb7
Vb6
Vb5
Vb4
Vb3
Vb2
Vb1
Vb0
NOVRAM
01 hex
DCP for VREF
Vref
X
X
Vr5
Vr4
Vr3
Vr2
Vr1
Vr0
NOVRAM
Note:
02H to 0EH are reserved for internal manufacturing use.
18
FN8204.0
March 8, 2005
X9470
X9470 BUS INTERFACE INFORMATION
Figure 7. Slave Address, Word Address, and Data Bytes - Write Mode
Slave Address
Device Identifier
0
1
0
1
S2
A7
A6
A5
A4
A3
S1
A2
S0
A1
R/W=0
A0
Slave Address Byte
Byte 0
Byte Address
0Fh : SR
Byte 1
00h : VBIAS
01h : VREF
D7
D6
D5
D4
D3
D2
D1
D0
Data Byte
Byte 2
Figure 8. Slave Address, Word Address, and Data Bytes - Read Mode
Slave Address
Device Identifier
S1
S0
R/W
0
1
0
1
S2
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Slave Address Byte
Byte 0
Data Byte
Byte 1
Data Byte
Byte 2
Slave Address, Byte Address, and Data Byte
Start Condition
The byte communication format for the serial bus is
shown in Figures 7 and 8 above. The first byte, BYTE
0, defines the device indentifier, 0101 in the upper
half; and the device slave address in the low half of the
byte. The slave address is determined by the logic values of the A0, A1, and A2 pins of the X9470. This
allows for up to 8 unique addresses for the X9470. The
next byte, BYTE 1, is the Byte Address. The Byte
Address identifies a unique address for the Status or
Control Registers as shown in Table 3. The following
byte, Byte 2, is the data byte that is used for READ
and WRITE operations.
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 9.
19
FN8204.0
March 8, 2005
X9470
Stop Condition
All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 9.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device,
either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 10.
The device will respond with an acknowledge after
recognition of a start condition and if the correct
Device Identifier and Select bits are contained in the
Slave Address Byte. If a write operation is selected,
the device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for:
– The Slave Address Byte when the Device Identifier
and/or Select bits are incorrect
– The 2nd Data Byte of a Status Register Write Operation (only 1 data byte is allowed)
Figure 9. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
Figure 10. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
Start
Acknowledge
Figure 11. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
20
Data Change
Data Stable
FN8204.0
March 8, 2005
X9470
WRITE OPERATIONS
READ OPERATIONS
Byte Write
There are three basic read operations: Current
Address Read, Random Read, and Sequential Read.
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the
array. Upon receipt of each address byte, the X9470
responds with an acknowledge. After receiving the
address bytes the X9470 awaits the eight bits of data.
After receiving the 8 data bits, the X9470 again
responds with an acknowledge. The master then terminates the transfer by generating a stop condition.
The X9470 then begins an internal write cycle of the
data to the nonvolatile memory. During the internal
write cycle, the device inputs are disabled, so the
device will not respond to any requests from the master.
The SDA output is at high impedance. See Figure 12.
A write to a protected block of memory is ignored, but
will still receive an acknowledge. At the end of the
write command, the X9470 will not initiate an internal
write cycle, and will continue to ACK commands.
Current Address Read
Internally the X9470 contains an address counter that
maintains the address of the last word read incremented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power-up, the address is initialized to 0h. In this way, a current address read immediately after the power-on reset can download the entire
contents of memory starting at the first location. Upon
receipt of the Slave Address Byte with the R/W bit set
to one, the X9470 issues an acknowledge, then transmits eight data bits. The master terminates the read
operation by not responding with an acknowledge during the ninth clock and issuing a stop condition. Refer
to Figure 13 for the address, acknowledge, and data
transfer sequence.
Stops and Write Modes
Stop conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte
and it’s associated ACK signal. If a stop is issued in the
middle of a data byte, or before 1 full data byte + ACK is
sent, then the X9470 resets itself without performing the
write. The contents of the array are not affected.
Acknowledge Polling
Disabling of the inputs during nonvolatile write cycles
can be used to take advantage of the typical 5ms write
cycle time. Once the stop condition is issued to indicate the end of the master’s byte load operation, the
X9470 initiates the internal nonvolatile write cycle.
Acknowledge polling can begin immediately. To do
this, the master issues a start condition followed by the
Slave Address Byte for a write or read operation. If the
X9470 is still busy with the nonvolatile write cycle then
no ACK will be returned. When the X9470 has completed the write operation, an ACK is returned and the
host can proceed with the read or write operation.
Refer to the flow chart in Figure 15.
21
FN8204.0
March 8, 2005
X9470
Figure 12. Byte Write Sequence
S
t Device
a
ID
r
t
Signals from
the Master
SDA Bus
Slave
Address
Byte
Address 0
S
t
o
p
Data
0 1 0 1 A2 A1 A0 0
A
C
K
Signals From
The Slave
A
C
K
A
C
K
Figure 13. Current Address Read Sequence
Signals from the
Master
S
t Device
a
ID
r
t
SDA Bus
S
t
o
p
Slave
Address
0 1 0 1 A2 A1 A0 1
A
C
K
Signals from
the Slave
Data
A
C
K
Figure 14. Random Address Read Sequence
S
t Device
a ID
r
t
Signals from the
Master
SDA Bus
Slave
Address
S
t Device
a ID
r
t
Byte
Address 0
0 1 0 1 A2 A1 A0 1
0 1 0 1 A2 A1 A0 0
A
C
K
Signals from
the Slave
22
S
t
o
p
Slave
Address
A
C
K
A
C
K
Data
A
C
K
FN8204.0
March 8, 2005
X9470
Figure 15. Acknowledge Polling Sequence
Random read operations allows the master to access
any location in the X9470. Prior to issuing the Slave
Address Byte with the R/W bit set to zero, the master
must first perform a “dummy” write operation.
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue START
Issue Slave
Address Byte
(Read or Write)
Issue STOP
NO
ACK
returned?
YES
nonvolatile write
Cycle complete.
Continue command
sequence?
Random Read
NO
Issue STOP
YES
Continue normal
Read or Write
command
sequence
The master issues the start condition and the slave
address byte, receives an acknowledge, then issues
the word address bytes. After acknowledging receipt
of each word address byte, the master immediately
issues another start condition and the slave address
byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
data word. The master terminates the read operation
by not responding with an acknowledge and then issuing a stop condition. Refer to Figure 13 for the
address, acknowledge, and data transfer sequence.
In a similar operation called “Set Current Address,” the
device sets the address if a stop is issued instead of
the second start shown in Figure 14. The X9470 then
goes into standby mode after the stop and all bus
activity will be ignored until a start is detected. This
operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
PROCEED
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
23
FN8204.0
March 8, 2005
X9470
PACKAGING INFORMATION
24-Lead Plastic, TSSOP Package Type V
.026 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.303 (7.70)
.311 (7.90)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.06)
.005 (.15)
.010 (.25)
Gage Plane
0° - 8 °
Seating Plane
.020 (.50)
.030 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
24
FN8204.0
March 8, 2005
Similar pages