DATASHEET

CA3054
Data Sheet
September 22, 2005
Dual Independent Differential Amp for
Low Power Applications from DC to
120MHz
FN388.6
Features
• Two Differential Amplifiers on a Common Substrate
• Independently Accessible Inputs and Outputs
The CA3054 consists of two independent differential
amplifiers with associated constant current transistors on a
common monolithic substrate. The six NPN transistors which
comprise the amplifiers are general purpose devices which
exhibit low 1/f noise and a value of fT in excess of 300MHz.
These feature make the CA3054 useful from DC to 120MHz.
Bias and load resistors have been omitted to provide
maximum application flexibility.
• Maximum Input Offset Voltage . . . . . . . . . . . . . . . . . ±5mV
The monolithic construction of the CA3054 provides close
electrical and thermal matching of the amplifiers. This
feature makes these devices particularly useful in dual
channel applications where matched performance of the two
channels is required.
• Dual Schmitt Triggers
TEMP.
RANGE (°C)
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Dual Sense Amplifiers
• Multifunction Combinations
- RF/Mixer/Oscillator; Converter/IF
• IF Amplifiers (Differential and/or Cascode)
• Product Detectors
Ordering Information
PART NUMBER
(BRAND)
• Temperature Range . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
• Doubly Balanced Modulators and Demodulators
PACKAGE
PKG.
DWG. #
• Balanced Quadrature Detectors
• Cascade Limiters
CA3054M96
(3054)
0 to 85
14 Ld SOIC
Tape and Reel
M14.15
CA3054MZ
(CA3054MZ)
0 to 85
14 Ld SOIC
(Pb-free)
M14.15
CA3054MZ96
(CA3054MZ)
0 to 85
14 Ld SOIC Tape M14.15
and Reel (Pb-free)
• Synchronous Detectors
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
• Pairs of Balanced Mixers
• Synthesizer Mixers
• Balanced (Push-Pull) Cascode Amplifiers
Pinout
CA3054 (SOIC)
TOP VIEW
1
2
14
Q2 Q1
3
4
SUBSTRATE 5
6
7
1
13
12
Q3
11
Q4
Q5 Q6
10 NC
9
8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright Harri Corporation 1998. Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
CA3054
Absolute Maximum Ratings TA = 25°C
Thermal Information
Collector-to-Emitter Voltage, VCEO . . . . . . . . . . . . . . . . . . . . . . 15V
Collector-to-Base Voltage, VCBO . . . . . . . . . . . . . . . . . . . . . . . . 20V
Collector-to-Substrate Voltage, VCIO (Note 1) . . . . . . . . . . . . . . 20V
Emitter-to-Base Voltage, VEBO . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
Collector Current, IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Thermal Resistance (Typical, Note 2)
θJA (°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
140
Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . . . 175°C
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(Lead Tips Only)
Maximum Power Dissipation (Any One Transistor) . . . . . . . 300mW
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The collector of each transistor of the CA3054 is isolated from the substrate by an integral diode. The substrate must be connected to a voltage
which is more negative than any collector voltage in order to maintain isolation between transistors and provide for normal transistor action. The
substrate should be maintained at signal (AC) ground by means of a suitable grounding capacitor, to avoid undesired coupling between transistors.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Maximum Voltage Ratings
Maximum
Current Ratings
The following chart gives the range of voltages which can be applied to the terminals listed vertically with respect to the terminals listed horizontally. For example, the voltage range of the vertical Terminal 2 with respect to Terminal 4 is +15V to -5V.
(NOTE 4)
TERM
NO.
13
13
14
1
2
0, -20
Note 3
+5, -5
3
4
6
7
8
9
11
Note 3 +15, -5 Note 3 Note 3 Note 3 Note 3 Note 3
(NOTE 4)
TERM
IIN
NO.
mA
IOUT
mA
12
5
Note 3
Note 3
13
5
0.1
14
Note 3 Note 3 Note 3 +20, 0 Note 3 Note 3 Note 3 Note 3 Note 3
Note 3
+20, 0
14
50
0.1
1
+20, 0 Note 3 +20, 0 Note 3 Note 3 Note 3 Note 3 Note 3
Note 3
+20, 0
1
50
0.1
2
Note 3 +15, -5 Note 3 Note 3 Note 3 Note 3 Note 3
Note 3
Note 3
2
5
0.1
Note 3 Note 3 Note 3 Note 3 Note 3
Note 3
Note 3
3
5
0.1
Note 3 Note 3 Note 3 Note 3 Note 3
Note 3
Note 3
4
0.1
50
Note 3 +15, -5 Note 3
6
5
0.1
3
+1, -5
4
6
0, -20
Note 3
+5, -5
7
Note 3 Note 3 Note 3
Note 3
+20, 0
7
50
0.1
8
+20, 0 Note 3
Note 3
+20, 0
8
50
0.1
9
Note 3 +15, -5 Note 3
9
5
0.1
11
-1, -5
Note 3
11
5
0.1
12
Note 3
12
0.1
50
5
Ref.
Substrate
NOTES:
3. Voltages are not normally applied between these terminals. Voltages appearing between these terminals will be safe
if the specified limits between all other terminals are not exceeded.
4. Terminal No. 10 of CA3054 is not used.
Electrical Specifications TA = 25°C
PARAMETER
DC CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
For Each Differential Amplifier
Input Offset Voltage (Figure 8)
VIO
VCB = 3V, IE(Q3) = IE(Q4) = 2mA
-
0.45
5
mV
Input Offset Current (Figure 9)
IIO
VCB = 3V, IE(Q3) = IE(Q4) = 2mA
-
0.3
2
µA
Input Bias Current (Figure 5)
Quiescent Operating Current Ratio
(Figure 5)
Temperature Coefficient Magnitude of
Input Offset Voltage (Figure 7)
2
II
VCB = 3V, IE(Q3) = IE(Q4) = 2mA
-
10
24
µA
I C(Q1)
I C(Q5)
------------------ or -----------------I C(Q2)
I C(Q6)
VCB = 3V, IE(Q3) = IE(Q4) = 2mA
-
0.98 to
1.02
-
-
∆V IO
----------------∆T
VCB = 3V, IE(Q3) = IE(Q4) = 2mA
-
1.1
-
µV/°C
CA3054
Electrical Specifications TA = 25°C (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FOR EACH TRANSISTOR
DC Forward Base-to-Emitter Voltage
(Figure 8)
Temperature Coefficient of Base-to-Emitter
Voltage (Figure 6)
Collector Cutoff Current (Figure 4)
VBE
∆V BE
---------------∆T
ICBO
VCB = 3V
IC = 50µA
-
0.630
0.700
V
IC = 1mA
-
0.715
0.800
V
IC = 3mA
-
0.750
0.850
V
IC = 10mA
-
0.800
0.900
V
VCB = 3V, IC = 1mA
-
-1.9
-
µV/°C
VCB = 10V, IE = 0
-
0.002
100
nA
Collector-to-Emitter Breakdown Voltage
V(BR)CEO
IC = 1mA, IB = 0
15
24
-
V
Collector-to-Base Breakdown Voltage
V(BR)CBO
IC = 10µA, IE = 0
20
60
-
V
Collector-to-Substrate Breakdown
Voltage
V(BR)CIO
IC = 10µA, ICI = 0
20
60
-
V
Emitter-to-Base Breakdown Voltage
V(BR)EBO
IE = 10µA, IC = 0
5
7
-
V
DYNAMIC CHARACTERISTICS
Common Mode Rejection Ratio for each
Amplifier (Figures 1, 10)
CMRR
VCC = 12V, VEE = -6V,
VX = -3.3V, f = 1kHz
-
100
-
dB
AGC Range, One Stage (Figures 2, 11)
AGC
VCC = 12V, VEE = -6V,
VX = -3.3V, f = 1kHz
-
75
-
dB
A
VCC = 12V, VEE = -6V,
VX = -3.3V, f = 1kHz
-
32
-
dB
AGC
VCC = 12V, VEE = -6V,
VX = -3.3V, f = 1kHz
-
105
-
dB
A
VCC = 12V, VEE = -6V,
VX = -3.3V, f = 1kHz
-
60
-
dB
Voltage Gain, Single Stage Double-Ended
Output (Figures 2, 11)
AGC Range, Two Stage (Figures 3, 12)
Voltage Gain, Two Stage Double-Ended Output
(Figures 3, 12)
Low Frequency, Small Signal Equivalent Circuit Characteristics (For Single Transistor)
Forward Current Transfer Ratio (Figure 13)
hFE
f = 1kHz, VCE = 3V, IC = 1mA
-
110
-
-
Short Circuit Input Impedance (Figure 13)
hIE
f = 1kHz, VCE = 3V, IC = 1mA
-
3.5
-
kΩ
Open Circuit Output Impedance
(Figure 13)
hOE
f = 1kHz, VCE = 3V, IC = 1mA
-
15.6
-
µS
Open Circuit Reverse Voltage Transfer
Ratio (Figure 13)
hRE
f = 1kHz, VCE = 3V, IC = 1mA
-
1.8 x
10-4
-
-
1/f Noise Figure for Single Transistor
NF
f = 1kHz, VCE = 3V
-
3.25
-
dB
Gain Bandwidth Product for Single
Transistor (Figure 14)
fT
VCE = 3V, IC = 3mA
-
550
-
MHz
Admittance Characteristics; Differential
Circuit Configuration (For Each Amplifier)
Forward Transfer Admittance (Figure 15)
Y21
VCB = 3V, f = 1MHz
Each Collector IC ≈ 1.25mA
-
-20 + j0
-
mS
Input Admittance (Figure 16)
Y11
VCB = 3V, f = 1MHz
Each Collector IC ≈ 1.25mA
-
0.22 +
j0.1
-
mS
Output Admittance (Figure 17)
Y22
VCB = 3V, f = 1MHz
Each Collector IC ≈ 1.25mA
-
0.01 +
j0
-
mS
Reverse Transfer Admittance (Figure 18)
Y12
VCB = 3V, f = 1MHz
Each Collector IC ≈ 1.25mA
-
-0.003
+ j0
-
mS
3
CA3054
Electrical Specifications TA = 25°C (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Admittance Characteristics; Cascode Circuit Configuration (For Each Amplifier)
Forward Transfer Admittance (Figure 19)
Y21
VCB = 3V, f = 1MHz
Total Stage IC ≈ 2.5 mA
-
68 - j0
-
mS
Input Admittance (Figure 20)
Y11
VCB = 3V, f = 1MHz
Total Stage IC ≈ 2.5 mA
-
0.55 +
j0
-
mS
Output Admittance (Figure 21)
Y22
VCB = 3V, f = 1MHz
Total Stage IC ≈ 2.5 mA
-
0+
j0.02
-
mS
Reverse Transfer Admittance (Figure 22)
Y12
VCB = 3V, f = 1MHz
Total Stage IC ≈ 2.5 mA
-
0.004 j0.005
-
µS
NF
f = 100MHz
-
8
-
dB
Noise Figure
Test Circuits
VX
0.1µF
1kΩ
VIN = 0.3VRMS
VX
VCC = +12V
VIN = 10mVRMS
7
11
7
10µF
9
9
VOUT
ICUT
6
SIGNAL
SOURCE
8
0.5kΩ
8
1kΩ
12
0.5kΩ
1kΩ
1kΩ
VCC = +12V
0.1µF
VEE = -6V
VEE = -6V
FIGURE 1. COMMON MODE REJECTION RATIO TEST SETUP
FIGURE 2. SINGLE STAGE VOLTAGE GAIN TEST SETUP
VCC = +12V
1µF
1kΩ
1kΩ
0.1µF
1kΩ
VIN = 1mVRMS
2
10µF
0.5kΩ
7
1
9
4
0.1µF
6
1kΩ
SIGNAL
SOURCE
VOUT
ICUT
3
1kΩ
VEE = -6V
12
11
8
14
13
VX
1kΩ
1kΩ
0.5kΩ
1kΩ
1µF
VCC = +12V
FIGURE 3. TWO STAGE VOLTAGE GAIN TEST SETUP
4
12
0.5kΩ
VCC = +12V
0.1µF
VOUT
ICUT
1kΩ
6
SIGNAL
SOURCE
0.1µF
1kΩ
11
10µF
VCC = +12V
CA3054
Typical Performance Curves
100
VCB = 3V
TA = 25°C
IE = 0
INPUT BIAS CURRENT (µA)
COLLECTOR CUTOFF CURRENT (nA)
102
10
VCB = 15V
VCB = 10V
VCB = 5V
1
10-1
10-2
10-3
10-4
0
25
50
75
100
TEMPERATURE (°C) (NOTE)
10.0
1.0
0.1
125
1.0
COLLECTOR CURRENT (mA)
10
NOTE: For CA3054 use data from 0°C to 85°C only.
FIGURE 5. INPUT BIAS CURRENT vs COLLECTOR CURRENT
FOR EACH TRANSISTOR
5
VCB = 3V
VCB = 3V
1.0
4
OFFSET VOLTAGE (mV)
BASE-TO-EMITTER VOLTAGE (V)
FIGURE 4. COLLECTOR-TO-BASE CUTOFF CURRENT vs
TEMPERATURE FOR EACH TRANSISTOR
0.9
0.8
0.7
0.5
IE = 3mA
IE = 1mA
IE = 0.5mA
0.4
-75
-50
0.6
-25
0
IE = 10mA
3
2
0.75
IE = 1mA
0.50
IE = 0.1mA
0.25
25
50
75
100
0
-75
125
-50
TEMPERATURE (°C) (NOTE)
3
VBE
0.6
2
0.5
1
VIO = |VBE1 - VBE2|
0
10
FIGURE 8. STATIC BASE-TO-EMITTER VOLTAGE AND INPUT
OFFSET VOLTAGE FOR DIFFERENTIAL PAIRS vs
EMITTER CURRENT
INPUT OFFSET CURRENT (µA)
0.7
INPUT OFFSET VOLTAGE Q1 AND Q2 (mV)
BASE-TO-EMITTER VOLTAGE (V)
10
4
5
50
75
100
125
FIGURE 7. OFFSET VOLTAGE vs TEMPERATURE FOR
DIFFERENTIAL PAIRS
VCB = 3V
TA = 25°C
0.1
1.0
EMITTER CURRENT (mA)
25
NOTE: For CA3054 use data from 0°C to 85°C only.
FIGURE 6. BASE-TO-EMITTER VOLTAGE FOR EACH
TRANSISTOR vs TEMPERATURE
0.4
0.01
0
TEMPERATURE (°C) (NOTE)
NOTE: For CA3054 use data from 0°C to 85°C only.
0.8
-25
VCB = 3V
TA = 25°C
1.0
0.1
0.01
0.01
0.1
1.0
10
COLLECTOR CURRENT (mA)
FIGURE 9. INPUT OFFSET CURRENT FOR MATCHED
DIFFERENTIAL PAIRS vs COLLECTOR CURRENT
CA3054
Typical Performance Curves
(Continued)
SINGLE STAGE VOLTAGE GAIN (dB)
COMMON MODE REJECTION RATIO (dB)
100
VCC = 12V
VEE = -6V
110
f = 1kHz
100
90
80
-1
-2
-3
BIAS VOLTAGE ON TERMINAL 11 (V)
50
25
0
-25
0
-4
100
NORMALIZED h PARAMETERS
25
0
-25
-50
-1
-2
-3
-4
-5
-6
BIAS VOLTAGE ON TERMINALS 3 AND 11 (V)
-7
FIGURE 12. TWO STAGE VOLTAGE GAIN CHARACTERISTIC
800
700
600
500
400
300
200
100
1
2
3
hIE
10
4 5 6 7 8 9 10 11
COLLECTOR CURRENT (mA)
12 13 14
FIGURE 14. GAIN BANDWIDTH PRODUCT (fT) vs COLLECTOR
CURRENT
6
-4
-5
hFE = 110
hIE = 3.5kΩ
hRE = 1.88 x 10-4
hOE = 15.6µS
AT
1mA
-6
-7
hOE
hRE
hFE
1.0
hRE
hIE
0.1
0.01
0.1
1.0
COLLECTOR CURRENT (mA)
10
FIGURE 13. FORWARD CURRENT TRANSFER RATIO (hFE),
SHORT CIRCUIT INPUT IMPEDANCE (hIE), OPEN
CIRCUIT OUTPUT IMPEDANCE (hOE), AND OPEN
CIRCUIT REVERSE VOLTAGE TRANSFER RATIO
(hRE) vs COLLECTOR CURRENT FOR EACH
TRANSISTOR
FORWARD TRANSFER SUSCEPTANCE
OR CONDUCTANCE (mS)
900
0
VCB = 3V
f = 1kHz
TA = 25°C
30
VCB = 3V
TA = 25°C
1000
-3
100
50
0
-2
FIGURE 11. SINGLE STAGE VOLTAGE GAIN CHARACTERISTIC
VCC = 12V
VEE = -6V
f = 1kHz
SIGNAL INPUT = 1mVRMS
75
-1
BIAS VOLTAGE ON TERMINAL 11 (V)
FIGURE 10. COMMON MODE REJECTION RATIO
CHARACTERISTIC
TWO STAGE VOLTAGE GAIN (dB)
75
-50
0
GAIN BANDWIDTH PRODUCT (MHz)
VCC = 12V
VEE = -6V
f = 1kHz
SIGNAL INPUT = 10mVRMS
20
DIFFERENTIAL CONFIGURATION
IC (EACH TRANSISTOR) ≅ 1.25mA
VCB = 3V
TA = 25°C
10
b21
0
-10
g21
-20
0.1
1.0
10
FREQUENCY (MHz)
100
FIGURE 15. FORWARD TRANSFER ADMITTANCE (Y21) vs
FREQUENCY
CA3054
Typical Performance Curves
3
DIFFERENTIAL CONFIGURATION
IC (EACH TRANSISTOR) ≅ 1.25mA
OUTPUT CONDUCTANCE (mS)
4
3
b11
2
g11
0.4
2
0.3
0.2
1
b22
0.1
g22
0
100
0
0
1
10
FREQUENCY (MHz)
1000
DIFFERENTIAL CONFIGURATION
VCB = 3V
IC (EACH TRANSISTOR) ≅ 1.25mA
TA = 25°C
1
100
b12
10
0.1
g12
0.01
1
-g12
0.1
0.001
0.0001
0.1
1
10
FREQUENCY (MHz)
100
0.01
1000
FIGURE 18. REVERSE TRANSFER ADMITTANCE (Y12) vs
FREQUENCY
5
CASCODE CONFIGURATION
IC (STAGE) ≅ 2.5mA
VCB = 3V
TA = 25°C
3
2
0
0.1
g11
b11
1
10
FREQUENCY (MHz)
100 200
FIGURE 20. INPUT ADMITTANCE (Y11) vs FREQUENCY
7
g21
60
40
CASCODE CONFIGURATION
IC (STAGE) ≅ 2.5mA
20
VCB = 3V
TA = 25°C
0
-20
b21
-40
1
10
FREQUENCY (MHz)
100 200
FIGURE 19. FORWARD TRANSFER ADMITTANCE (Y21) vs
FREQUENCY
g22
4
1
10
FREQUENCY (MHz)
80
0.1
OUTPUT CONDUCTANCE (mS x 10-4)
6
1
FIGURE 17. OUTPUT ADMITTANCE (Y22) vs FREQUENCY
REVERSE TRANSFER SUSCEPTANCE (µS)
FIGURE 16. INPUT ADMITTANCE (Y11)
10
0.1
100
FORWARD TRANSFER CONDUCTANCE OR
SUSCEPTANCE (mS)
0.1
REVERSE TRANSFER CONDUCTANCE (mS)
VCB = 3V
TA = 25°C
OUTPUT SUSCEPTANCE (mS)
0.5
VCB = 3V
TA = 25°C
1
INPUT CONDUCTANCE OR
SUSCEPTANCE (mS)
DIFFERENTIAL CONFIGURATION
IC (EACH TRANSISTOR) ≅ 1.25mA
0
2
-2
-4
-6
CASCODE CONFIGURATION
IC (STAGE) ≅ 2.5mA
VCB = 3V
TA = 25°C
1
-8
b22
-10
0
-12
0.1
1
10
FREQUENCY (MHz)
100
FIGURE 21. OUTPUT ADMITTANCE (Y22) vs FREQUENCY
OUTPUT SUSCEPTANCE (mS)
5
INPUT SUSCEPTANCE OR
CONDUCTANCE (mS)
(Continued)
CA3054
REVERSE TRANSFER CONDUCTANCE OR
SUSCEPTANCE (µS)
Typical Performance Curves
(Continued)
100
CASCODE CONFIGURATION
IC (STAGE) ≅ 2.5mA
10
VCB = 3V
TA = 25°C
g12
1
-b12
0.1
0.01
0.001
0.1
1
10
FREQUENCY (MHz)
100 200
FIGURE 22. REVERSE TRANSFER ADMITTANCE (Y12) vs FREQUENCY
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