DATASHEET

CA3127
®
Data Sheet
June 5, 2006
FN662.5
High Frequency NPN Transistor Array
Features
The CA3127 consists of five general purpose silicon NPN
transistors on a common monolithic substrate. Each of the
completely isolated transistors exhibits low 1/f noise and a
value of fT in excess of 1GHz, making the CA3127 useful
from DC to 500MHz. Access is provided to each of the
terminals for the individual transistors and a separate
substrate connection has been provided for maximum
application flexibility. The monolithic construction of the
CA3127 provides close electrical and thermal matching of
the five transistors.
• Gain Bandwidth Product (fT) . . . . . . . . . . . . . . . . . >1GHz
Ordering Information
• Multifunction Combinations - RF/Mixer/Oscillator
PART
NUMBER
PART
MARKING
• Power Gain . . . . . . . . . . . . . . . . . . 30dB (Typ) at 100MHz
• Noise Figure. . . . . . . . . . . . . . . . . 3.5dB (Typ) at 100MHz
• Five Independent Transistors on a Common Substrate
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• VHF Amplifiers
• Sense Amplifiers
TEMP.
RANGE
(°C)
PACKAGE
PKG.
DWG. #
CA3127M
CA3127
-55 to 125
16 Ld SOIC
M16.15
CA3127MZ
(Note)
CA3127MZ
-55 to 125
16 Ld SOIC
(Pb-free)
M16.15
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
• Synchronous Detectors
• VHF Mixers
• IF Converter
• IF Amplifiers
• Synthesizers
• Cascade Amplifiers
Pinout
CA3127 (SOIC)
TOP VIEW
1
16
Q1
15
2
Q2
14
3
13
4
Q5
SUBSTRATE
5
12
11
6
Q3
1
Q4
7
10
8
9
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
CA3127
Absolute Maximum Ratings
Thermal Information
The following ratings apply for each transistor in the device
Collector-to-Emitter Voltage, VCEO . . . . . . . . . . . . . . . . . . . . .15V
Collector-to-Base Voltage, VCBO . . . . . . . . . . . . . . . . . . . . . . .20V
Collector-to-Substrate Voltage, VCIO (Note 1) . . . . . . . . . . . . .20V
Collector Current, IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Thermal Resistance (Typical, Note 2)
θJA (°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
120
Maximum Power Dissipation, PD (Any One Transistor). . . . . .85mW
Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . 175°C
Maximum Junction Temperature (Plastic Packages) . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The collector of each transistor of the CA3127 is isolated from the substrate by an integral diode. The substrate (Terminal 5) must be connected to
the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS (For Each Transistor)
Collector-to-Base Breakdown Voltage
IC = 10µA, IE = 0
20
32
-
V
Collector-to-Emitter Breakdown Voltage
IC = 1mA, IB = 0
15
24
-
V
Collector-to-Substrate Breakdown-Voltage
IC1 = 10µA, IB = 0, IE = 0
20
60
-
V
Emitter-to-Base Breakdown Voltage (Note 3)
IE = 10µA, IC = 0
4
5.7
-
V
Collector-Cutoff-Current
VCE = 10V IB = 0
-
-
0.5
µA
Collector-Cutoff-Current
VCB = 10V, IE = 0
-
-
40
nA
DC Forward-Current Transfer Ratio
VCE = 6V
IC = 5mA
35
88
-
IC = 1mA
40
90
-
IC = 0.1mA
35
85
-
IC = 5mA
0.71
0.81
0.91
V
IC = 1mA
0.66
0.76
0.86
V
IC = 0.1mA
0.60
0.70
0.80
V
Base-to-Emitter Voltage
VCE = 6V
Collector-to-Emitter Saturation Voltage
IC = 10mA, IB = 1mA
-
0.26
0.50
V
Magnitude of Difference in VBE
Q1 and Q2 Matched
VCE = 6V, IC = 1mA
-
0.5
5
mV
-
0.2
3
µA
Noise Figure
f = 100kHz, RS = 500Ω, IC = 1mA
-
2.2
-
dB
Gain-Bandwidth Product
VCE = 6V, IC = 5mA
-
1.15
-
GHz
Collector-to-Base Capacitance
VCB = 6V, f = 1MHz
-
-
pF
Collector-to-Substrate Capacitance
VCI = 6V, f = 1MHz
-
See Fig.
5
-
pF
Emitter-to-Base Capacitance
VBE = 4V, f = 1MHz
-
-
pF
Voltage Gain
VCE = 6V, f = 10MHz, RL = 1kΩ, IC = 1mA
-
28
-
dB
Power Gain
Cascode Configuration
f = 100MHz, V+ = 12V, IC = 1mA
27
30
-
dB
-
3.5
-
dB
Magnitude of Difference in IB
DYNAMIC CHARACTERISTICS
Noise Figure
2
FN662.5
June 5, 2006
CA3127
Electrical Specifications
TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
400
-
Ω
-
4.6
-
kΩ
Input Capacitance
-
3.7
-
pF
Output Capacitance
-
2
-
pF
Magnitude of Forward Transadmittance
-
24
-
mS
Input Resistance
Common-Emitter Configuration
VCE = 6V, IC = 1mA, f = 200 MHz
Output Resistance
NOTE:
3. When used as a zener for reference voltage, the device must not be subjected to more than 0.1mJ of energy from any possible capacitance or
electrostatic discharge in order to prevent degradation of the junction. Maximum operating zener current should be less than 10mA.
Test Circuits
V+
10kΩ
BIAS-CURRENT
ADJ
470
pF
RL
2
51Ω
6
4
0.01
µF
1µF
VO
Q2
0.01µF
8
1µF
Q3
3
470pF
470pF
0.01
µF
7
VI GEN
FIGURE 1. VOLTAGE-GAIN TEST CIRCUIT USING CURRENT-MIRROR BIASING FOR Q2
1.5 - 8pF
VO
C2
(NOTE 5)
12
SHIELD
Q5
2
VI
1000pF
13
8.2
kΩ
0.47µH
14
620Ω
1000
pF
1000
pF
0.3µH
4
Q2
560Ω
1.8pF
C1
(NOTE 5)
TEST
POINT
NOTES:
750Ω
1%
3
1000
pF
OHMITE
Z144
6
+12V
25kΩ
8
Q3
1000
pF
7
5
4. This circuit was chosen because it conveniently
represents a close approximation in performance to a
properly unilateralized single transistor of this type. The
use of Q3 in a current-mirror configuration facilitates
simplified biasing. The use of the cascode circuit in no
way implies that the transistors cannot be used
individually.
5. E.F. Johnson number 160-104-1 or equivalent.
FIGURE 2. 100MHz POWER-GAIN AND NOISE-FIGURE TEST CIRCUIT
3
FN662.5
June 5, 2006
CA3127
GENERAL RADIO 1021-P1
100MHz GENERATOR
ATTN
100MHz
TEST SET
BOONTON 91C
RF VOLTMETER
12VDC
POWER SUPPLY
FIGURE 3A. POWER GAIN SET-UP
VHF NOISE SOURCE
HEWLETT PACKARD HP343A
100MHz
TEST SET
100MHz
POST AMPLIFIER
12VDC
POWER SUPPLY
15VDC
POWER SUPPLY
NOISE FIGURE METER
HEWLETT PACKARD HP342A
FIGURE 3B. NOISE FIGURE SET-UP
FIGURE 3. BLOCK DIAGRAMS OF POWER-GAIN AND NOISE-FIGURE TEST SET-UPS
Typical Performance Curves
TA = 25°C
VCE = 6V
RSOURCE = 500Ω
f = 10Hz
30
f = 100Hz
20
f = 1kHz
10
f = 10kHz
f = 100kHz
NOISE FIGURE (dB)
NOISE FIGURE (dB)
30
TA = 25°C
VCE = 6V
RSOURCE = 1kΩ
f = 10Hz
f = 100Hz
20
f = 1kHz
f = 10kHz
10
f = 100kHz
0
0.01
0.1
1.0
COLLECTOR CURRENT (mA)
FIGURE 4. NOISE FIGURE vs COLLECTOR CURRENT
4
0
0.01
0.1
1.0
COLLECTOR CURRENT (mA)
FIGURE 5. NOISE FIGURE vs COLLECTOR CURRENT
FN662.5
June 5, 2006
CA3127
Typical Performance Curves
(Continued)
1.0
BASE-TO-EMITTER VOLTAGE (V)
GAIN-BANDWIDTH PRODUCT (GHz)
TA = 25°C
VCE = 6V
1.2
1.1
1.0
0.9
TA = -55°C
0.9
TA = 25°C
0.8
0.7
TA = 125°C
0.6
0.5
0.4
0.8
0
1
2
3
4
5
6
7
8
9
10
0.1
1
COLLECTOR CURRENT (mA)
COLLECTOR CURRENT (mA)
FIGURE 6. GAIN-BANDWIDTH PRODUCT vs COLLECTOR
CURRENT
FIGURE 7. BASE-TO-EMITTER VOLTAGE vs COLLECTOR
CURRENT
TA = 25°C
f = 1MHz
CAPACITANCE (pF)
CCE
CCB
2.25
TRANSISTOR
2.00
CAPACITANCE (pF)
10
CEB
CCI
PKG TOTAL PKG TOTAL PKG TOTAL PKG TOTAL
1.50
BIAS
(V)
1.25
Q1
0.025 0.190 0.090 0.125 0.365 0.610 0.475 1.65
1.00
Q2
0.015 0.170 0.225 0.265 0.130 0.360 0.085 1.35
Q3
0.040 0.200 0.215 0.240 0.360 0.625 0.210 1.40
Q4
0.040 0.190 0.225 0.270 0.365 0.610 0.085 1.25
Q5
0.010 0.165 0.095 0.115 0.140 0.365 0.090 1.35
1.75
CCI
0.75
CEB
0.50
CCB
0.25
0
1
2
3
4
5
6
7
8
9
-
6V
-
6V
-
4V
-
6V
10
BIAS VOLTAGE (V)
FIGURE 8A. CAPACITANCE vs BIAS VOLTAGE FOR Q2
5
FIGURE 8B. TYPICAL CAPACITANCE VALUES AT f = 1MHz.
THREE TERMINAL MEASUREMENT. GUARD ALL
TERMINALS EXCEPT THOSE UNDER TEST.
FN662.5
June 5, 2006
CA3127
Typical Performance Curves
(Continued)
40
40
TA = 25°C, VCE = 6V, RL = 100Ω
FOR TEST CIRCUIT SEE FIGURE 19
35
IC = 1mA
30
25
VOLTAGE GAIN (dB)
30
VOLTAGE GAIN (dB)
IC = 5mA
35
IC = 5mA
20
15
IC = 1mA
10
IC = 0.5mA
5
IC = 0.2mA
0
25
IC = 0.5mA
20
IC = 0.2mA
15
10
5
0
-5
-5
-10
1M
10M
100M
FREQUENCY (Hz)
-10
1M
1G
TA = 25°C, VCE = 6V, RL = 1kΩ
FOR TEST CIRCUIT SEE FIGURE 19
10M
100M
FREQUENCY (Hz)
1G
FIGURE 10. VOLTAGE GAIN vs FREQUENCY
100
TA = 25°C
TA = 25°C, VCE = 6V, IC = 1mA
8
80
70
60
50
40
0.1
1.0
COLLECTOR CURRENT (mA)
FIGURE 11. DC FORWARD-CURRENT TRANSFER RATIO
(hFE) vs COLLECTOR CURRENT
6
10
7
SUSCEPTANCE (b11) (mS)
90
VCE = 6V
INPUT CONDUCTANCE (g11) OR
DC FORWARD CURRENT TRANSFER RATIO
FIGURE 9. VOLTAGE GAIN vs FREQUENCY
b11
6
5
4
g11
3
2
1
0
100M
1G
FREQUENCY (Hz)
FIGURE 12. INPUT ADMITTANCE (Y11) vs FREQUENCY
FN662.5
June 5, 2006
CA3127
(Continued)
OUTPUT CONDUCTANCE (g22) (mS)
9
8
g11
7
6
5
b11
4
3
2
1
0
1
2
3
4
5
6
7
8
COLLECTOR CURRENT (mA)
9
10
b22
2.8
2.7
0.350
2.6
g22
2.5
0.300
2.4
0.275
2.3
0.250
2.2
0.225
2.1
0.200
2.0
0.175
0
1
2
0.9
0.8
8
b22
0.7
7
0.6
6
0.5
5
0.4
4
0.3
3
g22
0.2
2
0.1
1
0
1G
FIGURE 14. OUTPUT ADMITTANCE (Y22) vs FREQUENCY
TA = 25°C
0.375
0.325
1.0
FREQUENCY (Hz)
3
4 5 6 7 8 9 10 11
COLLECTOR CURRENT (mA)
1.9
12
FIGURE 15. OUTPUT ADMITTANCE (Y22) vs COLLECTOR
CURRENT
7
OUTPUT SUSCEPTANCE (b22) (mS)
OUTPUT CONDUCTANCE (g22) (mS)
0.400
1.1
0
100M
FIGURE 13. INPUT ADMITTANCE (Y11) vs COLLECTOR
CURRENT
TA = 25°C
VCE = 6V
f = 200MHz
TA = 25°C
VCE = 6V
IC = 1mA
VCE = 6V
f = 200MHz
100
0
80
-20
|Y21|
60
40
θ21
-40
-60
-80
20
0
1
2
PHASE-ANGLE OF FORWARD
TRANSADMITTANCE (|θ21|) (°)
0
1.3
1.2
MAGNITUDE OF FORWARD
TRANSADMITTANCE (|Y21|) (mS)
SUSCEPTANCE (b11) (mS)
INPUT CONDUCTANCE (g11) OR
TA = 25°C
VCE = 6V
f = 200MHz
OUTPUT SUSCEPTANCE (b22) (mS)
Typical Performance Curves
-100
3 4 5 6 7 8 9 10 11 12
COLLECTOR CURRENT (mA)
FIGURE 16. FORWARD TRANSADMITTANCE (Y21) vs
COLLECTOR CURRENT
FN662.5
June 5, 2006
CA3127
(Continued)
TA = 25°C
-50
-60
|Y21|
-70
20
-80
10
-90
f = 200MHz
θ12
-100
|Y12|
0.21
-110
-120
-130
-140
-100
0
1G
150M 200M
FREQUENCY (Hz)
-80
-90
FIGURE 17. FORWARD TRANSADMITTANCE (Y21) vs
FREQUENCY
1
2
-150
3 4 5 6 7 8 9 10 11 12
COLLECTOR CURRENT (mA)
FIGURE 18. REVERSE TRANSADMITTANCE (Y12) vs
COLLECTOR CURRENT
MAGNITUDE OF REVERSE
TRANSADMITTANCE (|Y12|) (mS)
TA = 25°C
VCE = 6V
IC = 1mA
0.6
0.5
-90
θ12
-95
0.4
-100
0.3
0.2
-105
|Y12|
-110
-115
0.1
0
100M
PHASE-ANGLE OF REVERSE
TRANSADMITTANCE (|θ12|) (°)
0
100M
MAGNITUDE OF REVERSE
TRANSADMITTANCE (|Y12|) (mS)
-40
θ21
PHASE-ANGLE OF FORWARD
TRANSADMITTANCE (|θ21|) (°)
MAGNITUDE OF FORWARD
TRANSADMITTANCE (|Y21|) (mS)
-20
-30
30
TA = 25°C
VCE = 6V
-10
VCE = 6V
IC = 1mA
PHASE-ANGLE OF REVERSE
TRANSADMITTANCE (|θ12|) (°)
Typical Performance Curves
-120
FREQUENCY (Hz)
1G
FIGURE 19. REVERSE TRANSADMITTANCE (Y12) vs FREQUENCY
8
FN662.5
June 5, 2006
CA3127
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
N
INDEX
AREA
H
0.25(0.010) M
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
B M
INCHES
E
-B1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
C
0.10(0.004)
0.25(0.010) M
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.3859
0.3937
9.80
10.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
B S
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
16
0°
16
8°
0°
7
8°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
FN662.5
June 5, 2006
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