DATASHEET

400MHz Multiplexing Amplifier
ISL59420
Features
The ISL59420 is a 420MHz bandwidth 2:1 multiplexing
amplifier designed primarily for video switching. This Mux-amp
has user-settable gain and also feature a high speed three-state
function to enable the output of multiple devices to be wired
together. All logic inputs have pull-downs to ground and may be
left floating. The ENABLE pin, when pulled high, sets the
ISL59420 to the low current power-down mode for power
sensitive applications - consuming just 5mW.
• 420MHz (-3dB) Bandwidth (AV = 1, VOUT = 400mVP-P)
• 165MHz (-3dB) Bandwidth (AV = 2, VOUT = 2VP-P)
• Slew Rate (AV = 1, RL = 500Ω, VOUT = 4V). . . . . . . . . . 966V/µs
• Slew Rate (AV = 2, RL = 500Ω, VOUT = 5V) . . . . . . . . .1462V/µs
• Selectable Gain
• High Speed Three-State Output (HIZ)
• Low Current Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . 5mW
TABLE 1. CHANNEL SELECT LOGIC TABLE
• Pb-Free (RoHS Compliant)
S0
ENABLE
HIZ
OUTPUT
0
0
0
IN0
Applications
1
0
0
IN1
• HDTV/DTV Analog Inputs
X
1
X
Power Down
X
0
1
High Z
• Video Projectors
• Computer Monitors
• Set-Top Boxes
Related Literature
• Security Video
• See AN1187, “ISL59420/21EVAL1 Evaluation Board User’s
Guide”
• Broadcast Video Equipment
IN-
S0
EN0
IN0
DECODE
EN1
IN1
+
OUT
AMPLIFIER BIAS
HIZ
ENABLE
ENABLE pin must be low in order to activate the HIZ state
FIGURE 1. FUNCTIONAL DIAGRAM
July 3, 2012
FN7459.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2005, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL59420
Pin Configuration
ISL59420
(10 LD MSOP)
TOP VIEW
S0
1
GND
2
IN0
10 IN9
OUT
3
8
V+
ENABLE
4
7
V-
IN1
5
6
HIZ
+
Pin Descriptions
PIN
NUMBER
PIN
NAME
EQUIVALENT
CIRCUIT
1
S0
Circuit 2
2
GND
Circuit 4
Ground pin
3
IN0
Circuit 1
Input for channel 0
4
ENABLE
Circuit 2
Device enable (active low); there are internal pull-down resistors, so the device will be active with no
connection; "HI" puts device into power-down mode.
5
IN1
Circuit 1
Input for channel 1
6
HIZ
Circuit 2
Output disable (active high); there are internal pull-down resistors, so the device will be active with no
connection; “HI” puts the output in high impedance state.
7
V-
Circuit 4
Negative power supply
8
V+
Circuit 4
Positive power supply
9
OUT
Circuit 3
Output
10
IN-
Circuit 1
Inverting input of output amplifier
DESCRIPTION
Channel selection pin LSB (binary logic code)
V+
V+
21k
IN
LOGIC PIN
33k
V-
+
1.2V
-
GND.
V-
CIRCUIT 1.
CIRCUIT 2.
V+
V+
GND
OUT
V-
CAPACITIVELY
COUPLED
ESD CLAMP
V-
CIRCUIT 3.
CIRCUIT 4.
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
PACKAGE
(Pb-free)
TAPE &
REEL
PKG.
DWG. #
ISL59420IUZ
BBPAA
10 Ld MSOP
-
M10.118A
ISL59420IUZ-T7 (Note 1)
BBPAA
10 Ld MSOP
7”
M10.118A
ISL59420IUZ-T13 (Note 1)
BBPAA
10 Ld MSOP
13”
M10.118A
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL59420. For more information on MSL please see tech brief TB363.
2
FN7459.2
July 3, 2012
ISL59420
Absolute Maximum Ratings (TA = 25°C)
Thermal Information
Supply Voltage (V+ to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V
Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/μs
IN- Input Current (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Digital & Analog Input Current (Note 4). . . . . . . . . . . . . . . . . . . . . . . . 50mA
Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7). . . . . . . . . .2.5kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figures 22 and 23 on page 8
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTE:
4. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise
noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
V+ = +5V, V- = -5V, GND = 0V, TA = 25°C, RL = 500Ω to GND unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
(NOTE 5)
TYP
MAX
(NOTE 5)
UNIT
GENERAL
±IS Enabled
Supply Current
No load, VIN = 0V, ENABLE Low
9.5
11
15
mA
IS Disabled
Disabled Supply Current I+
No load, VIN = 0V, ENABLE High
0.5
1
1.5
mA
Disabled Supply Current I-
No load, VIN = 0V, ENABLE High
3
10
μA
Positive Output Swing
VIN = 2V, RL = 500Ω, AV = 2
Negative Output Swing
VIN = -2V, RL = 500Ω, AV = 2
IOUT
Output Current
RL = 10Ω to GND
VOS
Output Offset Voltage
Ib+
Input Bias Current
Ib-
Feedback Bias Current
Rout
Output Resistance
VOUT
VIN = 0V
3.5
3.9
-3
V
-2.8
V
80
130
mA
-12
4
+12
mV
-4
-2.5
-1.5
μA
-15
7
15
μA
HIZ = logic high, (DC), AV = 1
1.4
MΩ
HIZ = logic low, (DC), AV = 1
0.2
Ω
10
MΩ
RIN
Input Resistance
VIN = 3.5V
ACL or AV
Voltage Gain
RF = RG = 600Ω, VOUT = ±3V
ITRI
Output Current in Three-state
VOUT = 0V
1.990
2.005
2.020
V/V
-20
6
20
μA
LOGIC
VH
Input High Voltage (Logic Inputs)
2
VL
Input Low Voltage (Logic Inputs)
IIH
Input High Current (Logic Inputs)
55
IIL
Input Low Current (Logic Inputs)
-10
V
0.8
V
90
135
μA
0
10
μA
AC GENERAL
- 3dB BW
-3dB Bandwidth
3
AV = 1, RF = 200Ω, VOUT = 400MVP-P, CL = 5.5pF,
CG = 0.6pF
420
MHz
AV = 2, RF = RG = 453Ω, VOUT = 2VP-P, CL = 5.5pF,
CG = 0.6pF
165
MHz
FN7459.2
July 3, 2012
ISL59420
Electrical Specifications
PARAMETER
0.1dB BW
dG
dP
+SR
-SR
V+ = +5V, V- = -5V, GND = 0V, TA = 25°C, RL = 500Ω to GND unless otherwise specified. (Continued)
DESCRIPTION
0.1dB Bandwidth
CONDITIONS
MIN
(NOTE 5)
TYP
MAX
(NOTE 5)
UNIT
AV = 1, RF = 200Ω, VOUT = 100mVP-P, CL = 5.5pF,
CG = 0.6pF
25
MHz
AV = 2, RF = RG = 453Ω, VOUT = 2VP-P, CL = 5.5pF,
CG = 0.6pF
60
MHz
NTC-7, RL = 150, CL = 5.5pF, AV = 1
0.01
%
NTC-7, RL = 150, CL = 5.5pF, AV = 2
0.05
%
NTC-7, RL = 150, CL = 5.5pF, AV = 1
0.02
°
NTC-7, RL = 150, CL = 5.5pF, AV = 2
0.02
°
25% to 75%, AV = 1, VOUT = 4V, RL = 500Ω, CL = 5.5pF
966
V/μs
25% to 75%, AV = 2, VOUT = 5V, RL = 500Ω, CL = 5.5pF
1462
V/μs
25% to 75%, AV = 1, VOUT = 4V, RL = 500Ω, CL = 5.5pF
788
V/μs
25% to 75%, AV = 2, VOUT = 5V, RL = 500Ω, CL = 5.5pF
1171
V/μs
-68
dB
75
dB
Channel-to-Channel Switching Glitch VIN = 0V, CL = 5.5pF, AV = 2
36
mVP-P
ENABLE Switching Glitch
VIN = 0V, CL = 5.5pF, AV = 2
475
mVP-P
HIZ Switching Glitch
VIN = 0V, CL = 5.5pF, AV = 2
360
mVP-P
Differential Gain Error
Differential Phase Error
Slew Rate
Slew Rate
PSRR
Power Supply Rejection Ratio
DC, PSRR V+ and V- combined
ISO
Channel Isolation
f = 10MHz, Ch-Ch X-Talk and Off Isolation, CL = 5.5pF
-60
SWITCHING CHARACTERISTICS
VGLITCH
tSW-L-H
Channel Switching Time Low to High 1.2V logic threshold to 10% movement of analog output
24
ns
tSW-H-L
Channel Switching Time High to Low 1.2V logic threshold to 10% movement of analog output
19
ns
AV = 1, RF = 200Ω, VOUT = 100mVP-P, CL = 5.5pF,
CG = 0.6pF
0.83
ns
AV = 2, RF = RG = 453Ω, VOUT = 2VP-P, CL = 5.5pF,
CG = 0.6pF
1.64
ns
TRANSIENT RESPONSE
tR, tF
Rise & Fall Time, 10% to 90%
tS
0.1% Settling Time
AV = 2, RF = RG = 453Ω, VOUT = 2VP-P, CL = 5.5pF,
CG = 0.6pF
8.8
ns
OS
Overshoot
AV = 1, RF = 200Ω, VOUT = 100mVP-P, CL = 5.5pF,
CG = 0.6pF
24
%
AV = 2, RF = RG = 453Ω, VOUT = 2VP-P, CL = 5.5pF,
CG = 0.6pF
10
%
AV = 1, RF = 200Ω, VOUT = 100mVP-P, CL = 5.5pF,
CG = 0.6pF
0.5
ns
AV = 2, RF = RG = 453Ω, VOUT = 2VP-P, CL = 5.5pF,
CG = 0.6pF
1.01
ns
AV = 1, RF = 200Ω, VOUT = 100mVP-P, CL = 5.5pF,
CG = 0.6pF
0.65
ns
AV = 2, RF = RG = 453Ω, VOUT = 2VP-P, CL = 5.5pF,
CG = 0.6pF
1.08
ns
tPLH
tPHL
Propagation Delay - Low to High,
10% to 10%
Propagation Delay- High to Low,
10% to 10%
NOTE:
5. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
4
FN7459.2
July 3, 2012
ISL59420
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified.
5
2
CL = 5.5pF
1
0
CL = 1.6pF
-1
-2
-3
CL INCLUDES 1.6pF
BOARD CAPACITANCE
-4
AV = 1
VOUT = 100mVP-P
3 CL = 5.5pF
RF = 200Ω
2
4
CL = 7.2pF
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
3
5
CL = 9.7pF
AV = 1
VOUT = 100mVP-P
RF = 200Ω
4
1
0
RL = 150Ω
-1
RL = 75Ω
-2
-3
-5
1
100
10
1
1000
10
FREQUENCY (MHz)
1000
100
FREQUENCY (MHz)
FIGURE 3. SMALL SIGNAL GAIN vs FREQUENCY vs RL
FIGURE 2. SMALL SIGNAL GAIN vs FREQUENCY vs CL
5
5
AV = 2
VOUT = 2VP-P
RG = RF = 453Ω
3
2
1
0
CL = 9.7pF
-1
CL = 7.2pF
-2
CL = 5.5pF
-3
CL = 1.6pF
CL INCLUDES 1.6pF
BOARD CAPACITANCE
-4
AV = 2
VOUT = 2VP-P
CL = 5.5pF
RG = RF = 453Ω
4
NORMALIZED GAIN (dB)
4
NORMALIZED GAIN (dB)
RL = 1kΩ
-4
-5
3
2
1
RL = 75Ω
0
-1
-2
RL = 150Ω
RL = 1kΩ
-3
RL = 75Ω
-4
RL = 500Ω
-5
-5
1
100
10
1
1000
10
1000
100
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 5. LARGE SIGNAL GAIN vs FREQUENCY vs RL
FIGURE 4. LARGE SIGNAL GAIN vs FREQUENCY vs CL
0.8
0.8
CL = 9.7pF
AV = 1
VOUT = 100mVP-P
RF = 200Ω
0.6
CL = 1.6pF
CL = 7.2pF
CL = 5.5pF
0.5
AV = 1
VOUT = 100mVP-P
CL = 5.5pF
RF = 200Ω
0.7
NORMALIZED GAIN (dB)
0.7
NORMALIZED GAIN (dB)
RL = 500Ω
0.4
0.3
0.2
0.1
0
0.6
0.5
RL = 75Ω
RL = 1kΩ
RL = 500Ω
RL = 150Ω
0.4
0.3
0.2
0.1
0
CL INCLUDES 1.6pF
BOARD CAPACITANCE
-0.1
-0.2
-0.1
-0.2
1
100
10
1000
FREQUENCY (MHz)
FIGURE 6. SMALL SIGNAL 0.1dB GAIN vs FREQUENCY vs CL
5
1
10
100
1000
FREQUENCY (MHz)
FIGURE 7. SMALL SIGNAL 0.1dB GAIN vs FREQUENCY vs RL
FN7459.2
July 3, 2012
ISL59420
0.2
0.5
0.1
0.4
0
0.3
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified. (Continued)
CL = 9.7pF
-0.1
CL = 7.2pF
-0.2
CL = 5.5pF
-0.3
CL = 1.6pF
-0.4
AV = 2
VOUT = 2VP-P
RG = RF = 453Ω
-0.5
-0.6
CL INCLUDES 1.6pF
BOARD CAPACITANCE
-0.7
AV = 2
VOUT = 2VP-P
CL = 5.5pF
RG = RF = 453Ω
0.2
RL = 75Ω
0.1
RL = 150Ω
0
RL = 1kΩ
-0.1
RL = 500Ω
-0.2
-0.3
-0.4
-0.8
-0.5
1
100
10
1
1000
10
FREQUENCY (MHz)
1000
100
FREQUENCY (MHz)
FIGURE 8. LARGE SIGNAL 0.1dB GAIN vs FREQUENCY vs CL
FIGURE 9. LARGE SIGNAL 0.1dB GAIN vs FREQUENCY vs RL
-10
20
10
0
-30
-40
-50
-20
(dB)
PSRR (dB)
-10
AV = 2
VIN = 1VP-P
CL = 5.5pF
RG = RF = 453Ω
-20
AV = 2
VIN = 200mVP-P
CL = 5.5pF
RG = RF = 453Ω
-30
-60
CROSSTALK
-70
-40
-80
-50
PSRR (V+)
-90
-60
-100
PSRR (V-)
-70
-80
0.3
1
10
100
OFF ISOLATION
1000
-110
0.001
0.01
0.1
FREQUENCY (MHz)
FIGURE 10. PSRR CHANNELS
3
6 10
100
500
FIGURE 11. CROSSTALK AND OFF ISOLATION
60
AV = 1, RF = 500Ω
INPUT VOLTAGE NOISE (nV/√Hz)
-IIN CURRENT NOISE (pA/√Hz)
24
1
FREQUENCY (MHz)
20
16
12
8
4
AV = 1, RF = 500Ω
50
40
30
20
10
0
0
0.1
1
10
FREQUENCY (kHz)
FIGURE 12. INPUT NOISE vs FREQUENCY
6
100
0.1
1
10
100
FREQUENCY (kHz)
FIGURE 13. INPUT NOISE vs FREQUENCY
FN7459.2
July 3, 2012
ISL59420
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified. (Continued)
S0
1V/DIV
1V/DIV
S0
0
1V/DIV
20mV/DIV
0
0
VOUT
VOUT
0
20ns/DIV
FIGURE 14. CHANNEL TO CHANNEL SWITCHING GLITCH VIN = 0V,
AV = 2
20ns/DIV
FIGURE 15. CHANNEL TO CHANNEL TRANSIENT RESPONSE VIN =
1V, AV = 2
ENABLE
1V/DIV
1V/DIV
ENABLE
0
1V/DIV
200mV/DIV
0
VOUT
0
VOUT
0
20ns/DIV
FIGURE 16. ENABLE SWITCHING GLITCH VIN = 0V, AV = 2
20ns/DIV
FIGURE 17. ENABLE TRANSIENT RESPONSE VIN = 1V, AV = 2
HIZ
1V/DIV
1V/DIV
HIZ
0
1V/DIV
100mV/DIV
0
0
VOUT
20ns/DIV
FIGURE 18. HIZ SWITCHING GLITCH VIN = 0V, AV = 2
7
0
VOUT
20ns/DIV
FIGURE 19. HIZ TRANSIENT RESPONSE VIN = 1V, AV = 2
FN7459.2
July 3, 2012
ISL59420
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified. (Continued)
160
2.4
AV = 1
CL = 5.5pF
RF = 200Ω
RL = 500Ω
80
2
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
120
40
0
-40
-80
1.6
1.2
0.8
0.4
AV = 2
CL = 5.5pF
RG = RF = 453Ω
RL = 500Ω
0
-0.4
-120
-160
-0.8
TIME (4ns/DIV)
TIME (4ns/DIV)
FIGURE 20. SMALL SIGNAL TRANSIENT RESPONSE
FIGURE 21. LARGE SIGNAL TRANSIENT RESPONSE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.6
1
870mW
0.8
0.7
θ
JA
0.6
0.5
M
0.5
POWER DISSIPATION (W)
POWER DISSIPATION (W)
0.9
SO
P
=1
10
15
°C
/W
0.4
0.3
0.2
486mW
0.4
θ
JA
0.3
M
SO
P
=2
10
06
°C
/W
0.2
0.1
0.1
0
0
0
25
50
75 85
100
0
125
25
50
75 85
100
125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 23. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
100
AV = 1, VOUT = 100mVP-P
OUTPUT RESISTANCE (Ω)
AV = 2, VOUT = 2VP-P
10
AV = 2
1
0.1
0.1
1
AV = 1
10
FREQUENCY (MHz)
100
1000
FIGURE 24. ROUT vs FREQUENCY
8
FN7459.2
July 3, 2012
ISL59420
AC Test Circuits
ISL59420
RG
ISL59420
RF
50Ω
or
75Ω
TEST
EQUIPMENT
RS
VIN
CL
RF
RG
AV = 1, 2
475Ω
or
462.5Ω
50Ω
or
75Ω
AV = 1, 2
RS
VIN
50Ω
or
75Ω
50Ω
or
75Ω
FIGURE 25A. TEST CIRCUIT FOR MEASURING WITH A 50Ω OR 75Ω
INPUT TERMINATED EQUIPMENT
CL
50Ω or 75Ω
TEST
EQUIPMENT
50Ω
or
75Ω
FIGURE 25B. BACKLOADED TEST CIRCUIT FOR VIDEO CABLE
APPLICATION. BANDWIDTH AND LINEARITY FOR RL
LESS THAN 500Ω WILL BE DEGRADED.
NOTE: Figure 25A illustrates the optimum output load when connecting to input terminated equipment. Figure 26B illustrates backloaded test circuit for
video cable applications.
Application Circuits
200Ω
*CL = CT + COUT
VIN
VOUT
+
50Ω
0.6pF
CT
1.6pF
CG
COUT
3.9pF
RL = 500Ω
PC BOARD
CAPACITANCE
0.4pF < CG < 0.7pF
*CL: TOTAL LOAD CAPACITANCE
CT: TRACE CAPACITANCE
COUT: OUTPUT CAPACITANCE
FIGURE 26A. GAIN OF 1 APPLICATION CIRCUIT
453Ω
*CL = CT + COUT
453Ω
VIN
VOUT
+
50Ω
0.6pF
CG
CT
1.6pF
COUT
3.9pF
RL = 500Ω
PC BOARD
CAPACITANCE
0.4pF < CG < 0.7pF
FIGURE 26B. GAIN OF 2 APPLICATION CIRCUIT
9
FN7459.2
July 3, 2012
ISL59420
Application Information
Control Signals
General
S0, ENABLE, HIZ - These pins are TTL/CMOS compatible
control inputs. The S0 pin selects which one of the inputs
connect to the output. The ENABLE, HIZ pins are used to
disable the part to save power and three-state the output
amplifiers, respectively. For control signal rise and fall times
less than 10ns the use of termination resistors close to the
part will minimize transients coupled to the output.
The ISL59420 is a 2:1 mux that is ideal as a matrix element in
high performance switchers and routers. The ISL59420 is
optimized to drive 5pF in parallel with a 500Ω load. The
capacitance can be split between the PCB capacitance and an
external load capacitance. Its low input capacitance and high
input resistance provide excellent 50Ω or 75Ω terminations.
Parasitic Effects on Frequency
Performance
Capacitance at the Inverting Input
The AC performance of current-feedback amplifiers in the
non-inverting gain configuration is strongly affected by stray
capacitance at the inverting input. Stray capacitance from the
inverting input pin to the output (CF), and to ground (CG),
increase gain peaking and bandwidth. Large values of either
capacitance can cause oscillation. The ISL59420 has been
optimized for a 0.4pF to 0.7pF capacitance (CG). Capacitance
(CF) to the output should be minimized. To achieve optimum
performance the feedback network resistor(s) must be placed
as close to the device as possible. Trace lengths greater than
1/4 inch combined with resistor pad capacitance can result in
inverting input to ground capacitance approaching 1pF.
Inverting input and output traces should not run parallel to
each other. Small size surface mount resistors (604 or
smaller) are recommended.
Capacitance at the Output
The output amplifier is optimized for capacitance to ground
(CL) directly on the output pin. Increased capacitance causes
higher peaking with an increase in bandwidth. The optimum
range for most applications is ~1.0pF to ~6pF. The optimum
value can be achieved through a combination of PC board
trace capacitance (CT) and an external capacitor (COUT). A
good method to maintain control over the output pin
capacitance is to minimize the trace length (CT) to the next
component, and include a discrete surface mount capacitor
(COUT) directly at the output pin.
Feedback Resistor Values
The AC performance of the output amplifier is optimized with
the feedback resistor network (RF, RG) values recommended in
the application circuits. The amplifier bandwidth and gain
peaking are directly affected by the value(s) of the feedback
resistor(s) in unity gain and gain >1 configurations. Transient
response performance can be tailored simply by changing
these resistor values. Generally, lower values of RF and RG
increase bandwidth and gain peaking. This has the effect of
decreasing rise/fall times and increasing overshoot.
Ground Connections
For the best isolation and crosstalk rejection, the GND pin and
NIC pins must connect to the GND plane.
10
Power-Up Considerations
The ESD protection circuits use internal diodes from all pins
the V+ and V- supplies. In addition, a dV/dT- triggered clamp is
connected between the V+ and V- pins, as shown in the
Equivalent Circuits 1 through 4 section of the Pin Description
table. The dV/dT triggered clamp imposes a maximum supply
turn-on slew rate of 1V/µs. Damaging currents can flow for
power supply rates-of-rise in excess of 1V/µs, such as during
hot plugging. Under these conditions, additional methods
should be employed to ensure the rate of rise is not exceeded.
Consideration must be given to the order in which power is
applied to the V+ and V- pins, as well as analog and logic input
pins. Schottky diodes (Motorola MBR0550T or equivalent)
connected from V+ to ground and V- to ground (Figure 24) will
shunt damaging currents away from the internal V+ and V- ESD
diodes in the event that the V+ supply is applied to the device
before the V- supply.
If positive voltages are applied to the logic or analog video
input pins before V+ is applied, current will flow through the
internal ESD diodes to the V+ pin. The presence of large
decoupling capacitors and the loading effect of other circuits
connected to V+, can result in damaging currents through the
ESD diodes and other active circuits within the device.
Therefore, adequate current limiting on the digital and analog
inputs is needed to prevent damage during the time the
voltages on these inputs are more positive than V+.
HIZ State
An internal pull-down resistor connected to the HIZ pin ensures
the device will be active with no connection to the HIZ pin. The
HIZ state is established within approximately 25ns (Figure 19)
by placing a logic high (>2V) on the HIZ pin. If the HIZ state is
selected, the output is a high impedance 1.4MΩ. Use this state
to control the logic when more than one mux shares a
common output.
In the HIZ state the output is three-stated, and maintains its high
Z even in the presence of high slew rates. The supply current
during this state is basically the same as the active state.
ENABLE & Power Down States
The enable pin is active low. An internal pull-down resistor ensures
the device will be active with no connection to the ENABLE pin.
The Power Down state is established when a logic high (>2V) is
placed on the ENABLE pin. In the Power Down state, the output
has no leakage but has a large capacitance (on the order of
15pF), and is capable of being back-driven. Under this condition,
large incoming slew rates can cause fault currents of tens of mA.
Do not use this state as a high Z state for applications driving
more than one mux on a common output.
FN7459.2
July 3, 2012
ISL59420
V+ SUPPLY
SCHOTTKY
PROTECTION
LOGIC
V+
LOGIC
CONTROL
S0
POWER
GND
GND
EXTERNAL
CIRCUITS
V+
V-
V+
V+
SIGNAL
IN0
V+
OUT
V-
DE-COUPLING
CAPS
IN1
VV-
V-
V- SUPPLY
FIGURE 27. SCHOTTKY PROTECTION CIRCUIT
Limiting the Output Current
No output short circuit current limit exists on this part. All
applications need to limit the output current to less than 50mA.
Adequate thermal heat sinking of the parts is also required.
PC Board Layout
The frequency response of this circuit depends greatly on the
care taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
• The use of low inductance components such as chip resistors
and chip capacitors is strongly recommended.
• Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid sharp
corners, use rounded corners when possible. Vias in the signal
lines add inductance at high frequency and should be avoided.
PCB traces greater than 1" begin to exhibit transmission line
characteristics with signal rise/fall times of 1ns or less. High
frequency performance may be degraded for traces greater
than one inch, unless strip lines are used.
• Maximize use of AC de-coupled PCB layers. All signal I/O lines
should be routed over continuous ground planes (i.e. no split
planes or PCB gaps under these lines). Avoid vias in the signal
I/O lines.
• Use proper value and location of termination resistors.
Termination resistors should be as close to the device as
possible.
• When testing use good quality connectors and cables,
matching cable types and keeping cable lengths to a
minimum.
• Minimum of 2 power supply de-coupling capacitors are
recommended (1000pF, 0.01µF) as close to the device as
possible. Avoid vias between the cap and the device because
vias add unwanted inductance. Larger caps can be farther
away. When vias are required in a layout, they should be routed
as far away from the device as possible.
• Match channel-channel analog I/O trace lengths and layout
symmetry. This will minimize propagation delay mismatches.
11
FN7459.2
July 3, 2012
ISL59420
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
May 22, 2012
FN7459.2
Updated datasheet to new Intersil template.
Changed max “Supply Current” on page 3 from 13mA to 15mA .
September 22, 2005
FN7459.1
1. Edits to the Absolute Max Ratings table included increasing Input Voltage specs to 0.5V from 0.3V, and
increasing Digital & Analog Max input current from 5mA to 50mA
2. Expanded PowerUp Considerations by adding the Shottky Diode application circuit and expanded description.
3. Added Part Marking to Ordering Information Table.
June 27, 2005
FN7459.0
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL59420
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/sear
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
FN7459.2
July 3, 2012
ISL59420
ISL59420
Package Outline Drawing
M10.118A (JEDEC MO-187-BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP)
Rev 0, 9/09
A
3.0 ± 0.1
0.25
10
DETAIL "X"
CAB
0.18 ± 0.05
SIDE VIEW 2
4.9 ± 0.15
3.0 ± 0.1
1.10 Max
B
PIN# 1 ID
1
2
0.95 BSC
0.5 BSC
TOP VIEW
Gauge
Plane
0.86 ± 0.09
H
0.25
C
3°±3°
SEATING PLANE
0.55 ± 0.15
0.10 ± 0.05
0.10 C
0.23 +0.07/ -0.08
0.08 C A B
DETAIL "X"
SIDE VIEW 1
5.80
4.40
3.00
NOTES:
0.50
0.30
1.
Dimensions are in millimeters.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Plastic or metal protrusions of 0.15mm max per side are not
included.
Plastic interlead protrusions of 0.25mm max per side are not
included.
4.
1.40
5.
Dimensions “D” and “E1” are measured at Datum Plane “H”.
TYPICAL RECOMMENDED LAND PATTERN
6.
This replaces existing drawing # MDP0043 MSOP10L.
13
FN7459.2
July 3, 2012
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