ISL59444 ® Data Sheet September 21, 2005 1GHz, 4 x 1 Multiplexing Amplifier with Synchronous Controls The ISL59444 is a single-output 4:1 MUX-amp. The MUX-amp has a fixed gain of 1 and a 1GHz bandwidth. The ISL59444 is ideal for professional video switching, HDTV, computer display routing, and other high performance applications. The device contains logic inputs for channel selection (S0, S1), latch control signals (LE1, LE2), and a three-state output control (HIZ) for individual selection of MUX amps that share a common video output line. All logic inputs have pull-downs to ground and may be left floating. Features • 1GHz (-3dB) Bandwidth (VOUT = 200mVP-P) • 220MHz (-3dB) Bandwidth (VOUT = 2VP-P) • Slew Rate (RL = 500Ω, VOUT = 4V) . . . . . . . . . . . .1515V/µs • Slew Rate (RL = 500Ω, VOUT = 5V) . . . . . . . . . . . . 1155V/µs • High Speed Three-State Output (HIZ) • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • HDTV/DTV Analog Inputs TABLE 1. TRUTH TABLE LE1/LE2 HIZ S1 S0 OUT 0 0 0 0 IN0 0 0 0 1 IN1 0 0 1 0 IN2 0 0 1 1 IN3 X 1 X X HiZ Ordering Information PART NUMBER PART TAPE & MARKING PACKAGE REEL • Video Projectors • Computer Monitors • Set-top Boxes • Security Video • Broadcast Video Equipment • RGB Video Distribution Systems • RF Switching and Routing Pinout ISL59444 (16 LD SO) TOP VIEW PKG. DWG. # IN0 1 16 V+ NIC 2 15 S0 MDP0027 IN1 3 14 S1 GND 4 ISL59444IB 59444IB 16 Ld SO† - MDP0027 ISL59444IB-T7 59444IB 16 Ld SO† 7” MDP0027 ISL59444IB-T13 59444IB 16 Ld SO† 13” ISL59444IBZ (Note) 59444IBZ 16 Ld SO† (Pb-free) - MDP0027 ISL59444IBZ-T13 (Note) 59444IBZ 16 Ld SO† (Pb-free) 7” MDP0027 ISL59444IBZ-T7 (Note) 59444IBZ 16 Ld SO† (Pb-free) 13” MDP0027 † SO16 (0.150”) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 13 HIZ IN2 5 12 OUT NIC 6 11 LE2 IN3 7 10 LE1 NIC 8 9 V- Functional Diagram EN0 EN1 S0 DECODE S1 Timing Diagram LE1 LE2 CHX CHY CHZ CHX CHZ LE1 LE2 DL Q C DL Q C DL Q C DL Q C EN2 DL Q C DL Q C EN3 DL Q C DL Q C HIZ S0, S1, HIZ FN7451.1 IN0 IN1 OUT IN2 IN3 100kΩ 100kΩ OUT CHX CHY 1 CHX CHZ CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL59444 Absolute Maximum Ratings (TA = 25°C) Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +125°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs Digital & Analog Input Current (Note 1) . . . . . . . . . . . . . . . . . . 50mA Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7). . . . . .3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications V+ = +5V, V- = -5V, GND = 0V, TA = 25°C, RL = 500Ω to GND, VHIZ = 0.8V, Unless Otherwise Specified PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT No load, VHIZ = 0.8V 14.5 18 20 mA No load, VHIZ = 2.0V 12.5 16 18 mA GENERAL IS Supply Current (VOUT = 0V) VOUT Positive and Negative Output Swing VIN = ±3.5V, RL = 500Ω ±3.2 ±3.44 IOUT Output Current RL = 10Ω to GND ±80 ±120 ±180 mA VOS Output Offset Voltage -2 9 20 mV Ib Input Bias Current VIN = 0V -5 -2.5 -1 µA Rout Output Resistance HIZ = logic high, (DC), AV = 1 1.4 MΩ HIZ = logic low, (DC), AV = 1 0.2 Ω 10 MΩ RIN Input Resistance VIN = ±3.5V ACL or AV Voltage Gain VIN = ±1.5V, RL = 500Ω ITRI Output Current in Three-state VOUT = 0V V 0.999 1.001 1.003 V/V -35 6 +35 µA LOGIC VH Input High Voltage (Logic Inputs) VL Input Low Voltage (Logic Inputs) IIH Input High Current (Logic Inputs) IIL tLE 2 V 0.8 V 50 150 µA Input Low Current (Logic Inputs) -10 5 µA LE1, LE2 Minimum Pulse Width - - ns 4 AC GENERAL -3dB BW 0.1dB BW -3dB Bandwidth 0.1dB Bandwidth VOUT = 200mVP-P, CL = 1.6pF 1.0 GHz VOUT = 2VP-P, CL = 23.6pF, RS = 25Ω 230 MHz VOUT = 200mVP-P, CL = 1.6pF 80 MHz VOUT = 2VP-P, CL = 23.6pF, RS = 25Ω 50 MHz dG Differential Gain Error NTSC-7, RL = 150 0.01 % dP Differential Phase Error NTSC-7, RL = 150 0.02 ° 2 FN7451.1 September 21, 2005 ISL59444 Electrical Specifications V+ = +5V, V- = -5V, GND = 0V, TA = 25°C, RL = 500Ω to GND, VHIZ = 0.8V, Unless Otherwise Specified (Continued) PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT +SR Slew Rate 25% to 75%, VOUT = 5V, RL = 500Ω, CL = 23.6pF, RS = 25Ω 1515 V/µs -SR Slew Rate 25% to 75%, VOUT = 5V, RL = 500Ω, CL = 23.6pF, RS = 25Ω 1155 V/µs PSRR Power Supply Rejection Ratio DC, PSRR V+ and V- combined V± = ±4.5V to ±5.5V -57 dB ISO Channel Isolation f = 10MHz, Ch-Ch X-Talk and Off Isolation, CL = 1.6pF 75 dB Channel-to-Channel Switching Glitch VIN = 0V, CL = 23.6pF, RS = 25Ω 38 mVP-P HIZ Switching Glitch VIN = 0V, CL = 23.6pF, RS = 25Ω 175 mVP-P tSW-L-H Channel Switching Time Low to High 1.2V logic threshold to 10% movement of analog output 32 ns tSW-H-L Channel Switching Time High to Low 1.2V logic threshold to 10% movement of analog output 29 ns VOUT = 200mVP-P, CL = 1.6pF 0.68 ns VOUT = 2VP-P, CL = 23.6pF, RS = 25Ω 1.4 ns -50 SWITCHING CHARACTERISTICS VGLITCH TRANSIENT RESPONSE tr, tf Rise & Fall Time, 10% to 90% tS 0.1% Settling Time VOUT = 2VP-P, CL = 23.6pF, RS = 25Ω 6.8 ns tPLH Propagation Delay - Low to High, 10% to 10% VOUT = 200mVP-P, CL = 1.6pF 0.5 ns VOUT = 2VP-P, CL = 23.6pF, RS = 25Ω 0.85 ns Propagation Delay- High to Low, 10% to 10% VOUT = 200mVP-P, CL = 1.6pF 0.54 ns VOUT = 2VP-P, CL = 23.6pF, RS = 25Ω 0.88 ns Overshoot VOUT = 200mVP-P, CL = 1.6pF 8.3 % VOUT = 2VP-P, CL = 23.6pF, RS = 25Ω 15.7 % tPHL OS 3 FN7451.1 September 21, 2005 ISL59444 Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified. 5 5 4 VOUT = 200mVP-P 4 3 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 3 CL = 9.7pF 2 CL = 7.2pF 1 0 -1 CL = 5.5pF -2 CL = 1.6pF -3 -4 VOUT = 200mVP-P CL = 1.6pF CL INCLUDES 1.6pF BOARD CAPACITANCE -5 0.001 2 RL = 500Ω 1 RL = 1kΩ 0 -1 -2 RL = 150Ω -3 RL = 75Ω -4 0.01 -5 0.001 1 1.5 0.1 0.01 FIGURE 1. SMALL SIGNAL GAIN vs FREQUENCY vs CL FIGURE 2. SMALL SIGNAL GAIN vs FREQUENCY vs RL 5 5 VOUT = 2VP-P RS = 25Ω 4 3 2 1 CL = 11.6pF 0 -1 CL = 16.6pF -2 CL = 23.6pF NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 4 3 VOUT = 2VP-P CL = 23.6pF RS = 25Ω 2 1 0 -1 -2 RL = 150Ω -3 -3 -4 CL INCLUDES 1.6pF BOARD CAPACITANCE -5 0.001 CL = 28.6pF 0.01 -5 0.001 1 1.5 0.1 0.01 1 1.5 0.1 FIGURE 4. LARGE SIGNAL GAIN vs FREQUENCY vs RL 0.5 0.5 CL = 9.7pF VOUT = 200mVP-P 0.4 CL = 7.2pF 0.2 NORMALIZED GAIN (dB) 0.3 NORMALIZED GAIN (dB) RL = 1kΩ FREQUENCY (MHz) FIGURE 3. LARGE SIGNAL GAIN vs FREQUENCY vs CL CL = 5.5pF 0.1 0 -0.1 -0.2 -0.3 -0.4 RL = 75Ω RL = 500Ω -4 FREQUENCY (MHz) 0.4 1 1.5 0.1 FREQUENCY (MHz) FREQUENCY (GHz) 0.3 VOUT = 200mVP-P CL = 1.6pF 0.2 0.1 0 -0.1 RL = 1kΩ -0.2 RL = 150Ω RL = 500Ω -0.3 CL = 1.6pF CL INCLUDES 1.6pF BOARD CAPACITANCE -0.5 0.001 0.01 0.1 -0.4 1 1.5 FREQUENCY (MHz) FIGURE 5. SMALL SIGNAL 0.1dB GAIN vs FREQUENCY vs CL 4 -0.5 0.001 RL = 75Ω 0.01 0.1 1 1.5 FREQUENCY (MHz) FIGURE 6. SMALL SIGNAL 0.1dB GAIN vs FREQUENCY vs RL FN7451.1 September 21, 2005 ISL59444 Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified. 5 0.1 4 NORMALIZED GAIN (dB) 0 CL = 11.6pF -0.1 -0.2 -0.3 CL = 16.6pF -0.4 -0.5 CL = 23.6pF VOUT = 2VP-P RS = 25Ω NORMALIZED GAIN (dB) 0.2 VOUT = 2VP-P CL = 23.6pF RS = 25Ω RL = 500Ω 2 RL = 150Ω RL = 1kΩ 1 0 RL = 75Ω -1 -2 -3 -0.6 -0.7 3 (Continued) CL = 28.6pF CL INCLUDES 1.6pF BOARD CAPACITANCE -0.8 0.001 0.01 -4 -5 0.001 1 1.5 0.1 0.01 1 1.5 0.1 FREQUENCY (MHz) FREQUENCY (MHz) FIGURE 7. LARGE SIGNAL 0.1dB GAIN vs FREQUENCY vs CL FIGURE 8. LARGE SIGNAL 0.1dB GAIN vs FREQUENCY vs RL -10 20 10 0 VIN = 200mVP-P CL = 23.6pF RS = 25Ω -30 -40 -50 -20 (dB) PSRR (dB) -10 -30 -60 CROSSTALK -70 -40 -80 -50 PSRR (V+) -90 -60 PSRR (V-) -70 -80 0.3 VIN = 1VP-P CL = 23.6pF RS = 25Ω -20 1 10 OFF ISOLATION -100 100 1000 -110 0.001 0.01 0.1 1 3 6 10 100 500 FREQUENCY (MHz) FREQUENCY (MHz) FIGURE 9. PSRR CHANNELS FIGURE 10. CROSSTALK AND OFF ISOLATION 100 60 INPUT VOLTAGE NOISE (nV/√Hz) OUTPUT RESISTANCE (Ω) VOUT = 100mVP-P 10 1 RF = 500Ω 50 40 30 20 10 0.1 0.1 1 10 100 FREQUENCY (MHz) FIGURE 11. ROUT vs FREQUENCY 5 1000 0 0.1 1 10 100 FREQUENCY (kHz) FIGURE 12. INPUT NOISE vs FREQUENCY FN7451.1 September 21, 2005 ISL59444 Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified. S0, S1 1V/DIV 1V/DIV S0, S1 0 0 500mV/DIV 20mV/DIV 0 VOUT VOUT 0 20ns/DIV 20ns/DIV FIGURE 13. CHANNEL TO CHANNEL SWITCHING GLITCH VIN = 0V, RS = 25, CL = 23.6pF FIGURE 14. CHANNEL TO CHANNEL TRANSIENT RESPONSE VIN = 1V, RS = 25, CL = 23.6pF HIZ 1V/DIV 1V/DIV HIZ 0 500mV/DIV 100mV/DIV 0 0 VOUT VOUT 0 20ns/DIV 20ns/DIV FIGURE 15. HIZ SWITCHING GLITCH VIN = 0V, RS = 25, CL = 23.6pF FIGURE 16. HIZ TRANSIENT RESPONSE VIN = 1V, RS = 25, CL = 23.6pF 160 2.4 CL = 1.6pF RL = 500Ω 120 80 2 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (mV) (Continued) 40 0 -40 -80 1.6 1.2 0.8 0.4 0 -0.4 -120 -160 -0.8 TIME (4ns/DIV) FIGURE 17. SMALL SIGNAL TRANSIENT RESPONSE 6 CL = 23.6pF RS = 25Ω RL = 500Ω TIME (4ns/DIV) FIGURE 18. LARGE SIGNAL TRANSIENT RESPONSE FN7451.1 September 21, 2005 ISL59444 Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified. 1 1.250W POWER DISSIPATION (W) 1.2 θ 1 SO JA 0.8 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.9 POWER DISSIPATION (W) 1.4 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 16 (0 .1 =8 50 0° ” C /W ) 0.6 0.4 0.2 (Continued) 909mW 0.8 θ 0.7 SO 16 JA = 0.6 0.5 11 0° (0 . 15 0” ) C /W 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125 0 150 AMBIENT TEMPERATURE (°C) 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Pin Descriptions PIN NUMBER PIN NAME EQUIVALENT CIRCUIT 1 IN0 Circuit 1 2, 6, 8 NIC 3 IN1 Circuit 1 Input for channel 1 4 GND Circuit 4 Ground pin 5 IN2 Circuit 1 Input for channel 2 7 IN3 Circuit 1 Input for channel 3 9 V- Circuit 4 Negative Power Supply 10 LE1 Circuit 2 Synchronized channel switching: When LE1 is low, the master control latch loads the next switching address. The Mux Amp is configured for this address when LE2 goes low. Synchronized operation results when LE2 is the inverse of LE1. Channel selection is asynchronous (changes with any control signal change) if both LE1 and LE2 are both low. 11 LE2 Circuit 2 Synchronized channel switching: When LE2 is low, the newly selected channel, stored in the master latch via LE1 is selected. Synchronized operation results when LE2 is the inverse of LE1. Channel selection is asynchronous (changes with any control signal change) if both LE1 and LE2 are both low. 12 OUT Circuit 3 Output 13 HIZ Circuit 2 Output disable (active high); there are internal pull-down resistors, so the device will be active with no connection; "HI" puts the output in high impedance state. 14 S1 Circuit 2 Channel selection pin MSB (binary logic code) 15 S0 Circuit 2 Channel selection pin LSB (binary logic code) 16 V+ Circuit 4 Positive power supply DESCRIPTION Input for channel 0 Not Internally Connected; it is recommended this pin be tied to ground to minimize crosstalk. 7 FN7451.1 September 21, 2005 ISL59444 Pin Descriptions (Continued) PIN NUMBER EQUIVALENT CIRCUIT PIN NAME DESCRIPTION V+ V+ 21k IN 1.2V LOGICPIN + - GND. 33k V- V- CIRCUIT 1 CIRCUIT 2 V+ V+ CAPACITIVELY COUPLED ESD CLAMP GND OUT VV- CIRCUIT 4 CIRCUIT 3 AC Test Circuits ISL59444 ISL59444 VIN VIN CL 2pF 50Ω or 75Ω 50Ω or 75Ω RL 500Ω FIGURE 21A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD ISL59444 RS VIN 50Ω or 75Ω CL 2pF 50Ω or 75Ω TEST EQUIPMENT RS CL 2pF 475Ω 50Ω or 75Ω 50Ω or 75Ω FIGURE 21B. TEST CIRCUIT FOR MEASURING WITH A 50Ω OR 75Ω INPUT TERMINATED EQUIPMENT TEST EQUIPMENT 50Ω or 75Ω FIGURE 21C. BACKLOADED TEST CIRCUIT FOR VIDEO CABLE APPLICATION. BANDWIDTH AND LINEARITY FOR RL LESS THAN 500Ω WILL BE DEGRADED. Figure 21A illustrates the optimum output load for testing AC performance. Figure 21B illustrates the optimum output load when connecting to input terminated equipment. Figure 21C illustrates back loaded test circuit for video cable. 8 FN7451.1 September 21, 2005 ISL59444 Application Circuits *CL = CT + COUT VIN VOUT + COUT CT 1.6pF 50Ω 0pF RL = 500Ω *CL: TOTAL LOAD CAPACITANCE CT: TRACE CAPACITANCE COUT: OUTPUT CAPACITANCE FIGURE 22A. SMALL SIGNAL 200mVP-P APPLICATION CIRCUIT RS 25Ω VIN + 50Ω 1.6pF CT VOUT COUT 22pF RL = 500Ω CL = CT + COUT FIGURE 22B. LARGE SIGNAL 1VP-P APPLICATION CIRCUIT Application Information General The ISL59444 is a 4:1 mux that is ideal as a matrix element in high performance switchers and routers. The ISL59444 is optimized to drive a 2pF in parallel with a 500Ω load. The capacitance can be split between the PCB capacitance an and external load capacitance. Their low input capacitance and high input resistance provide excellent 50Ω or 75Ω terminations. Capacitance at the Output The output amplifier is optimized for capacitance to ground (CL) directly on the output pin. Increased capacitance causes higher peaking with an increase in bandwidth. The optimum range for most applications is ~1.0pF to ~6pF. The optimum value can be achieved through a combination of PC board trace capacitance (CT) and an external capacitor (COUT). A good method to maintain control over the output pin capacitance is to minimize the trace length (CT) to the next component, and include a discrete surface mount capacitor (COUT) directly at the output pin. For large signal applications where overshoot is important the circuit in Figure 22B should be used. The series resistor (RS) and capacitor (CL) form a low pass network that limits system bandwidth and reduces overshoot. The component values shown result in a typical pulse response shown in Figure 18. 9 Ground Connections For the best isolation and crosstalk rejection, the GND pin and NIC pins must connect to the GND plane. The NIC pins are placed on both sides of the input pins. These pins are not internally connected to the die. It is recommended this pin be tied to ground to minimize crosstalk. Control Signals S0, S1, HIZ - These pins are, TTL/CMOS compatible control inputs. The S0, S1 pins select which one of the inputs connect to the output. The HIZ pin is used to three-state the output amplifiers. For control signal rise and fall times less than 10ns the use of termination resistors close to the part will minimize transients coupled to the output. HIZ State An internal pull-down resistor connected to the HIZ pin ensures the device will be active with no connection to the HIZ pin. The HIZ state is established within approximately 30ns by placing a logic high (>2V) on the HIZ pin. If the HIZ state is selected, the output is a high impedance 1.4MΩ. Use this state to control the logic when more than one mux shares a common output. In the HIZ state the output is three-stated, and maintains its high Z even in the presence of high slew rates. The supply current during this state is basically the same as the active state. FN7451.1 September 21, 2005 ISL59444 Latch State PC Board Layout The latched control signals allow for synchronized channel switching. When LE1 is low the master control latch loads the next switching address (S0, S1), while the closed (assuming LE2 is the inverse of LE1) slave control latch maintains the current state. LE2 switching low closes the master latch (with previous assumption), loads the now open slave latch, and switches the crosspoint to the newly selected channel. Channel selection is asynchronous (changes with any control signal change) if both LE1 and LE2 are low. The frequency response of this circuit depends greatly on the care taken in designing the PC board. The following are recommendations to achieve optimum high frequency performance from your PC board. • The use of low inductance components such as chip resistors and chip capacitors is strongly recommended. • Minimize signal trace lengths. Trace inductance and capacitance can easily limit circuit performance. Avoid sharp corners, use rounded corners when possible. Vias in the signal lines add inductance at high frequency and should be avoided. PCB traces greater than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. High frequency performance may be degraded for traces greater than one inch, unless strip lines are used. Power-Up Considerations The ESD protection circuits use internal diodes from all pins the V+ and V- supplies. In addition, a dv/dt triggered clamp is connected between the V+ and V- pins, as shown in the Equivalent Circuits 1 through 4 section of the Pin Description table. The dv/dt triggered clamp imposes a maximum supply turn-on slew rate of 1V/µs. Damaging currents can flow for power supply rates-of-rise in excess of 1V/µs, such as during hot plugging. Under these conditions, additional methods should be employed to ensure the rate of rise is not exceeded. • Match channel-channel analog I/O trace lengths and layout symmetry. This will minimize propagation delay mismatches. • Maximize use of AC de-coupled PCB layers. All signal I/O lines should be routed over continuous ground planes (i.e. no split planes or PCB gaps under these lines). Avoid vias in the signal I/O lines. Consideration must be given to the order in which power is applied to the V+ and V- pins, as well as analog and logic input pins. Schottky diodes (Motorola MBR0550T or equivalent) connected from V+ to ground and V- to ground (Figure 23) will shunt damaging currents away from the internal V+ and V- ESD diodes in the event that the V+ supply is applied to the device before the V- supply. • Use proper value and location of termination resistors. Termination resistors should be as close to the device as possible. • When testing use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. If positive voltages are applied to the logic or analog video input pins before V+ is applied, current will flow through the internal ESD diodes to the V+ pin. The presence of large decoupling capacitors and the loading effect of other circuits connected to V+, can result in damaging currents through the ESD diodes and other active circuits within the device. Therefore, adequate current limiting on the digital and analog inputs is needed to prevent damage during the time the voltages on these inputs are more positive than V+. • Minimum of 2 power supply de-coupling capacitors are recommended (1000pF, 0.01µF) as close to the devices as possible. Avoid vias between the cap and the device because vias add unwanted inductance. Larger caps can be farther away. When vias are required in a layout, they should be routed as far away from the device as possible. • The NIC pins are placed on both sides of the input pins. These pins are not internally connected to the die. It is recommended these pins be tied to ground to minimize crosstalk. Limiting the Output Current No output short circuit current limit exists on these parts. All applications need to limit the output current to less than 50mA. Adequate thermal heat sinking of the parts is also required. V+ SUPPLY SCHOTTKY PROTECTION LOGIC V+ LOGIC CONTROL S0 POWER GND GND SIGNAL IN0 EXTERNAL CIRCUITS V+ V- V+ V+ V+ OUT V- DE-COUPLING CAPS IN1 VV- V- V- SUPPLY FIGURE 23. SCHOTTKY PROTECTION CIRCUIT 10 FN7451.1 September 21, 2005 ISL59444 SO Package Outline Drawing NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at <http://www.intersil.com/design/packages/index.asp> All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN7451.1 September 21, 2005