DATASHEET

N OT R E
CO
RECOM MMENDED FO
MENDE
R NEW
D REPL
DESIGN
A C E ME
S
ISL9767
NT PAR
1A or IS
TS
L97672
B
ISL97673
Features
The ISL97673 is a 6-Channel 45V dual dimming capable
LED driver that can be used with either SMBus/I2C or
PWM signal for dimming control. The ISL97673 drives 6
channels of LED to support 78 LEDs from 4.5V to 26V or
48 LEDs from a boost supply of 2.7V to 26V and a
separate 5V bias on the ISL97673 VIN pin
• 6 Channels
The ISL97673 compensates for non-uniformity of the
forward voltage drops in the LED strings with its 6 voltage
controlled-current source channels. Its headroom control
monitors the highest LED forward voltage string for output
regulation, to minimize the voltage headroom and power
loss in a typical multi-string operation.
- PWM/DPST Dimming, I2C 8-bit with equal phase
shift, and 0.007% Direct PWM dimming at 200Hz
• Optional Master Fault Protection
• 4.5V to 26.5V Input
• 45V Output Max
• Up to 40mA LED Current per channel
• Extensive Dimming Control
• PWM Dimming Linearity 0.4%~100% <30kHz
• 600kHz/1.2MHz selectable switching frequency
• Dynamic Headroom Control
The ISL97673 features optional channel phase shift
control to minimize the input, output ripple
characteristics and load transients as well as spreading
the light output to help reduce the video and audio
interference from the backlight driver operation. The
phase shift can be programmed with equal phase angle
or adjustable in 7-bit resolution.
• Protections with Flag Indication
- String Open/Short Circuit, VOUT Short Circuit,
Overvoltage and Over-Temperature Protections
- Optional Master Fault Protection
• Current Matching ±0.7%
• 20 Ld 4mmx3mm QFN Package
The ISL97673 has a full range of dimming capabilities
that include SMBus/I2C controlled PWM dimming or DC
dimming. Another key feature of the ISL97673 is that it
allows very linear PWM dimming from 0.4% to 100% of
up to 30kHz. Current matching of 0.4% to 100%
dimming achieves ±1% tolerance from 100Hz to 5kHz
dimming and ±3% tolerance from 5kHz to 30kHz
dimming.
Applications
• Notebook Displays WLED or RGB LED Backlighting
• LCD Monitor LED Backlighting
• Automotive Displays LED Backlighting
Typical Application Circuit
VOUT = 45V*, 40mA PER CHANNEL
VIN = 4.5~26.5V
ISL97673
1 FAULT
2 VIN
4 VDC
18 COMP
LX 20
OVP 16
PGND 19
7 SMBCLK(SCL)/SEL2
6 SMBDAT(SDA)/ CH0 10
_FLAG
CH1 11
3 EN/PWM
CH2 12
17 RSET
CH3 13
8 FPWM
CH4 14
5 SEL1
CH5 15
AGND
9
*VIN > 12V
FIGURE 1. ISL97673 TYPICAL APPLICATION DIAGRAM
October 5, 2012
FN7633.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010, 2012. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL97673
6-Channel SMBus or PWM Dimming LED Driver
with Phase Shift Control
ISL97673
Block Diagram
40mA per string
45V*, 25mA
78 (6x13) LEDs
VIN = 4.5V~26V
10uH/3A
VIN
VDC
FAULT
REG
FPWM
O/P Short
Bias
Σ=0
Dimming
Controller
Imax
OVP
OVP
Fault/Status
Register
fsw
OSC &
RAMP
Comp
4.7uF/50V
LX
Boost SW
FET
Drivers
Logic
ILIMIT
PGND
pe
Open Ckt, Short Ckt
Detects
Fault/Status Control
COMP
GM
AMP
VSET
SMBDAT(SDA)
SEL1
SEL2
EN/PWM
SMBus/
I2C
Control
DAC0
PWM0
Controls
0
PWM0
DAC1
PWM1
Controls
Temp
Sensor
Fault/Status
Register
DAC1
Phase Shift
Controller
1
+
-
PWM1
*V
12V
IN >
* Vin
> 6V
Dimming Mode
Selection
Ext PWM
Control Ckt
CH5
+
-
DAC0
REF_OVP
REF_VSC
GND
SMBCLK(SCL)
REF
GEN
+
-
RSET
CH0
CH1
Highest VF
String Detect
DAC5
D AC5
PWM5
Controls
+
-
5
PWM5
ISL97673
FIGURE 2. ISL97673 BLOCK DIAGRAM
2
FN7633.2
October 5, 2012
ISL97673
Pin Configuration
Evaluation Board
NOTES:
1. Add “-T” or “-TK” suffix for tape and reel. Please refer to TB347 for
details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3
termination finish, which is RoHS compliant and compatible
with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements
of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device
information page for ISL97673. For more information on
MSL please see techbrief TB363.
Pin Descriptions
PIN
NAME
RSET
ISL97673IRZ-EVAL
L20.3x4
20
19
18
17
FAULT
1
16 OVP
VIN
2
15 CH5
EN/PWM
3
14 CH4
VDC
4
13 CH3
SEL1
5
12 CH2
SMBDAT(SDA) 6
/_FLAG
11 CH1
7
8
9
10
CH0
20 Ld 4x3 QFN
COMP
7673
AGND
ISL97673IRZ
ISL97673
(20 LD QFN)
TOP VIEW
PKG.
DWG. #
PGND
PACKAGE
(Pb-free)
FPWM
PART
MARKING
LX
PART NUMBER
(Notes 1, 2)
SMBCLK(SCL)/SEL2
Ordering Information
(I = Input, O = Output, S = Supply)
PIN
NUMBER
TYPE
FAULT
1
O
Fault disconnect switch
VIN
2
S
Input voltage for the device and LED power
EN/PWM
3
I
Dual Functions: Enable pin and PWM brightness control pin or DPST control
input. The device needs 4ms for initial power-up Enable, then this pin can
be applied with a PWM signal with off time no longer than 28ms.
VDC
4
S
De-couple capacitor for internally generated supply rail.
Mode select pin 1
DESCRIPTION
SEL1
5
I
SMBDAT(SDA)/_FLAG
6
I/O
When SEL1 is high, this pin is configured as the SMBus/I2C serial data
input/output.
When SEL1 is low or floating, this pin is configured as the fault flag output
and will be pulled low when a fault condition occurs. An external pull-up is
required.
SMBCLK(SCL)/SEL2
7
I
When SEL1 is high, this pin is configured as the SMBus/I2C serial clock
input.
When SEL1 is low or floating, this pins is configured as mode select pin 2,
and operates in conjunction with SEL1 to determine the operating mode.
See Table 1 for details.
FPWM
8
I
PWM Dimming Frequency Set Pin with RFPWM
AGND
9
S
Analog Ground for precision circuits
CH0, CH1, CH2, CH3, CH4,
CH5
10, 11, 12,
13, 14, 15
I
Input 0, Input 1, Input 2, Input 3, Input 4, Input 5 to current source, FB,
and monitoring
OVP
16
I
Overvoltage protection input
RSET
17
I
Resistor connection for setting LED current, (see Equation 2 for calculating
the ILEDpeak)
COMP
18
O
Boost compensation pin
PGND
19
S
Power ground
LX
20
O
Input to boost switch
3
FN7633.2
October 5, 2012
ISL97673
Table of Contents
Typical Application Circuit .............................. 1
Block Diagram ................................................ 2
Pin Descriptions ............................................. 3
Absolute Maximum Ratings ............................ 5
Thermal Information ...................................... 5
Operating Conditions ...................................... 5
Electrical Specifications ...............................5
Typical Performance Curves ........................... 8
Theory of Operation........................................ 11
PWM Boost Converter .....................................11
Enable and PWM ............................................11
OVP and VOUT Requirement .............................11
Current Matching and Current Accuracy ............11
Dynamic Headroom Control .............................11
Operating Modes ............................................11
Dimming Controls ..........................................12
Maximum DC Current Setting .................. 12
DC Current Adjustment .......................... 12
PWM Control ......................................... 12
PWM Dimming Frequency Adjustment ...............13
Phase Shift Control ................................ 13
Switching Frequency.......................................14
5V Low Dropout Regulator...............................14
In-rush Control and Soft-start..........................14
Fault Protection and Monitoring ........................14
Short Circuit Protection (SCP) ..........................14
Open Circuit Protection (OCP) ..........................15
4
Overvoltage Protection (OVP) .......................... 15
Undervoltage Lockout .................................... 15
Input Overcurrent Protection........................... 15
Over-Temperature Protection (OTP) ................. 15
Write Byte ........................................................ 18
Read Byte ........................................................ 18
Slave Device Address......................................... 18
SMBus/I2C Register Definitions ....................... 18
PWM Brightness Control Register (0x00)........... 20
Device Control Register (0x01)........................ 20
Fault/Status Register (0x02) ........................... 21
Si Revision Register (0x03) ............................. 21
DC Brightness Control Register (0x07) ............. 22
Configuration Register (0x08) ......................... 22
Output Channel Select and Fault Readout
Register (0x09) ........................................... 23
Phase Shift Control Register (0x0A) ................. 24
Components Selections ...................................24
Input Capacitor ............................................. 24
Inductor ....................................................... 24
Output Capacitors.......................................... 25
Output Ripple................................................ 25
Schottky Diode.............................................. 25
Applications ....................................................25
High Current Applications ............................... 25
Multiple Drivers Operation .............................. 26
Revision History ..............................................26
Products..........................................................26
Package Outline Drawing ................................ 27
FN7633.2
October 5, 2012
ISL97673
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
VIN, EN/PWM. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V
FAULT . . . . . . . . . . . . . . . . . . . . . VIN - 8.5V to VIN + 0.3V
VDC, COMP, RSET, FPWM, OVP . . . . . . . . . . . . -0.3V to 5.5V
SMBCLK(SCL), SMBDAT(SDA) . . . . . . . . . . . . -0.3V to 5.5V
CH0 - CH5, LX . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 45V
PGND, AGND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Above voltage ratings are all with respect to AGND pin
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . 3kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . 300V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . 1kV
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
20 Ld QFN Package (Notes 4, 5, 7) .
Thermal Characterization (Typical)
40
2.5
PSIJT (°C/W)
20 Ld QFN Package (Note 6) . . . . . . . . . . . .
1
Maximum Continuous Junction Temperature . . . . . . +125°C
Storage Temperature . . . . . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . -40°C to +85°C
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless
otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
6. PSIJT is the PSI junction-to-top thermal characterization parameter. If the package top temperature can be measured with this
rating then the die junction temperature can be estimated more accurately than the θJC and θJC thermal resistance ratings
7. Refer to JESD51-7 high effective thermal conductivity board layout for proper via and plane designs.
Electrical Specifications
PARAMETER
All specifications below are tested at TA = +25°C; VIN = 12V, EN/PWM = 5V, RSET = 20.1kΩ,
unless otherwise noted. Boldface limits apply over the operating temperature range,
-40°C to +85°C.
DESCRIPTION
MAX
(Note 8)
UNIT
26.5
V
10
µA
4.5V < VIN ≤ 26V,
FSW = 600kHz
45
V
8.55V < VIN ≤ 26V,
FSW = 1.2MHz
45
V
4.5V < VIN ≤ 8.55V,
FSW = 1.2MHz
VIN/0.19
V
3.3
V
CONDITION
MIN
(Note 8)
TYP
GENERAL
VIN (Note 9)
IVIN_STBY
VOUT
Backlight Supply Voltage
≤11 LEDs per channel
(3.2V/20mA type)
4.5
VIN Shutdown Current
Output Voltage
VUVLO
Undervoltage Lock-out Threshold
VUVLO_HYS
Undervoltage Lock-out Hysteresis
2.6
275
mV
REGULATOR
VDC
LDO Output Voltage
VIN > 6V
Standby Current
EN/PWMI = 0V
IVDC
Active Current
EN/PWMI = 5V
VLDO
VDC LDO Droop Voltage
VIN > 5.5V, 20mA
ENLow
Guaranteed Range for EN Input Low Voltage
ENHi
Guaranteed Range for EN Input High Voltage
IVDC_STBY
tENLow
EN/PWMI Low Time Before Shut-down
5
4.55
4.8
5
V
5
µA
5
20
1.8
mA
200
mV
0.5
V
V
30.5
ms
FN7633.2
October 5, 2012
ISL97673
Electrical Specifications
PARAMETER
All specifications below are tested at TA = +25°C; VIN = 12V, EN/PWM = 5V, RSET = 20.1kΩ,
unless otherwise noted. Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
DESCRIPTION
CONDITION
MIN
(Note 8)
TYP
MAX
(Note 8)
UNIT
1.5
2.0
2.7
A
235
300
mΩ
BOOST
SWILimit
Boost FET Current Limit
rDS(ON)
Internal Boost Switch ON-resistance
TA = +25°C
Soft-start
100% LED Duty Cycle
Peak Efficiency
SS
Eff_peak
ΔIOUT/ΔVIN
DMAX
DMIN
7
ms
VIN = 12V, 72 LEDs, 20mA
each, L = 10µH with DCR
101mΩ, TA = +25°C
92.9
%
VIN = 12V, 60 LEDs, 20mA
each, L = 10µH with DCR
101mΩ, TA = +25°C
90.8
%
0.1
%
Line Regulation
Boost Maximum Duty Cycle
Boost Minimum Duty Cycle
FSW = 1, 600kHz
90
FSW = 0, 1.2MHz
81
%
FSW = 1, 600kHz
9.5
FSW = 0, 1.2MHz
17
%
fOSC_hi
Lx Frequency High
FSW = 1, 600kHz
475
600
640
kHz
fOSC_lo
Lx Frequency Low
FSW = 0, 1.2MHz
0.97
1.14
1.31
MHz
Lx Leakage Current
LX = 45V, EN = 0
10
µA
ILX_leakage
FAULT DETECTION
VSC
Short Circuit Threshold Accuracy
Reg0x08, SC[1:0] = 01
3.15
3.6
4.3
V
Reg0x08, SC[1:0] = 10
4.2
4.8
5.4
V
Reg0x08, SC[1:0] = 11
5.2
5.85
6.6
V
Temp_shtdwn Temperature Shutdown Threshold
Temp_Hyst
VOVPlo
OVPfault
Temperature Shutdown Hysteresis
Overvoltage Limit on OVP Pin
150
°C
23
°C
1.19
OVP Short Detection Fault Level
1.25
400
V
mV
CURRENT SOURCES
IMATCH
IACC
Vheadroom
VRSET
ILEDmax
DC Channel-to-Channel Current Matching
±0.7
RSET = 20.1kΩ,
Reg0x00 = 0xFF
(IOUT = 20mA)
Current Accuracy
-1.5
Dominant Channel Current Source Headroom at
FBx Pin
ILED = 20mA
TA = +25°C
Voltage at RSET Pin
RSET = 20.1kΩ
Maximum LED Current per Channel
VIN = 12V, VOUT = 45V,
Fsw=1.2MHz, TA = +25°C
±1.0
%
+1.5
%
500
1.2
1.22
mV
1.24
40
mV
mA
PWM GENERATOR
VIL
Guaranteed Range for PWMI Input Low Voltage
VIH
Guaranteed Range for PWMI Input High Voltage
PWMI Input Frequency Range
FPWM
PWMACC
PWM Input Accuracy
6
0.8
V
1.5
VDD
V
200
30,000
Hz
8
bits
FN7633.2
October 5, 2012
ISL97673
Electrical Specifications
PARAMETER
All specifications below are tested at TA = +25°C; VIN = 12V, EN/PWM = 5V, RSET = 20.1kΩ,
unless otherwise noted. Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
DESCRIPTION
CONDITION
FPWM
PWM Dimming Frequency Range
RFPWM = 660kΩ
tDIRECTPWM
Direct PWM Minimum On Time
Direct PWM Mode
IFAULT
Fault Pull-down Current
VIN = 12V
VFAULT
Fault Clamp Voltage with Respect to VIN
VIN = 12V, VIN - VFAULT
MIN
(Note 8)
TYP
MAX
(Note 8)
UNIT
90
100
110
Hz
350
ns
250
FAULT PIN
LXStart_thres
IlxStart-up
Lx Start-up Threshold
Lx Start-up Current
12
21
30
µA
6
7
8.3
V
1.3
1.4
1.5
V
1
3.5
5
mA
0.8
V
VDD
V
0.17
V
10
µA
SMBus/I2C INTERFACE LOGIC LEVEL
VIL
Guaranteed Range for Data, Clock Input Low
Voltage
VIH
Guaranteed Range for Data, Clock Input High
Voltage
VOL
SMBus/I2C Output Data Line Logic Low Voltage
IPULLUP = 4mA
Input Leakage On SMBData/SMBClk
Measured at 4.8V
ILEAK
1.5
-10
SMBus/I2C TIMING SPECIFICATIONS (Note 10)
tEN-SMB/I2C
Minimum Time Between EN high and SMBus/I2C
Enabled
1µF capacitor on VDC
2
0.15
ms
PWS
Pulse Width Suppression on SMBCLK/SMBDAT
0.45
µs
fSMB
SMBus Clock Frequency
tBUF
Bus Free Time Between Stop and Start Condition
1.3
400
kHz
µs
tHD:STA
Hold Time After (Repeated) START Condition.
After this Period, the First Clock is Generated
0.6
µs
tSU:STA
Repeated Start Condition Setup Time
0.6
µs
tSU:STO
Stop Condition Setup Time
0.6
µs
tHD:DAT
Data Hold Time
300
ns
tSU:DAT
Data Setup Time
100
ns
tLOW
Clock Low Period
1.3
µs
tHIGH
Clock High Period
0.6
µs
tF
Clock/data Fall Time
300
ns
tR
Clock/data Rise Time
300
ns
NOTES:
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
9. Independent from the numbers of LEDs, at minimum VIN of 4.5V, maximum VOUT is limited to 35V. And at maximum VIN of 26.5V,
minimum VOUT is limited 28V.
10. Limits established by characterization and are not production tested.
7
FN7633.2
October 5, 2012
ISL97673
100
100
90
90
80
80
70
24VIN
12VIN
60
EFFICIENCY (%)
EFFICIENCY (%)
Typical Performance Curves
5VIN
50
40
30
20
10
0
6P10S_30mA/CHANNEL
70
24VIN
12VIN
60
5VIN
50
40
30
20
10
0
5
10
15
20
0
25
0
5
10
ILED(mA)
FIGURE 3. EFFICIENCY vs up to 20mA LED CURRENT
(100% LED DUTY CYCLE) vs VIN
15
20
ILED(mA)
25
30
35
FIGURE 4. EFFICIENCY vs up to 30mA LED CURRENT
(100% LED DUTY CYCLE) vs VIN
100
100
80
70
580k
60
EFFICIENCY (%)
EFFICIENCY (%)
90
1.2MHz
50
40
30
20
80
60
1.2MHz
580k
40
20
10
0
0
5
10
15
20
25
0
0
30
5
10
15
FIGURE 5. EFFICIENCY vs VIN vs SWITCHING
FREQUENCY AT 20mA (100% LED DUTY
CYCLE)
30
0.40
CURRENT MATCHING(%)
90
80
EFFICIENCY (%)
25
FIGURE 6. EFFICIENCY vs VIN vs SWITCHING
FREQUENCY AT 30mA (100% LED DUTY
CYCLE)
100
70 +25°C
60
+85°C
-40°C
0°C
50
40
30
20
10
0
20
VIN
VIN
0
5
10
15
20
25
30
VIN
FIGURE 7. EFFICIENCY vs VIN vs TEMPERATURE AT
20mA (100% LED DUTY CYCLE)
8
0.30
0.20
0.10
0.00
4.5 VIN
-0.10
12 VIN
-0.20
-0.30
-0.40
0
21 VIN
1
2
3
4
5
6
7
CHANNEL
FIGURE 8. CHANNEL-TO-CHANNEL CURRENT
MATCHING
FN7633.2
October 5, 2012
ISL97673
Typical Performance Curves
(Continued)
1.2
0.60
+25°C
0.8
VHEADROOM (V)
CURRENT
1.0
4.5 VIN
0.6
12 VIN
0.4
-40°C
0.55
0.50
0°C
0.45
0.2
0
0
1
2
3
DC
4
5
6
FIGURE 9. CURRENT LINEARITY vs LOW LEVEL PWM
DIMMING DUTY CYCLE vs VIN
0.40
0
5
10
15
VIN (V)
20
25
30
FIGURE 10. VHEADROOM vs VIN AT 20mA
FIGURE 11. VOUT RIPPLE VOLTAGE, VIN = 12V, 6P12S
AT 20mA/CHANNEL
FIGURE 12. IN-RUSH and LED CURRENT AT VIN = 6V
FOR 6P12S AT 20mA/CHANNEL
FIGURE 13. IN-RUSH AND LED CURRENT AT VIN = 12V
FOR 6P12S AT 20mA/CHANNEL
FIGURE 14. LINE REGULATION WITH VIN CHANGE
FROM 6V TO 26V, VIN = 12V, 6P12S AT
20mA/CHANNEL
9
FN7633.2
October 5, 2012
ISL97673
Typical Performance Curves
(Continued)
FIGURE 15. LINE REGULATION WITH VIN CHANGE
FROM 26V TO 6V FOR 6P12S AT
20mA/CHANNEL
FIGURE 17. LOAD REGULATION WITH ILED CHANGE
FROM 100% TO 0% PWM DIMMING,
VIN = 12V, 6P12S AT 20mA/CHANNEL
10
FIGURE 16. LOAD REGULATION WITH ILED CHANGE
FROM 0% TO 100% PWM DIMMING,
VIN = 12V, 6P12S AT 20mA/CHANNEL
FIGURE 18. ISL97671 SHUTS DOWN AND STOPS
SWITCHING ~ 30ms AFTER EN GOES LOW
FN7633.2
October 5, 2012
ISL97673
Theory of Operation
PWM Boost Converter
The current mode PWM boost converter produces the
minimal voltage needed to enable the LED stack with the
highest forward voltage drop to run at the programmed
current. The ISL97673 employs current mode control
boost architecture that has a fast current sense loop and
a slow voltage feedback loop. Such architecture achieves
a fast transient response that is essential for the
notebook backlight application where the power can be a
series of drained batteries or instantly change to an
AC/DC adapter without rendering a noticeable visual
nuisance. The number of LEDs that can be driven by
ISL97673 depend on the type of LED chosen in the
application. The ISL97673 are capable of boosting up to
45V and typically driving 13 LEDs in series for each of the
6 channels, enabling a total of 104 pieces of the
3.2V/20mA type of LEDs.
The LED peak current is set by translating the RSET
current to the output with a scaling factor of 410.5/RSET.
The source terminals of the current source MOSFETs are
designed to run at 500mV to optimize power loss versus
accuracy requirements. The sources of errors of the
channel-to-channel current matching come from the
op amps offset, internal layout, reference, and current
source resistors. These parameters are optimized for
current matching and absolute current accuracy.
However, the absolute accuracy is additionally
determined by the external RSET. A 1% tolerance resistor
is recommended.
Enable and PWM
The ISL97673 has EN/PWM pin that serves dual
purposes; it is used as an Enable signal and can be used
as a PWM input signal for dimming. If a PWM signal is
applied to this pin, the first pulse of minimum 4ms will be
used as an Enable signal. If there is no signal for longer
than 28ms, the device will enter shutdown.
OVP and VOUT Requirement
+
REF
RSET
+
PWM DIMMING
DC DIMMING
The Overvoltage Protection (OVP) pin has a function of
setting the overvoltage trip level as well as limiting the
VOUT regulation range.
The ISL97673 OVP threshold is set by RUPPER and
RLOWER as shown in Equation 1:
V OUT_OVP = 1.21V × ( R UPPER + R LOWER ) ⁄ R LOWER
+
-
(EQ. 1)
VOUT can only regulate between 64% and 100% of the
VOUT_OVP such that:
Allowable VOUT = 64% to 100% of VOUT_OVP
For example, if 10 LEDs are used with the worst case
VOUT of 35V. If R1 and R2 are chosen such that the OVP
level is set at 40V, then the VOUT is allowed to operate
between 25.6V and 40V. If the requirement is changed to
a 6 LEDs 21V VOUT application, then the OVP level must
be reduced and users should follow VOUT = (64%
~100%) OVP requirement. Otherwise, the headroom
control will be disturbed such that the channel voltage
can be much higher than expected and sometimes it can
prevent the driver from operating properly.
The ratio of the OVP capacitors should be the inverse of
the OVP resistors. For example, if RUPPER/RLOWER = 33/1,
then CUPPER/CLOWER = 1/33 with CUPPER = 100pF and
CLOWER = 3.3nF.
FIGURE 19. SIMPLIFIED CURRENT SOURCE CIRCUIT
Dynamic Headroom Control
The ISL97673 features a proprietary Dynamic Headroom
Control circuit that detects the highest forward voltage
string or effectively the lowest voltage from any of the
CH0-CH5 pins digitally. When the lowest channel voltage
is lower than the short circuit threshold, VSC, such
voltage will be used as the feedback signal for the boost
regulator. The boost makes the output to the correct
level such that the lowest channel is at the target
headroom voltage. Since all LED stacks are connected to
the same output voltage, the other channel pins will have
a higher voltage, but the regulated current source circuit
on each channel will ensure that each channel has the
same current. The output voltage will regulate cycle-bycycle and it is always referenced to the highest forward
voltage string in the architecture.
Operating Modes
The ISL97673 has extensive operating modes such as
SMBus controlled PWM or DC dimmings, PWM dimming
with phase shift control and more. Depending on the pin
5 (SEL1) condition, pins 6 and 7 correspond to different
operating modes as shown in Table 1.
Current Matching and Current Accuracy
Each channel of the LED current is regulated by the
current source circuit, as shown in Figure 19.
11
FN7633.2
October 5, 2012
ISL97673
DC CURRENT ADJUSTMENT
TABLE 1.
Once RSET is fixed, the LED DC current can be adjusted
through Register 0x07 (BRTDC) as Equation 3:
SEL1
SEL2
OPERATING MODE
High
N/A
Selectable by SMBus/I2C Interface
Float
High
PWMI, Fixed-Delay Phase Shift PWM
Float
Float
PWMI, Equal-Phase Phase Shift PWM
Float
Low
PWMI, No-Delay PWM
Low
High
Not Used
Low
Float
DC Current Adjustment
Low
Low
Direct PWM
• When SEL1 is high, Pins 6 and 7 Correspond to
SMBDAT and SMBCLK Accordingly. The dimming duty
cycle is controlled by the SMBus/I2C communications
and the dimming frequency is set by RFPWM.
• When SEL1 is floating and SEL2 is high, the channels
will be in phase shift mode with fixed delay. The
dimming signal is derived from the applied PWMI
signal and the dimming frequency is set by RFPWM.
• When SEL1 is floating and SEL2 is floating, the
channels will be in phase shift mode with equal
phase. The dimming signal is derived from the
applied PWMI signal and the dimming frequency is
set by RFPWM.
• When SEL1 is floating and SEL2 is low, the channels
phase shift mode is disabled. The dimming signal is
derived from the applied PWMI signal and the
dimming frequency is set by RFPWM.
• When SEL1 is low and SEL2 is high, this combination
is not used thus the operation will not change.
• When SEL1 is low and SEL2 is floating, it is in DC
dimming mode such that the output current is
averaged in DC and is proportional to the applied
PWMI signal duty cycle.
• When SEL1 is low and SEL2 is low, it is in direct PWM
mode such that the dimming follows directly from
the applied PWMI signal.
Dimming Controls
The ISL97673 allow two ways of controlling the LED
current, and therefore, the brightness. They are:
1. DC current adjustment
2. PWM chopping of the LED current defined in Step 1.
There are various ways to achieve DC or PWM current
control, which will be described in the following.
MAXIMUM DC CURRENT SETTING
The initial brightness should be set by choosing an
appropriate value for RSET. This should be chosen to fix
the maximum possible LED current:
( 410.5 )
I LEDmax = ------------------R SET
I LED = 1.58x ( BRTDC ⁄ R SET )
(EQ. 3)
BRTDC can be programmed from 0 to 255 in decimal and
defaults to 255 (0xFF). If left at the default value, LED
current will be fixed at ILEDmax. BRTDC can be adjusted
dynamically on the fly during operation and a “0” value
disconnects all channels.
For example, if the maximum required LED current
(ILED(max)) is 20mA, rearranging Equation 2 yields
Equation 4:
R SET = 410.5 ⁄ 0.02 = 20.52kΩ
(EQ. 4)
If BRTDC is set to 200 then:
(EQ. 5)
I LED = 1.58 • 200 ⁄ 20100 = 15.7mA
PWM CONTROL
The ISL97673 provides two different PWM dimming
methods, as described in the following. Each of these
methods results in PWM chopping of the current in the
LEDs for all 6 channels to provide an average LED
current. During the On periods, the LED current will be
defined by the value of RSET and BRTDC, as described in
Equations 2 and 3. The source of the PWM signal can be
described as follows:
1. SMBus/I2C generated 256 level duty cycle
programmed through the SMBus/I2C.
2. External signal from PWM.
The default PWM dimming is in SMBus/I2C mode. In both
methods, the average LED current of each channel is
controlled by ILED and the PWM duty cycle in percent as:
I LED ( ave ) = I LED × PWM
(EQ. 6)
Method 1 (SMBus/I2C controlled PWM)
To use this mode, users need to set Register 0x01 to
0x05 with EN/PWM in logic high.
The average LED current of each channel is controlled
by the SMBus/I2C setting as:
I LED ( ave ) = I LED × ( BRT ⁄ 255 )
(EQ. 7)
where BRT is the PWM brightness level programmed in
the Register 0x00. BRT ranges from 0 to 255 in decimal
and defaults to 255 (0xFF). BRT = 0 disconnects all
channels.
(EQ. 2)
12
FN7633.2
October 5, 2012
ISL97673
Method 2 (External applied PWM)
To use this mode users need to set Register 0x01 to 0x03
The average LED current of each channel can also be
controlled by an external PWM signal as Equation 8:
(EQ. 8)
I LILED ( ave ) = I LED × PWM
60%
PWMI
40%
ILED0
60%
40%
tD1
ILED1
tD1
ILED2
PWM Dimming Frequency Adjustment
(Applicable to SMBus/I2C controlled PWM
and DPST Modes)
Except for the external PWM dimming mode, the
dimming frequencies of any other modes are set by an
external resistor at the FPWM pin as Equation 9:
tD1
ILED3
tD1
ILED4
tD1
ILED5
tD2
tFPWM
ILED0
7
6.66 ×10
F PWM = -----------------------RFPWM
tON
tOFF
(EQ. 9)
where FPWM is the desirable PWM dimming frequency
and RFPWM is the setting resistor.
The PWM dimming frequency can be set or applied up to
30kHz with duty cycle from 0.4% to 100%.
FIGURE 21. 6 EQUAL PHASE CHANNELS PHASE SHIFT
ILLUSTRATION
tPWMin
PWMI
60%
40%
tFPWM
(tPWMout)
PHASE SHIFT CONTROL
ILED1
The ISL97673 is capable of delaying the phase of each
current source to minimize load transients. By default,
phase shifting is disabled as shown in Figure 20 where
the channels PWM currents are switching uniformly. The
duty cycles can be controlled by the data in PWM
Brightness Control Register via the SMBus/I2C interface,
an external PWM signal with the frequency set by the
RFPWM, or by an external PWM signal with the frequency
set by the incoming signal.
ILED2
tON
tOFF
60%
40%
tD1
tD1
ILED3
tD1
ILED4
tD2
ILED1
tD1 = Fixed Delay with Integer only while the decimal value will be discarded (eg. 63.75=63)
tFPWM
ILED0
tON
tOFF
FIGURE 22. 4 EQUAL PHASE CHANNELS PHASE SHIFT
ILLUSTRATION
When EqualPhase = 1, the phase shift evenly spreads
the channels switching across the PWM cycle, depending
on how many channels are enabled, as shown in
Figures 21 and 22. Equal phase means there are fixed
delays between channels and such delay can be
calculated as Equations 10 and 11:
ILED1
ILED2
ILED3
ILED4
t FPWM 255
t D1 = ------------------- x ⎛ ----------⎞
255 ⎝ N ⎠
(EQ. 10)
t FPWM
255
t D2 = ------------------- x ⎛ 255 – ( N – 1 ) ⎛ ----------⎞ ⎞
⎝ N ⎠⎠
255 ⎝
(EQ. 11)
ILED5
FIGURE 20. NO DELAY (DEFAULT PHASE SHIFT
DISABLED)
where (255/N) is rounded down to the nearest integer.
For example, if N = 6, (255/N) = 42, that leads to:
tD1 = tFPWM x 42/255
tD2 = tFPWM x 45/255
where tFPWM is the sum of tON and tOFF. N is the number
of LED channels. The ISL97673 will detect the numbers
of operating channels automatically.
13
FN7633.2
October 5, 2012
ISL97673
tFPWM
ILED0
tON
tOFF
tPD
ILED1
tPD
ILED2
tPD
ILED3
tPD
ILED4
tPD
ILED5
FIGURE 23. PHASE SHIFT WITH 7-BIT
PROGRAMMABLE DELAY
The ISL97673 allows the user to program the amount of
phase shift degree in 7-bit resolution, as shown in
Figure 24. To enable programmable phase shifting, the
user must write to the Phase Shift Control register with
EqualPhase = 0 and the desirable phase shift value of
PhaseShift[6:0]. The delay between CH5 and the
repeated CH0 is the rest of the PWM cycle.
Switching Frequency
There are 2 levels of switching frequencies enable for the
boost regulator’s control of the LX pin: 600kHz or
1.2MHz. Each can be programmed in the Configuration
Register 0x08 bit 2. The default switching frequency is at
600kHz.
5V Low Dropout Regulator
A 5V LDO regulator is present at the VDC pin to develop
the necessary low voltage supply, which is used by the
chips internal control circuitry. Because VDC is an LDO
pin, it requires a bypass capacitor of 1µF or more for the
regulation. Low input voltage also allows only lower
output voltage applications only with the maximum
boost ratio defined in “Components Selections” on
page 24. The VDC pin can be used as a coarse reference
with a few mA sourcing capability.
In-rush Control and Soft-start
The ISL97673 has separately built in independent in-rush
control and soft-start functions. The in-rush control
function is built around the short circuit protection FET,
and is only available in applications, which include this
device. At start-up, the fault protection FET is turned on
slowly due to a 15µA pull-down current output from the
FAULT pin. This discharges the fault FET's gate-source
capacitance, turning on the FET in a controlled fashion.
As this happens, the output capacitor is charged slowly
through the weakly turned on FET before it becomes fully
enhanced. This results in a low in-rush current. This
current can be further reduced by adding a capacitor (in
the 1nF to 5nF range) across the gate-source terminals
of the FET.
Once the chip detects that the fault protection FET is
turned on hard, it is assumed that in-rush has
completed. At this point, the boost regulator will begin to
switch and the current in the inductor will ramp-up. The
14
current in the boost power switch is monitored and the
switching is terminated in any cycle where the current
exceeds the current limit. The ISL97673 includes a
soft-start feature where this current limit starts at a low
value (275mA). This is stepped up to the final 2.2A
current limit in 7 further steps of 275mA. These steps will
happen over at least 8ms, and will be extended at low
LED PWM frequencies if the LED duty cycle is low. This
allows the output capacitor to be charged to the required
value at a low current limit and prevents high input
current for systems that have only a low to medium
output current requirement.
For systems with no master fault protection FET, the
inrush current will flow towards COUT when VIN is applied
and it is determined by the ramp rate of VIN and the
values of COUT and L.
Fault Protection and Monitoring
The ISL97673 features extensive protection functions to
cover all the perceivable failure conditions. The failure
mode of a LED can be either open circuit or as a short.
The behavior of an open circuited LED can additionally
take the form of either infinite resistance or, for some
LEDs, a zener diode, which is integrated into the device
in parallel with the now opened LED.
For basic LEDs (which do not have built-in zener diodes),
an open circuit failure of an LED will only result in the loss
of one channel of LEDs without affecting other channels.
Similarly, a short circuit condition on a channel that
results in that channel being turned off does not affect
other channels unless a similar fault is occurring. LED
faults are reported via the SMBus/I2C interface to
Register 0x02 (Fault/Status register). The controller is
able to determine which channels have failed via Register
0x09 (Output Masking register). The controller can also
choose to use Register 0x09 to disable faulty channels at
start-up, resulting in only further faulty channels being
reported by Register 0x02.
Due to the lag in boost response to any load change at its
output, certain transient events (such as LED current
steps or significant step changes in LED duty cycle) can
transiently look like LED fault modes. The ISL97673 uses
feedback from the LEDs to determine when it is in a
stable operating region and prevents apparent faults
during these transient events from allowing any of the
LED stacks to fault out. See Table 2 for more details.
A fault condition that results in high input current due to
a short on VOUT will result in a shutdown of all output
channels. The control device logic will remain functional
such that the Fault/Status Register can be interrogated
by the system. The root cause of the failure will be
loaded to the volatile Fault/Status Register so that the
host processor can interrogate the data for failure
monitoring.
Short Circuit Protection (SCP)
The short circuit detection circuit monitors the voltage on
each channel and disables faulty channels which are
detected above the programmed short circuit threshold.
FN7633.2
October 5, 2012
ISL97673
There are three selectable levels of short circuit threshold
(3.6V, 4.8V, and 5.85V) that can be programmed through
the Configuration Register 0x08. When an LED becomes
shorted, the action taken is described in Table 2. The
default short circuit threshold is 5.85V. The detection of
this failure mode can be disabled via Register 0x08.
Open Circuit Protection (OCP)
When one of the LEDs becomes open circuit, it can
behave as either an infinite resistance or a gradually
increasing finite resistance. The ISL97673 monitors the
current in each channel such that any string which
reaches the intended output current is considered
“good”. Should the current subsequently fall below the
target, the channel will be considered an “open circuit”.
Furthermore, should the boost output of the ISL97673
reaches the OVP limit or should the lower
over-temperature threshold be reached, all channels
which are not “good” will immediately be considered as
“open circuit”. Detection of an “open circuit” channel will
result in a time-out before disabling of the affected
channel. This time-out is run when the device is above
the lower over-temperature threshold in an attempt to
prevent the upper over-temperature trip point from
being reached.
Some users employ some special types of LEDs that
have zener diode structure in parallel with the LED for
ESD enhancement, thus enabling open circuit operation.
When this type of LED goes open circuit, the effect is as
if the LED forward voltage has increased, but no light is
emitted. Any affected string will not be disabled, unless
the failure results in the boost OVP limit being reached,
allowing all other LEDs in the string to remain
functional. Care should be taken in this case that the
boost OVP limit and SCP limit are set properly, so as to
make sure that multiple failures on one string do not
cause all other good channels to be faulted out. This is
due to the increased forward voltage of the faulty
channel making all other channel look as if they have
LED shorts. See Table 2 for details for responses to fault
conditions.
Overvoltage Protection (OVP)
The integrated OVP circuit monitors the output voltage
and keeps the voltage at a safe level. The OVP threshold
is set as:
OVP = 1.21V × ( R UPPER + R LOWER ) ⁄ R LOWER
Undervoltage Lockout
If the input voltage falls below the UVLO level of 2.45V,
the device will stop switching and be reset. Operation will
restart only if the device is re-enabled through the
SMBus/I2C interface once the input voltage is back in the
operating range. In non-SMBus/I2C applications, the part
will automatically restart once the input voltage clears
the UVLO threshold with the part already enabled.
Input Overcurrent Protection
During normal switching operation, the current through
the internal boost power FET is monitored. If the current
exceeds the current limit, the internal switch will be
turned off. This monitoring happens on a cycle by cycle
basis in a self protecting way.
Additionally, the ISL97673 monitors the voltage at the LX
and OVP pins. At startup, a fixed current is injected out of
the LX pins and into the output capacitor. The device will
not start up unless the voltage at LX exceeds 1.2V. The
OVP pin is also monitored such that if it rises above and
subsequently falls below 20% of the target OVP level, the
input protection FET will be switched off.
Over-Temperature Protection (OTP)
The ISL97673 includes two over-temperature thresholds.
The lower threshold is set to +130°C. When this
threshold is reached, any channel which is outputting
current at a level below the regulation target will be
treated as “open circuit” and disabled after a time-out
period. The intention of the lower threshold is to allow
bad channels to be isolated and disabled before they
cause enough power dissipation (as a result of other
channels having large voltages across them) to hit the
upper temperature threshold.
The upper threshold is set to +150°C. Each time this is
reached, the boost will stop switching and the output
current sources will be switched off. Hitting of the upper
threshold will also set the thermal fault bit of the
Fault/Status register 0x02. Unless disabled via the EN
pin, the device stays in an active state throughout,
allowing an external processor to interrogate the fault
condition.
For the extensive fault protection conditions, please refer
to Figure 24 and Table 2 for details.
(EQ. 12)
These resistors should be large to minimize the power
loss. For example, a 1MkΩ RUPPER and 30kΩ RLOWER sets
OVP to 41.2V. Large OVP resistors also allow COUT
discharges slowly during the PWM Off time. Parallel
capacitors should also be placed across the OVP resistors
such that RUPPER/RLOWER = CLOWER/CUPPER. Using a
CUPPER value of at least 30pF is recommended. These
capacitors reduce the AC impedance of the OVP node,
which is important when using high value resistors.
15
FN7633.2
October 5, 2012
ISL97673
LX
VIN
DRIVER
IMAX
FAULT
ILIMIT
VOUT
O/P
SHORT
OVP
FET
DRIVER
LOGIC
CH0
VSC
CH5
VSET/2
REG
THRM
SHDN
REF
OTP
T2
TEMP
SENSOR
T1
VSET
+
Q0 VSET
PWM/OC0/SC0
SMB/I2C
CONTROL
LOGIC
Q5
-
-
FAULT/
STATUS
REGISTER
+
PWM/OC5/SC5
DC CURRENT
FIGURE 24. SIMPLIFIED FAULT PROTECTIONS
TABLE 2. PROTECTIONS TABLE
VOUT
REGULATED
BY
CASE
FAILURE MODE
DETECTION MODE
1
CH0 Short Circuit
Upper
Over-Temperature
Protection limit (OTP)
not triggered and CH0
< 4V
CH0 ON and burns power.
CH1 through CH5 Normal
Highest VF of
CH1 through
CH5
2
CH0 Short Circuit
Upper OTP triggered
but VCH0 < 4V
All channels go off until chip
cooled and then comes back
on with current reduced to
76%. Subsequent OTP
triggers will reduce IOUT
further.
Same as CH0
Highest VF of
CH1 through
CH5
3
CH0 Short Circuit
Upper OTP not
triggered but CH0 >
4V
CH1 disabled after 6 PWM
cycle time-out.
CH1 through CH5 Normal
Highest VF of
CH1 through
CH5
4
CH0 Open Circuit
with infinite
resistance
Upper OTP not
triggered and CH0 <
4V
VOUT will ramp to OVP. CH1
will time-out after 6 PWM
cycles and switch off. VOUT
will drop to normal level.
CH1 through CH5 Normal
Highest VF of
CH1 through
CH5
5
CH0 LED Open
Circuit but has
paralleled Zener
Upper OTP not
triggered and CH0 <
4V
CH1 remains ON and has
highest VF, thus VOUT
increases.
CH1 through CH5 ON, Q1
through Q5 burn power
VF of CH0
16
FAILED CHANNEL ACTION
GOOD CHANNELS
ACTION
FN7633.2
October 5, 2012
ISL97673
TABLE 2. PROTECTIONS TABLE (Continued)
CASE
FAILURE MODE
DETECTION MODE
VOUT
REGULATED
BY
GOOD CHANNELS
ACTION
FAILED CHANNEL ACTION
6
CH0 LED Open
Circuit but has
paralleled Zener
Upper OTP triggered
but CH0 < 4V
All channels go off until chip
cooled and then comes back
on with current reduced to
76%. Subsequent OTP
triggers will reduce IOUT
further
Same as CH0
7
CH0 LED Open
Circuit but has
paralleled Zener
Upper OTP not
triggered but CHx >
4V
CH0 remains ON and has
highest VF, thus VOUT
increases.
VOUT increases, then CH-X VF of CH0
switches OFF after 6 PWM
cycles. This is an unwanted
shut off and can be
prevented by setting OVP at
an appropriate level.
8
Channel-toChannel
ΔVF too high
Lower OTP triggered
but CHx < 4V
Any channel at below the target current will fault out after
6 PWM cycles.
Remaining channels driven with normal current.
Highest VF of
CH0 through
CH5
9
Channel-toChannel ΔVF too
high
Upper OTP triggered
but CHx < 4V
All channels go off until chip cooled and then comes back
on with current reduced to 76%. Subsequent OTP triggers
will reduce IOUT further
Highest VF of
CH0 through
CH5
10
Output LED stack
voltage too high
VOUT > VOVP
Any channel that is below the target current will time-out
after 6 PWM cycles, and VOUT will return to the normal
regulation voltage required for other channels.
Highest VF of
CH0 through
CH5
11
VOUT/LX shorted
to GND at start-up
or VOUT shorted in
operation
LX current and timing The chip is permanently shutdown 31mS after power-up if
VOUT/Lx is shorted to GND.
are monitored.
OVP pins monitored
for excursions below
20% of OVP threshold.
SMBCLK
tLOW
VF of CH0
tF
tR
VIH
VIL
tHD:STA
tHD:DAT
tHIGH
tSU:DAT
tSU:STA
tSU:STO
SMBDAT
VIH
VIL
P
tBUF
S
S
P
NOTES:
SMBus/I2C Description
S = start condition
P = stop condition
A = acknowledge
A = not acknowledge
R/W = read enable at high; write enable at low
FIGURE 25. SMBus/I2C INTERFACE
17
FN7633.2
October 5, 2012
ISL97673
1
7
1
1
8
1
8
1
1
S
Slave Address
W
A
Command Code
A
Data byte
A
P
Master to Slave
Slave to Master
FIGURE 26. WRITE BYTE PROTOCOL
1
7
1
1
8
1
1
8
1
1
8
1
1
S
Slave Address
W
A
Command
Code
A
S
Slave Address
R
A
Data Byte
A
P
Master to Slave
Slave to Master
FIGURE 27. READ BYTE PROTOCOL
Write Byte
The Write Byte protocol is only three bytes long. The first
byte starts with the slave address followed by the
“command code,” which translates to the “register index”
being written. The third byte contains the data byte that
must be written into the register selected by the
“command code”. A shaded label is used on cycles during
which the slaved backlight controller “owns” or “drives”
the Data line. All other cycles are driven by the “host
master.”
01011000b. If the device is in the read mode where bit 0
is 1, the slave address byte is 0x59 or 01011001b.
The backlight controller may sense the state of the pins
at POR or during normal operation. The pins will not
change state while the device is in operation.
MSB
0
LSB
1
0
1
1
0
0
R/W
Slave Device Address
DEVICE
IDENTIFIER
DEVICE
ADDRESS
RE
AD
/W
RI
TE
As shown in the Figure 27, the four byte long Read Byte
protocol starts out with the slave address followed by
the “command code” which translates to the “register
index.” Subsequently, the bus direction turns around
with the re-broadcast of the slave address with bit 0
indicating a read (“R”) cycle. The fourth byte contains
the data being returned by the backlight controller. That
byte value in the data byte reflects the value of the
register being queried at the “command code” index.
Note the bus directions, which are highlighted by the
shaded label that is used on cycles during which the
slaved backlight controller “owns” or “drives” the Data
line. All other cycles are driven by the “host master.”
BI
T
Read Byte
FIGURE 28. SLAVE ADDRESS BYTE DEFINITION
SMBus/I2C Register Definitions
The backlight controller registers are Byte wide and
accessible via the SMBus/I2C Read/Write Byte
protocols. Their bit assignments are provided in the
following sections with reserved bits containing a
default value of “0”.
The slave address contains 7 MSB plus one LSB as R/W
bit, but these 8 bits are usually called Slave Address
bytes. As shown in Figure 28, the high nibble of the Slave
Address byte is 0x5 or 0101b to denote the “backlight
controller class.” Bit 3 in the lower nibble of the Slave
Address byte is 1. Bit 0 is always the R/W bit, as
specified by the SMBus/I2C protocol. Note: In this
document, the device address will always be expressed
as a full 8-bit address instead of the shorter 7-bit address
typically used in other backlight controller specifications
to avoid confusion. Therefore, if the device is in the write
mode where bit 0 is 0, the slave address byte is 0x58 or
18
FN7633.2
October 5, 2012
ISL97673
TABLE 3A. REGISTER LISTING
ADDRESS
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DEFAULT
VALUE
SMBus/I2C
PROTOCOL
BRT7
BRT6
BRT5
BRT4
BRT3
BRT2
BRT1
BRT0
0xFF
Read and Write
PWM_SEL
BL_CTL
0x00
Read and Write
FAULT
0x00
Read Only
0x00
PWM
Brightness
Control
Register
0x01
Device Control Reserved
Register
Reserved
Reserved Reserved Reserved PWM_MD
0x02
Fault/Status
Register
Reserved
Reserved
2_CH_SD 1_CH_SD BL_STAT OV_CURR THRM_SHDN
0x03
Si Revision
Register
1
1
0
0
1
REV2
REV1
REV0
0xC8
Read Only
0x07
DC Brightness
Control
Register
BRTDC7
BRTDC6
BRTDC5
BRTDC4
BRTDC3
BRTDC2
BRTDC1
BRTDC0
0xFF
Read and Write
0x08
Configuration
Register
Reserved DirectPWM PWMtoDC
BstSlew
Rate1
BstSlew
Rate0
FSW
VSC1
VSC0
0x1F
Read and Write
0x09
Output
Channel
Register
Reserved
Reserved
CH5
CH4
CH3
CH2
CH1
CH0
0x3F
Read and Write
0x0A
Phase Shift
Deg
Equal
Phase
Phase
Shift6
Phase
Shift5
Phase
Shift4
Phase
Shift3
Phase
Shift2
Phase
Shift1
Phase
Shift0
0x00
Read and Write
TABLE 3B. DATA BIT DESCRIPTIONS
ADDRESS
REGISTER
DATA BIT DESCRIPTIONS
0x00
PWM Brightness Control
Register
BRT[7..0] = 256 steps of DPWM duty cycle brightness control
0x01
Device Control Register
PWM_MD = PWM mode select bit (1 = absolute brightness, 0 = % change),
default = 0
PWM_SEL = Brightness control select bit (1 = control by PWMI, 0 = control by
SMBus/I2C), default = 0
BL_CTL = BL On/Off (1 = On, 0 = Off), default = 0
0x02
Fault/Status Register
2_CH_SD = Two LED output channels are shutdown (1 = shutdown, 0 = OK)
1_CH_SD = One LED output channel is shutdown (1 = shutdown, 0 = OK)
BL_STAT = BL status (1 = BL On, 0 = BL Off)
OV_CURR = Input overcurrent (1 = Overcurrent condition, 0 = Current OK)
THRM_SHDN = Thermal Shutdown (1 = Thermal fault, 0 = Thermal OK)
FAULT = Fault occurred (Logic “OR” of all of the fault conditions)
0x03
Si Revision Register
REV[2..0] = Silicon rev (Rev 0 through Rev 7 allowed for silicon spins)
0x07
DC Brightness Control
Register
BRTDC[7..0] = 256 steps of DC brightness control
0x08
Configuration Register
DirectPWM = Forces the PWM input signal to directly control the current sources.
PWM-to-DC = Switches current sources on and varies DC level rather than PWMing.
BstSlewRate = Controls strength of FET driver. 00 - 25% drive strength, 01 - 50%
drive strength, 10 - 75% drive strength, 11 - 100% drive strength.
FSW = Switching frequencies selection, FSW = 0 = 1.2MHz. FSW = 1 = 600kHz
VSC[1..0] = Short circuit thresholds selection, 0 = disabled, 1 = 3.6V, 2 = 4.8V, 3
= 5.8V
0x09
Output Channel Select and
Fault Readout Register
CH[5..0] = Output Channel Read and Write. In Write, 1 = Channel Enabled, 0 =
Channel Disabled. In Read, 1 = Channel OK, 0 = Channel Shutdown or Disabled
0x0A
Phase Shift Degree
EqualPhase = Controls phase shift mode - When 0, phase shift is defined by
PhaseShift<6:0>. When 1, phase shift is 360/N (where N is the number of channels
enabled).
PS[6..0] = 7-bit Phase shift setting - phase shift between each channel is
PhaseShift<6:0>/(255*PWMFreq). In direct PWM modes, phase shift between each
channel is PhaseShift<6:0>/12.8MHz. Note that user must not specify a value that
gives >360° shift between first and last channels.
19
FN7633.2
October 5, 2012
ISL97673
PWM Brightness Control Register (0x00)
The Brightness control resolution has 256 steps of PWM
duty cycle adjustment. The bit assignment is shown in
Figure 29. All of the bits in this Brightness Control
Register can be read or write. Step 0 corresponds to the
minimum step where the current is less than 10µA.
Steps 1 to 255 represent the linear steps between 0.39%
and 100% duty cycle with approximately 0.39% duty
cycle adjustment per step.
• An SMBus/I2C Write Byte cycle to Register 0x00 sets
the PWM brightness level only if the backlight
controller is in SMBus/I2C mode (see Table 3A
• An SMBus/I2C Read Byte cycle to Register 0x00
returns the programmed PWM brightness level.
• An SMBus/I2C setting of 0xFF for Register 0x00 sets
the backlight controller to the maximum brightness.
• An SMBus/I2C setting of 0x00 for Register 0x00 sets
the backlight controller to the minimum brightness
output.
• Default value for Register 0x00 is 0xFF.
PWM BRIGHTNESS CONTROL
REGISTER
REGISTER 0x00
BRT7
Operating Modes selected by Device Control Register
Bits 1 and 2).
BRT6
BRT5
BRT4
BRT3
BRT2
BRT1
BRT0
Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W)
BIT ASSIGNMENT
BIT FIELD DEFINITIONS
= 256 steps of PWM brightness levels
BRT[7..0]
FIGURE 29. DESCRIPTIONS OF BRIGHTNESS CONTROL REGISTER
Device Control Register (0x01)
REGISTER 0x01
DEVICE CONTROL REGISTER
RESERVED
RESERVED RESERVED RESERVED RESERVED
PWM_MD PWM_SEL
Bit 7 (R/W)
Bit 6 (R/W)
Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W)
PWM_MD PWM_SEL
Bit 5 (R/W)
Bit 4 (R/W)
BL_CTL
Bit 3 (R/W)
BL_CTL
MODE
X
X
0
Backlight Off
0
0
1
SMBus/I2C and PWM dimming
(DPST)
0
1
1
PWMI controlled PWM dimming
1
0
1
SMBus/I2C controlled PWM dimming
1
1
1
Backlight On but stays with previous
mode selection
FIGURE 30. DESCRIPTIONS OF DEVICE CONTROL REGISTER
20
FN7633.2
October 5, 2012
ISL97673
This register has two bits that control either SMBus/I2C
controlled or external PWM controlled PWM dimming and
a single bit that controls the BL ON/OFF state. The
remaining bits are reserved. The bit assignment is shown
in Figure 30. All other bits in the Device Control Register
will read as low unless otherwise written.
this register are read-only, with the exception of Bit 0,
which can be cleared by writing to it.
• All defined control bits return their current, latched
value when read.
• A Read Byte cycles to Register 0x2 also returns
FAULT as the logical OR of THRM_SHDN, OV_CURR,
2_CH_SD, and 1_CH_SD should these events occur.
A value of 1 written to BL_CTL turns on the BL in 4ms or
less after the write cycle completes. The BL is
• deemed to be on when Bit 3 BL_STAT of Register 0x02
is 1 and Register 0x09 is not 0.
• A value of 0 written to BL_CTL immediately turns off the
BL. The BL is deemed to be off when Bit 3 BL_STAT of
Register 0x02 is 0 and Register 0x09 is 0.
SMBus/I2C
• When
mode with DPST is selected,
Register 0x00 reflects the last value written to it
from SMBus/I2C.
• The default value for Register 0x01 is 0x00.
Fault/Status Register (0x02)
This register has 6 status bits that allow monitoring of
the backlight controller’s operating state. Bit 0 is a logical
“OR” of all fault codes to simplify error detection. Not all
of the bits in this register are fault related (Bit 3 is a
simple BL status indicator). The remaining bits are
reserved and return a “0” when read. All of the bits in
• A Read Byte cycle to Register 0x02 indicates the
current BL on/off status in BL_STAT (1 if the BL is on,
0 if the BL is off).
• 1_CH_SD returns a 1 if one or more channels have
faulted out.
• 2_CH_SD returns a 1 if two or more channels have
faulted out.
• A fault will not be reported in the event that the BL is
commanded on and then immediately off by the
system.
• When FAULT is set to 1, it will remain at 1 even if the
signal which sets it goes away. FAULT will be cleared
when the BL_CTL bit of the Device Control Register is
toggled or when written low. At that time, if the fault
condition is still present or reoccurs, FAULT will be
set to 1 again. BL_STAT will not cause FAULT to be
set.
• The default value for Register 0x02 is 0x00.
Si Revision Register (0x03)
The Si Revision register has 3 bits that allows up to 8
silicon revisions each. In order to keep the number of
silicon revisions low, the revision field will not be updated
unless the part will make it out to the user’s factory.
Thus, if during the first silicon engineering development
process, 2 silicon spins were needed, the revision
remains as 0. All of the bits in this register are read-only.
• The default value for Register 0x03 is 0xC8.
The initial value of REV shall be 0. Subsequent values of
REV will increment by 1.
REGISTER 0x02
FAULT/STATUS REGISTER
RESERVED RESERVED
Bit 7 (R)
Bit 6 (R)
2_CH_SD
1_CH_SD
BL_STAT
Bit 5 (R)
Bit 4 (R)
Bit 3 (R)
OV_CURR THRM_SHDN
Bit 2 (R)
Bit 1 (R)
FAULT
Bit 0 (R)
BIT
BIT ASSIGNMENT
BIT FIELD DEFINITIONS
Bit 5
2_CH_SD
= Two LED output channels are shutdown (1 = shutdown, 0 = OK)
Bit 4
1_CH_SD
= One LED output channel is shutdown (1 = shutdown, 0 = OK)
Bit 3
BL_STAT
= BL Status (1 = BL On, 0 = BL Off)
Bit 2
OV_CURR
= Input Overcurrent (1 = Overcurrent condition, 0 = Current OK)
Bit 1
THRM_SHDN
Bit 0
FAULT
= Thermal Shutdown (1 = Thermal Fault, 0 = Thermal OK)
= Fault occurred (Logic “OR” of all of the fault conditions)
FIGURE 31. DESCRIPTIONS OF FAULT/STATUS REGISTER
21
FN7633.2
October 5, 2012
ISL97673
REGISTER 0x03
ID REGISTER
LED
PANEL
MFG3
MFG2
MFG1
MFG0
REV2
REV1
REV0
Bit 7 = 1
Bit 6 (R)
Bit 5 (R)
Bit 4 (R)
Bit 3 (R)
Bit 2 (R)
Bit 1 (R)
Bit 0 (R)
BIT ASSIGNMENT
MFG[3..0]
REV[2..0]
BIT FIELD DEFINITIONS
= Manufacturer ID. See “Si Revision Register
(0x03)” on page 21.
data 0 to 8 in decimal correspond to other vendors
data 9 in decimal represents Intersil ID
data 10 to 14 in decimal are reserved
data 15 in decimal Manufacturer ID is not
implemented
= Silicon rev (Rev 0 through Rev 7 allowed for
silicon spins)
FIGURE 32. DESCRIPTIONS OF ID REGISTER
DC Brightness Control Register (0x07)
REGISTER 0x07
DC BRIGHTNESS CONTROL
REGISTER
BRTDC7
BRTDC5
BRTDC6
BRTDC4
BRTDC3
BRTDC2
BRTDC1
BRTDC0
Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W)
BIT ASSIGNMENT
BRTDC[7..0]
BIT FIELD DEFINITIONS
= 256 steps of DC brightness levels
FIGURE 33. DESCRIPTIONS OF DC BRIGHTNESS CONTROL REGISTER
The DC Brightness Control Register 0x07 allows users to
have additional dimming flexibility by:
Configuration Register (0x08)
1. Effectively achieving 16-bits of dimming control
when DC dimming is combined with PWM dimming.
The Configuration Register provides many extra functions
that users can explore in order to optimize the driver
performance at a given application.
2. Achieving visual or audio noise free 8-bit DC
dimming over potentially noisy PWM dimming.
A Direct PWM bit allows Direct PWM where the output
current follows the same input PWM signal.
The bit assignment is shown in Figure 33. All of the bits
in this Register can be read or write. Steps 0 to 255
represent the linear steps of current adjustment in DC on
the fly. It can also be considered as the peak current
factory calibration feature to account for various LED
production batch variations, but external EEPROM
settings storing and restoring are required.
• An SMBus/I2C Write Byte cycle to Register 0x07 sets
the brightness level in DC only.
• An SMBus/I2C Read Byte cycle to Register 0x07
returns the current DC brightness level.
• Default value for Register 0x07 is 0xFF.
22
A PWM-to-DC bit allows users to provide convert PWM
input into average DC LED current output with the level
that is proportional to the input PWM duty cycle.
A BstSlewRate bit allows users to control the boost FET
slew rate (the rates of turn-on and turn-off). The slew
rate can be selected to four relative strengths when
driving the internal boost FET. The purpose of this
function is to allow users to experiment the slew rate
with respect to EMI effect in the system. In general, the
slower the slew rate is, the lower the EMI interference to
the surrounding circuits; however, the switching loss of
the boost FET is also increased.
The FSW bit allows users to set the boost conversion
switching frequency between 1.2MHz and 600kHz.
FN7633.2
October 5, 2012
ISL97673
The Vsc bits allow users to set 3 levels of channel
short-circuit thresholds or disable it.
The bit assignment is shown in Figure 34. The default
value for Register 0x08 is 0x1F.
Output Channel Select and Fault Readout
Register (0x09)
This register can be read or write; the bit position
corresponds to the channel. For example, Bit 0
corresponds to CH0 and Bit 4 corresponds to CH4 and so
on. Writing data to this register, it enables the channels
REGISTER 0x08
of interest. When reading data from this register, any
disabled channel and any faulted out channel will read as
0. This allows the user to determine which channel is
faulty and optionally not enabling it in order to allow the
rest of the system to continue to function. Additionally, a
faulted out channel can be disabled and re-enabled in
order to allow a retry for any faulty channel without
having to power-down the other channels.
The bit assignment is shown in Figure 35. The default for
Register 0x09 is 0x3F.
CONFIGURATION REGISTER
RESERVED
DIRECT PWM
PWM-TO-DC
BSTSLEWRATE1
BSTSLEWRATE0
Bit 7 (R/W)
Bit 6 (R/W)
Bit 5 (R/W)
Bit 4 (R/W)
Bit 3 (R/W)
FSW
VSC1
VSC0
Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W)
BIT ASSIGNMENT
BIT FIELD DEFINITIONS
DirectPWM
Forces the PWMI signal to directly control the current sources. Note that there is some
synchronous delay between PWMI and current sources.
PWM-to-DC
Switches current sources on and varies DC level rather than PWMing.
BstSlewRate[1:0]
FSW
VSC[1..0]
Controls strength of FET driver. 00 - 25% drive strength, 01 to 50% drive strength,
10 -75% drive strength, 11 to 100% drive strength.
2 levels of Switching Frequencies (0 = 1,200kHz, 1 = 600kHz)
3 levels of Short-Circuit Thresholds (0 = disabled, 1 = 3.6V, 2 = 4.8V, 3 = 5.8V)
FIGURE 34. DESCRIPTIONS OF CONFIGURATION REGISTER
REGISTER 0x09
Reserved
Reserved
OUTPUT CHANNEL REGISTER
CH5
CH4
CH3
CH2
CH1
CH0
Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W)
BIT ASSIGNMENT
BIT FIELD DEFINITIONS
CH[5..0]
CH5 = Channel 5, CH4 = Channel 4 and so
on
FIGURE 35. DESCRIPTIONS OF OUTPUT CHANNEL REGISTER
23
FN7633.2
October 5, 2012
ISL97673
REGISTER 0x0A
PHASE SHIFT CONTROL REGISTER
EQUAL
PHASE
PHASESHIFT6
PHASESHIFT5
PHASESHIFT4
PHASESHIFT3
PHASESHIFT2
PHASESHIFT1
PHASESHIFT0
Bit 7 (R/W)
Bit 6 (R/W)
Bit 5 (R/W)
Bit 4 (R/W)
Bit 3 (R/W)
Bit 2 (R/W)
Bit 1 (R/W)
Bit 0 (R/W)
BIT ASSIGNMENT
BIT FIELD DEFINITIONS
EqualPhase
Controls phase shift mode - When 0, phase shift is defined by PhaseShift<6:0>.
When 1, phase shift is 360/N (where N is the number of channels enabled).
PhaseShift[6..0]
7-bit Phase shift setting - phase shift between each channel is
PhaseShift<6:0>/(255*PWMFreq)
In direct PWM modes, phase shift between each channel is
PhaseShift<6:0>/12.8MHz
Note that user must not specify a value that gives >360° shift between first and last
channels.
FIGURE 36. DESCRIPTIONS OF PHASE SHIFT CONTROL REGISTER
Phase Shift Control Register (0x0A)
The Phase Shift Control register is used to set phase
delay between each channels. When bit 7 is set high, the
phase delay is set by the number of channels enabled
and the PWM frequency. The delay time is defined by the
Equation 13:
(EQ. 13)
t DELAY = ( t FPWM ⁄ N )
where N is the number of channels enabled, and tFPWM is
the period of the PWM cycle. When bit 7 is set low, the
phase delay is set by bits 6 to 0 and the PWM frequency.
The delay time is defined by Equation 14:
t DELAY = ( PS < 6, 0 > xt FPWM ⁄ ( 255 ) )
(EQ. 14)
where PS is an integer from 0 to 127, and tFPWM is the
period of the PWM cycle. By default, all the register bits
are set low, which sets zero delay between each channel.
Note that the user should not program the register to
give more than one period of the PWM cycle delay
between the first and last enabled channels.
Components Selections
According to the inductor Voltage-Second Balance
principle, the change of inductor current during the
switching regulator On time is equal to the change of
inductor current during the switching regulator Off time.
Since the voltage across an inductor is:
(EQ. 15)
V L = L × ΔI L ⁄ Δt
and ΔIL @ On = ΔIL @ Off, therefore:
( V I – 0 ) ⁄ L × D × tS = ( VO – VD – VI ) ⁄ L × ( 1 – D ) × tS
(EQ. 16)
where D is the switching duty cycle defined by the turn-on
time over the switching period. VD is Schottky diode
forward voltage that can be neglected for approximation.
24
Rearranging the terms without accounting for VD gives
the boost ratio and duty cycle respectively as:
VO ⁄ VI = 1 ⁄ ( 1 – D )
(EQ. 17)
D = ( VO – VI ) ⁄ VO
(EQ. 18)
Input Capacitor
Switching regulators require input capacitors to deliver
peak charging current and to reduce the impedance of
the input supply. This reduces interaction between the
regulator and input supply, thereby improving system
stability. The high switching frequency of the loop causes
almost all ripple current to flow in the input capacitor,
which must be rated accordingly.
A capacitor with low internal series resistance should be
chosen to minimize heating effects and improve system
efficiency, such as X5R or X7R ceramic capacitors, which
offer small size and a lower value of temperature and
voltage coefficient compared to other ceramic capacitors.
In Boost mode, input current flows continuously into the
inductor; AC ripple component is only proportional to the
rate of the inductor charging, thus, smaller value input
capacitors may be used. It is recommended that an input
capacitor of at least 10µF be used. Ensure the voltage
rating of the input capacitor is suitable to handle the full
supply range.
Inductor
The selection of the inductor should be based on its
maximum current (ISAT) characteristics, power
dissipation (DCR), EMI susceptibility (shielded vs
unshielded), and size. Inductor type and value influence
many key parameters, including ripple current, current
limit, efficiency, transient performance and stability.
The inductor’s maximum current capability must be
adequate enough to handle the peak current at the worst
case condition. If an inductor core is chosen with too low
FN7633.2
October 5, 2012
ISL97673
a current rating, saturation in the core will cause the
effective inductor value to fall, leading to an increase in
peak to average current level, poor efficiency and
overheating in the core. The series resistance, DCR,
within the inductor causes conduction loss and heat
dissipation. A shielded inductor is usually more suitable
for EMI susceptible applications, such as LED
backlighting.
The peak current can be derived from the voltage across
the inductor during the Off period, as expressed in
Equation 19:
IL pk = ( V O × I O ) ⁄ ( 85% × V I ) + 1 ⁄ 2 [ V I × ( V O – V I ) ⁄ ( L × V O × f SW ) ]
(EQ. 19)
The choice of 85% is just an average term for the
efficiency approximation. The first term is the average
current, which is inversely proportional to the input
voltage. The second term is the inductor current change,
which is inversely proportional to L and fSW. As a result,
for a given switching frequency and minimum input
voltage on which the system operates, the inductor ISAT
must be chosen carefully. At a given inductor size,
usually the larger the inductance, the higher the series
resistance because of the extra winding of the coil. Thus,
the higher the inductance, the lower the peak current
capability. The ISL97673 current limit should also have to
be taken into account.
Output Capacitors
A larger output capacitor will also ease the driver
response during PWM dimming Off period due to the
longer sample and hold effect of the output drooping.
The driver does not need to boost harder in the next On
period that minimizes transient current. The output
capacitor is also needed for compensation, and, in
general one to two 4.7µF/50V ceramic capacitors are
suitable for netbook to notebook display backlight
applications.
Schottky Diode
A high-speed rectifier diode is necessary to prevent
excessive voltage overshoot, especially in the boost
configuration. Low forward voltage and reverse leakage
current will minimize losses, making Schottky diodes the
preferred choice. Although the Schottky diode turns on
only during the boost switch Off period, it carries the
same peak current as the inductor, and therefore, a
suitable current rated Schottky diode must be used.
Applications
High Current Applications
Each channel of the ISL97673 can support up to 30mA.
For applications that need higher current, multiple
channels can be grouped to achieve the desirable
current. For example, the cathode of the last LED can be
connected to CH0 to CH2, this configuration can be
treated as a single string with 90mA current driving
capability.
The output capacitor acts to smooth the output voltage
and supplies load current directly during the conduction
phase of the power switch. Output ripple voltage consists
of the discharge of the output capacitor for ILPEAK during
FET On and the voltage drop due to flowing through the
ESR of the output capacitor. The ripple voltage can be
shown as Equation 20:
ΔV CO = ( I O ⁄ C O × D ⁄ f S ) + ( ( I O × ESR )
VOUT
(EQ. 20)
CH0
CH1
The conservation of charge principle in Equation 20 also
brings up the fact that during the boost switch Off period,
the output capacitor is charged with the inductor ripple
current minus a relatively small output current in boost
topology. As a result, the user needs to select an output
capacitor with low ESR and enough input ripple current
capability.
CH2
FIGURE 37. GROUPING MULTIPLE CHANNELS FOR
HIGH CURRENT APPLICATIONS
The choice of X7R over Y5V ceramic capacitor is highly
recommend because X7R capacitor is less sensitive to
capacitance change over voltage but the Y5V capacitor
exhibits very high capacitance coefficient such that its
absolute capacitance can be reduced to 10~20% to the
rated capacitance at maximum voltage.
Output Ripple
ΔVCo, can be reduced by increasing Co or fSW, or using
small ESR capacitors. In general, Ceramic capacitors are
the best choice for output capacitors in small to medium
sized LCD backlight applications due to their cost, form
factor, and low ESR.
25
SMBCLK
SMBCLK
SMBDAT
SMBDAT
EN/PWM
EN/PWM
SMBCLK/SCL
SMBDAT/SDA
EN
FIGURE 38. MULTIPLE DRIVERS OPERATION
FN7633.2
October 5, 2012
ISL97673
Multiple Drivers Operation
For large LCD panels where more than 6 channels of
LEDs are needed, multiple ISL97673s with each driver
having its own supporting components can be controlled
together with the common SMBus/I2C. While the
ISL97673 does not have extra pins strappable slave
address feature, but a separate EN signal can be applied
to each driver for asynchronous operation. A trade-off of
such scheme is that an exact faulty channel cannot be
identified since both ICs have the same I2C slave
address.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
August 1, 2012
FN7633.2
On page 12, changed 401.8 to 410.5 in Equations 2 and 4.
July 18, 2012
FN7633.1
Stamped page 1 “Not Recommended for New Designs”
June 24, 2010
FN7633.0
Initial Release.
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For information regarding Intersil Corporation and its products, see www.intersil.com
26
FN7633.2
October 5, 2012
ISL97673
Package Outline Drawing
L20.3x4
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 3/10
3.00
0.10 M C A B
0.05 M C
A
B
4
20X 0.25
16X 0.50
+0.05
-0.07
17
A
16
6
PIN 1
INDEX AREA
6
PIN 1 INDEX AREA
(C 0.40)
20
1
4.00
2.65
11
+0.10
-0.15
6
0.15 (4X)
A
10
7
VIEW "A-A"
1.65
TOP VIEW
+0.10
-0.15
20x 0.40±0.10
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
C
0.9± 0.10
SEATING PLANE
0.08 C
SIDE VIEW
(16 x 0.50)
(2.65)
(3.80)
(20 x 0.25)
C
(20 x 0.60)
0.2 REF
5
0.00 MIN.
0.05 MAX.
(1.65)
(2.80)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
27
FN7633.2
October 5, 2012
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