DATASHEET

Data Sheet
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1-888-IN
10-Bit, 125/60MSPS, Dual High Speed
CMOS D/A Converter
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 125MSPS
• Low Power . . . . . . . . . . . . . . . 330mW at 5V, 54mW at 3V
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . . . 1 LSB
• Differential Linearity . . . . . . . . . . . . . . . . . . . . . . 0.5 LSB
• Gain Matching (Typ). . . . . . . . . . . . . . . . . . . . . . . . . . 0.5%
• SFDR at 5MHz Output . . . . . . . . . . . . . . . . . . . . . . . 68dBc
• Single Power Supply from +5V to +3V
• CMOS Compatible Inputs
• Excellent Spurious Free Dynamic Range
• Internal Voltage Reference
Ordering Information
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE
MAX
CLOCK
SPEED
PKG.
DWG. # (MHz)
• Dual 10-Bit D/A Converters on a Monolithic Chip
• Pb-Free Available (RoHS Compliant)
Applications
HI5728IN*
HI5728IN
-40 to +85 48 Ld LQFP Q48.7x7A
125
HI5728INZ*
(Note)
HI5728INZ
-40 to +85 48 Ld LQFP Q48.7x7A
(Pb-free)
125
HI5728/6IN
HI5728/6IN
-40 to +85 48 Ld LQFP Q48.7x7A
60
• Wireless Communications
HI5728/6INZ
(Note)
HI5728 /6INZ -40 to +85 48 Ld LQFP Q48.7x7A
(Pb-free)
60
• Signal Reconstruction
HI5728EVAL1
+25
FN4321.5
Features
The HI5728 is a 10-bit, dual 125MSPS D/A converter which
is implemented in an advanced CMOS process. It is
designed for high speed applications where integration,
bandwidth and accuracy are essential. Operating from a
single +5V or +3V supply, the converter provides 20.48mA of
full scale output current and includes an input data register.
Low glitch energy and excellent frequency domain
performance are achieved using a segmented architecture.
A 60MSPS version and an 8-bit (HI5628) version are also
available. Comparable single DAC solutions are the HI5760
(10-bit) and the HI5660 (8-bit).
PART
NUMBER
HI5728
Evaluation Platform
125
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel
specifications.
• Wireless Local Loop
• Direct Digital Frequency Synthesis
• Arbitrary Waveform Generators
• Test Equipment/Instrumentation
• High Resolution Imaging Systems
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1999, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HI5728
Pinout
2
QD7
DVDD
QD9 (MSB)
QD8
QCLK
DGND
ICLK
ID9 (MSB)
DVDD
DGND
REFIO
QD6
QD5
QD4
QD3
QD2
QD1
QD0 (LSB)
DVDD
DGND
NC
AVDD
AGND
QCOMP1
QOUTA
FSADJ
AGND
QOUTB
AGND
IOUTB
IOUTA
REFLO
AGND
SLEEP
DVDD
DGND
NC
AVDD
48 47 46 45 44 43 42 41 40 39 38 37
36
35
2
34
3
33
4
32
5
31
6
30
7
29
8
28
9
27
10
26
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
1
ICOMP1
ID6
ID5
ID4
ID3
ID2
ID1
ID0 (LSB)
ID8
ID7
HI5728
(48 LD LQFP)
TOP VIEW
FN4321.5
January 22, 2010
HI5728
Functional Block Diagram
IOUTA
IOUTB
(LSB) ID0
CASCODE
CURRENT
SOURCE
ID1
ID2
ID3
ID4
LATCH
LATCH
36
SWITCH
MATRIX
36
5 LSBs
+
31 MSB
SEGMENTS
ID5
ID6
UPPER
5-BIT
ID7
31
DECODER
ID8
(MSB) ID9
ICLK
ICOMP1
INT/EXT
VOLTAGE
REFERENCE
INT/EXT
REFERENCE
SELECT
BIAS
GENERATION
REFLO
REFIO
FSADJ
SLEEP
QCOMP1
(LSB) QD0
CASCODE
CURRENT
SOURCE
QD1
QD2
QD3
QD4
LATCH
LATCH
36
SWITCH
MATRIX
QD5
36
5 LSBs
+
31 MSB
SEGMENTS
QD6
UPPER
5-BIT
QD7
31
DECODER
QD8
QCLK
AVDD
AGND
DVDD
3
DGND
QOUTA QOUTB
FN4321.5
January 22, 2010
HI5728
Typical Applications Circuit
ICLK/QCLK
DIGITAL
GROUND
PLANE
50
DVDD
DVDD
0.1µF
QD9 (MSB)
QD8
QD7
ID7
ID8
ID9 (MSB)
48 47 46 45 44 43 42 41 40 39 38 37
36
1
35
2
34
3
33
4
32
5
31
6
30
7
DVDD 29
8
DGND 28
9 DVDD
NC (GROUND) 27
10 DGND
AVDD 26
11 NC (GROUND)
25
12
13 14 15 16 17 18 19 20 21 22 23 24
ID6
ID5
ID4
ID3
ID2
ID1
ID0 (LSB)
SLEEP
ANALOG
GROUND
PLANE
0.1µF
DVDD
0.1µF
AGND
DVDD
QD6
QD5
QD4
QD3
QD2
QD1
QD0 (LSB)
0.1µF
AVDD
0.1µF
AGND
AVDD
0.1µF
AGND
QCOMP1
REFIO
ICOMP1
AVDD
RSET
2k
0.1µF
+5V OR +3V SUPPLY
+
IOUTB
QOUTB
10µH
0.1µF
4
NOTE: ICOMP1 AND QCOMP1
PINS (24, 14) MUST BE TIED
TOGETHER EXTERNALLY
QOUTA
FERRITE
BEAD
10µF
AVDD
50 50
50 50
IOUTA
0.1µF
0.1µF
FERRITE
BEAD
DVDD (POWER PLANE)
AVDD (POWER PLANE)
10µH
0.1µF
+5V OR +3V SUPPLY
+
10µF
FN4321.5
January 22, 2010
HI5728
Pin Descriptions
PIN NO.
39, 38, 37, 36,
35, 34, 33, 32,
31, 30
PIN NAME
PIN DESCRIPTION
QD9 (MSB) Through Digital Data Bit 9, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the Q
QD0 (LSB)
channel.
1, 2, 3, 4, 5, 6, 7,
46, 47, 48
ID9 (MSB) Through
ID0 (LSB)
Digital Data Bit 9, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the I
channel.
8
SLEEP
Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep
pin has internal 20µA active pull-down current.
15
REFLO
Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable.
23
REFIO
Reference voltage input if internal reference is disabled and reference voltage output if internal reference is
enabled. Use 0.1µF cap to ground when internal reference is enabled.
22
FSADJ
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output
Current Per Channel = 32 x IFSADJ .
14, 24
ICOMP1, QCOMP1
Reduces noise. Connect each to AVDD with 0.1µF capacitor near each pin. The ICOMP1 and QCOMP1
pins MUST be tied together externally.
13, 18, 19, 25
AGND
Analog Ground Connections.
17
IOUTB
The complimentary current output of the I channel. Bits set to all 0s gives full scale current.
16
IOUTA
Current output of the I channel. Bits set to all 1s gives full scale current.
20
QOUTB
The complimentary current output of the Q channel. Bits set to all 0s gives full scale current.
21
QOUTA
Current output of the Q channel. Bits set to all 1s gives full scale current.
11, 27
NC
12, 26
AVDD
Analog Supply (+2.7V to +5.5V).
10, 28, 41, 44
DGND
Digital Ground.
9, 29, 40, 45
DVDD
Supply voltage for digital circuitry (+2.7V to +5.5V).
43
ICLK
Clock input for I channel. Positive edge of clock latches data.
42
QCLK
Clock input for Q channel. Positive edge of clock latches data.
No Connect. Recommended: connect to ground.
5
FN4321.5
January 22, 2010
HI5728
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage DVDD to DCOM . . . . . . . . . . . . . . . . . +5.5V
Analog Supply Voltage AVDD to ACOM. . . . . . . . . . . . . . . . . . +5.5V
Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (D9-D0, CLK, SLEEP). . . . . . . . . DVDD +0.3V
Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . . 50µA
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AVDD +0.3V
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Thermal Resistance (Typical, Note 1)
Operating Conditions
JA(°C/W)
48 Ld TQFP Package. . . . . . . . . . . . . . . . . . . . . . . .
55
Maximum Power Dissipation
48 Ld TQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .930mW
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = +25°C for All Typical Values. Data given is
per channel except for “POWER SUPPLY CHARACTERISTICS” on page 8
HI5728IN
TA = -40°C TO +85°C
PARAMETER
TEST CONDITIONS
MIN
(Note 11)
TYP
MAX
(Note 11)
UNITS
10
-
-
Bits
SYSTEM PERFORMANCE (Per Channel)
Resolution
Integral Linearity Error, INL
“Best Fit” Straight Line (Note 7)
-1
0.5
+1
LSB
Differential Linearity Error, DNL
(Note 7)
-0.5
0.25
+0.5
LSB
Offset Error, IOS
(Note 7)
-0.025
+0.025
% FSR
Offset Drift Coefficient
(Note 7)
-
0.1
-
ppm FSR/°C
Full Scale Gain Error, FSE
With External Reference (Notes 2, 7)
-10
2
+10
% FSR
With Internal Reference (Notes 2, 7)
-10
1
+10
% FSR
-
50
-
ppm FSR/°C
Full Scale Gain Drift
With External Reference (Note 7)
With Internal Reference (Note 7)
Gain Matching Between Channels
I/Q Channel Isolation
FOUT = 10MHz
Output Voltage Compliance Range
(Note 3)
Full Scale Output Current, IFS
-
100
-
ppm FSR/°C
-0.5
0.1
0.5
dB
-
80
-
dB
-0.3
-
1.25
V
2
-
20
mA
DYNAMIC CHARACTERISTICS (Per Channel)
Maximum Clock Rate, fCLK
(Note 3)
125
-
-
MHz
Output Settling Time, (tSETT)
0.1% (1 LSB, equivalent to 9 Bits) (Note 7)
-
20
-
ns
0.05% (1/2 LSB, equivalent to 10 Bits) (Note 7)
-
35
-
ns
Singlet Glitch Area (Peak Glitch)
RL = 25(Note 7)
-
35
-
pV•s
Output Rise Time
Full Scale Step
-
1.5
-
ns
Output Fall Time
Full Scale Step
-
1.5
-
ns
-
10
-
pF
IOUTFS = 20mA
-
50
-
pA/Hz
IOUTFS = 2mA
-
30
-
pA/Hz
Output Capacitance
Output Noise
6
FN4321.5
January 22, 2010
HI5728
Electrical Specifications
AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = +25°C for All Typical Values. Data given is
per channel except for “POWER SUPPLY CHARACTERISTICS” on page 8 (Continued)
HI5728IN
TA = -40°C TO +85°C
PARAMETER
TEST CONDITIONS
MIN
(Note 11)
TYP
MAX
(Note 11)
UNITS
-
75
-
dBc
AC CHARACTERISTICS (Per Channel) - HI5728IN - 125MHz
Spurious Free Dynamic Range,
SFDR Within a Window
fCLK = 125MSPS, fOUT = 32.9MHz, 10MHz Span (Notes 4, 7)
Total Harmonic Distortion (THD) to
Nyquist
Spurious Free Dynamic Range,
SFDR to Nyquist
fCLK = 100MSPS, fOUT = 5.04MHz, 4MHz Span (Notes 4, 7)
-
76
-
dBc
fCLK = 60MSPS, fOUT = 10.1MHz, 10MHz Span (Notes 4, 7)
-
75
-
dBc
fCLK = 50MSPS, fOUT = 5.02MHz, 2MHz Span (Notes 4, 7)
-
76
-
dBc
fCLK = 50MSPS, fOUT = 1.00MHz, 2MHz Span (Notes 4, 7)
-
78
-
dBc
dBc
fCLK = 100MSPS, fOUT = 2.00MHz (Notes 4, 7)
-
71
-
fCLK = 50MSPS, fOUT = 2.00MHz (Notes 4, 7)
-
71
-
dBc
fCLK = 50MSPS, fOUT = 1.00MHz (Notes 4, 7)
-
76
-
dBc
fCLK = 125MSPS, fOUT = 32.9MHz, 62.5MHz Span (Notes 4, 7)
-
54
-
dBc
fCLK = 125MSPS, fOUT = 10.1MHz, 62.5MHz Span (Notes 4, 7)
-
64
-
dBc
fCLK = 100MSPS, fOUT = 40.4MHz, 50MHz Span (Notes 4, 7)
-
52
-
dBc
fCLK = 100MSPS, fOUT = 20.2MHz, 50MHz Span (Notes 4, 7)
-
60
-
dBc
fCLK = 100MSPS, fOUT = 5.04MHz, 50MHz Span (Notes 4, 7)
-
68
-
dBc
fCLK = 100MSPS, fOUT = 2.51MHz, 50MHz Span (Notes 4, 7)
-
74
-
dBc
fCLK = 60MSPS, fOUT = 10.1MHz, 30MHz Span (Notes 4, 7)
-
63
-
dBc
fCLK = 50MSPS, fOUT = 20.2MHz, 25MHz Span (Notes 4, 7)
-
55
-
dBc
fCLK = 50MSPS, fOUT = 5.02MHz, 25MHz Span (Notes 4, 7)
-
68
-
dBc
fCLK = 50MSPS, fOUT = 2.51MHz, 25MHz Span (Notes 4, 7)
-
73
-
dBc
fCLK = 50MSPS, fOUT = 1.00MHz, 25MHz Span (Notes 4, 7)
-
73
-
dBc
fCLK = 60MSPS, fOUT = 10.1MHz, 10MHz Span (Notes 4, 7)
-
75
-
dBc
fCLK = 50MSPS, fOUT = 5.02MHz, 2MHz Span (Notes 4, 7)
-
76
-
dBc
fCLK = 50MSPS, fOUT = 1.00MHz, 2MHz Span (Notes 4, 7)
-
78
-
dBc
AC CHARACTERISTICS (Per Channel) - HI5728/6IN - 60MHz
Spurious Free Dynamic Range,
SFDR Within a Window
Total Harmonic Distortion (THD) to
Nyquist
Spurious Free Dynamic Range,
SFDR to Nyquist
fCLK = 50MSPS, fOUT = 2.00MHz (Notes 4, 7)
-
71
-
dBc
fCLK = 50MSPS, fOUT = 1.00MHz (Notes 4, 7)
-
76
-
dBc
fCLK = 60MSPS, fOUT = 20.2MHz, 30MHz Span (Notes 4, 7)
-
56
-
dBc
fCLK = 60MSPS, fOUT = 10.1MHz, 30MHz Span (Notes 4, 7)
-
63
-
dBc
fCLK = 50MSPS, fOUT = 20.2MHz, 25MHz Span (Notes 4, 7)
-
55
-
dBc
fCLK = 50MSPS, fOUT = 5.02MHz, 25MHz Span (Notes 4, 7)
-
68
-
dBc
fCLK = 50MSPS, fOUT = 2.51MHz, 25MHz Span (Notes 4, 7)
-
73
-
dBc
fCLK = 50MSPS, fOUT = 1.00MHz, 25MHz Span (Notes 4, 7)
-
73
-
dBc
fCLK = 25MSPS, fOUT = 5.02MHz, 25MHz Span (Notes 4, 7)
-
71
-
dBc
1.04
1.16
1.28
V
Internal Reference Voltage Drift
-
60
-
ppm/°C
Internal Reference Output Current
Sink/Source Capability
-
0.1
-
µA
VOLTAGE REFERENCE
Internal Reference Voltage, VFSADJ
Voltage at Pin 22 with Internal Reference
Reference Input Impedance
Reference Input Multiplying
Bandwidth
DIGITAL INPUTS
(Note 7)
-
1
-
M
-
1.4
-
MHz
3.5
5
-
V
D9-D0, CLK (Per Channel)
Input Logic High Voltage with
5V Supply, VIH
(Note 3)
7
FN4321.5
January 22, 2010
HI5728
Electrical Specifications
AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = +25°C for All Typical Values. Data given is
per channel except for “POWER SUPPLY CHARACTERISTICS” on page 8 (Continued)
HI5728IN
TA = -40°C TO +85°C
PARAMETER
TEST CONDITIONS
MIN
(Note 11)
TYP
MAX
(Note 11)
UNITS
Input Logic High Voltage with
3V Supply, VIH
(Note 3)
2.1
3
-
V
Input Logic Low Voltage with
5V Supply, VIL
(Note 3)
-
0
1.3
V
Input Logic Low Voltage with
3V Supply, VIL
(Note 3)
-
0
0.9
V
Input Logic Current, IIH
-10
-
+10
µA
Input Logic Current, IIL
-10
-
+10
µA
-
5
-
pF
-
-
ns
Digital Input Capacitance, CIN
TIMING CHARACTERISTICS (Per Channel)
Data Setup Time, tSU
See Figure 41 (Note 3)
3
Data Hold Time, tHLD
See Figure 41 (Note 3)
3
-
-
ns
Propagation Delay Time, tPD
See Figure 41
-
1
-
ns
CLK Pulse Width, tPW1 , tPW2
See Figure 41 (Note 3)
4
-
-
ns
POWER SUPPLY CHARACTERISTICS
AVDD Power Supply
(Notes 8, 9)
2.7
5.0
5.5
V
DVDD Power Supply
(Notes 8, 9)
2.7
5.0
5.5
V
Analog Supply Current (IAVDD)
(5V or 3V, IOUTFS = 20mA)
-
46
60
mA
(5V or 3V, IOUTFS = 2mA)
-
8
-
mA
mA
Digital Supply Current (IDVDD)
(5V, IOUTFS = Don’t Care) (Note 5)
-
6
10
(3V, IOUTFS = Don’t Care) (Note 5)
-
3
-
mA
Supply Current (IAVDD) Sleep Mode
(5V or 3V, IOUTFS = Don’t Care)
-
3.2
6
mA
Power Dissipation
(5V, IOUTFS = 20mA) (Note 6)
-
330
-
mW
(5V, IOUTFS = 2mA) (Note 6)
-
140
-
mW
(3V, IOUTFS = 20mA) (Note 6)
-
170
-
mW
(3V, IOUTFS = 2mA) (Note 6)
-
54
-
mW
(5V, IOUTFS = 20mA) (Note 10)
-
300
-
mW
(3.3V, IOUTFS = 20mA) (Note 10)
-
150
-
mW
-
135
-
mW
-0.2
-
+0.2
% FSR/V
(3V, IOUTFS = 20mA) (Note 10)
Power Supply Rejection
Single Supply (Note 7)
NOTES:
2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 625A). Ideally the ratio
should be 32.
3. Limits established by characterization and are not production tested.
4. Spectral measurements made with differential coupled transformer and 100% amplitude.
5. Measured with the clock at 50MSPS and the output frequency at 1MHz, both channels.
6. Measured with the clock at 100MSPS and the output frequency at 40MHz, both channels.
7. See “Definition of Specifications” on page 16.
8. For operation below 3V, it is recommended that the output current be reduced to 12mA or less to maintain optimum performance. DVDD and AVDD
do not have to be equal.
9. For operation above 125MHz, it is recommended that the power supply be 3.3V or greater. The part is functional with the clock above 125MSPS
and the power supply below 3.3V, but performance is degraded.
10. Measured with the clock at 60MSPS and the output frequency at 10MHz, both channels.
11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
8
FN4321.5
January 22, 2010
HI5728
Typical Performance Curves, 5V Power Supply
80
76
74
75
-6dBFS
72
-6dBFS
SFDR (dBc)
SFDR (dBc)
70
0dBFS
65
60
70
-12dBFS
68
66
64
-12dBFS
55
0dBFS
62
60
50
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
1
2
2
3
4
5
6
7
8
9
10
40
45
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
FIGURE 1. SFDR vs fOUT, CLOCK = 5MSPS
FIGURE 2. SFDR vs fOUT, CLOCK = 25MSPS
80
75
0dBFS
SFDR (dBc)
SFDR (dBc)
-6dBFS
70
65
-12dBFS
65
-12dBFS
60
55
60
55
-6dBFS
70
75
0dBFS
50
0
2
4
6
8
10
12
14
16
18
45
20
0
5
10
15
20
25
30
35
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
FIGURE 3. SFDR vs fOUT, CLOCK = 50MSPS
FIGURE 4. SFDR vs fOUT, CLOCK = 100MSPS
75
80
70
75
25MSPS
6dBFS
-12dBFS
60
SFDR (dBc)
65
SFDR (dBc)
50MSPS
70
55
100MSPS
65
125MSPS
60
55
0dBFS
50
50
45
0
5
10
15
20
25
30
35
40
45
OUTPUT FREQUENCY (MHz)
FIGURE 5. SFDR vs fOUT, CLOCK = 125MSPS
9
50
45
-25
-20
-15
-10
-5
0
AMPLITUDE (dBFS)
FIGURE 6. SFDR vs AMPLITUDE, fCLK / fOUT = 10
FN4321.5
January 22, 2010
HI5728
Typical Performance Curves, 5V Power Supply
(Continued)
75
80
25MSPS
75
50MSPS
65
65
SFDR (dBc)
SFDR (dBc)
70
100MSPS
60
125MSPS
55
60
125MSPS
(16.9/18.1MHz)
45
40
-25
-20
-15
-10
-5
40
-25
0
AMPLITUDE (dBFS)
-20
-15
-10
-5
0
AMPLITUDE (TOTAL PEAK POWER OF COMBINED TONES) (dBFS)
FIGURE 7. SFDR vs AMPLITUDE, fCLK / fOUT = 5
FIGURE 8. SFDR vs AMPLITUDE OF TWO TONES, fCLK / fOUT = 7
75
75
2.5MHz
70
70
-6dBFS DIFF
10MHz
65
0dBFS DIFF
65
60
SFDR (dBc)
SFDR (dBc)
100MSPS
(13.5/14.5MHz)
50
45
20MHz
55
40MHz
50
60
55
-6dBFS SINGLE
50
45
0dBFS SINGLE
2
4
6
8
10
12
IOUT (mA)
14
16
18
45
20
10
15
20
25
30
35
40
-10
-10
2.5MHz
-20
-20
-30
-30
70
10.1MHz
-40
-40
AMP(dB)
(dB)
Amp
65
60
55
-50
-50
fCLK = 100MSPS
= f100MSPS
=9.95MHz
Fout = OUT
9.95MHz
AMPLITUDE = 0dBFS
Amplitude = 0dBFS
SFDR = 64dBc
SFDR = 64dBc
14dB 14dB
EXTERNAL
ATTENUATION
ExternalANALYZER
Analyzer Attenuation
-60
-60
-70
-70
-80
-80
50
-90
-90
40.4MHz
45
40
-40
5
FIGURE 10. DIFFERENTIAL vs SINGLE-ENDED,
CLOCK = 100MSPS
80
75
0
OUTPUT FREQUENCY (MHz)
FIGURE 9. SFDR vs IOUT, CLOCK = 100MSPS
SFDR (dBc)
50MSPS
(6.75/7.25MHz)
55
50
40
25MSPS
(3.38/3.63MHz)
70
-20
0
20
40
60
-100
-100
80
TEMPERATURE (°C)
FIGURE 11. SFDR vs TEMPERATURE, CLOCK = 100MSPS
10
-110
-110
00
5MHz/DIV.
5MHz/DIV.
Frequency (MHz)
FREQUENCY
(MHz)
50
FIGURE 12. SINGLE TONE SFDR
FN4321.5
January 22, 2010
HI5728
Typical Performance Curves, 5V Power Supply
(Continued)
-10
-20
-20
Fclk
= 100MSPS
fCLK
= 100MSPS
Fout
= 13.5/14.5MHz
= 13.5/14.5MHZ
fOUT
Combined PeakCOMBINED
Amplitude =PEAK
0dBFS
MTPR==0dBFS
62.9dBc
AMPLITUDE
14dB External Analyzer
Attenuation
SFDR =
62.9dBc
14dB EXTERNAL
ANALYZER ATTENUATION
-40
-40
AMP(dB)
(dB)
Amp
-50
-50
-60
-60
-30
-40
-70
-70
-80
-80
-50
-60
-70
-90
-90
-80
-100
-100
-110
-110
-90
00
5MHz/DIV.
5MHz/DIV.
Frequency (MHz)
FREQUENCY
(MHz)
50
-100
0.5
FIGURE 13. TWO TONE, CLOCK = 100MSPS
-10
fCLK = 100MSPS
fOUT = 2.6, 3.2, 3.8, 4.4, 5.6, 6.2, 6.8MHZ
COMBINED PEAK AMPLITUDE = 0dBFS
SFDR = 67dBc (IN A WINDOW)
-30
-40
-30
-40
-60
-70
-50
-60
-80
-70
-90
-80
-100
-90
-110
0.5
1.95MHz/DIV.
FREQUENCY (MHz)
fCLK = 50MSPS
fOUT = 1.9, 2.2, 2.8, 3.1MHZ
COMBINED PEAK
AMPLITUDE = 0dBFS
SFDR = 73.6dBc
(IN A WINDOW)
-20
AMP (dB)
-50
AMP (dB)
15
1.45MHz / DIV.
FIGURE 14. FOUR-TONE, CLOCK = 100MSPS
-20
-100
0.5
20
950kHz/DIV.
10
FREQUENCY (MHz)
FIGURE 15. EIGHT-TONE, CLOCK = 100MSPS
FIGURE 16. FOUR-TONE, CLOCK = 50MSPS
0.4
0.4
0.2
0.2
LSB
LSB
fCLK = 100MSPS
fOUT = 3.8, 4.4, 5.6, 6.2MHz
COMBINED PEAK
AMPLITUDE = 0dBFS
SFDR = 71.4dBc
(IN A WINDOW)
-20
AMP (dB)
-30
-30
0
0
-0.2
-0.2
-0.4
-0.4
0
200
400
600
800
CODE
FIGURE 17. DIFFERENTIAL NONLINEARITY
11
1000
0
200
400
600
800
1000
CODE
FIGURE 18. INTEGRAL NONLINEARITY
FN4321.5
January 22, 2010
HI5728
Typical Performance Curves, 5V Power Supply
(Continued)
320
310
300
POWER (mW)
290
280
270
260
250
240
230
220
210
0
20
40
60
80
100
120
CLOCK RATE (MSPS)
FIGURE 19. POWER vs CLOCK RATE, fCLK / fOUT = 10, IOUT = 20mA
Typical Performance Curves, 3V Power Supply
80
80
0dBFS
-6dBFS
75
-6dBFS
70
0dBFS
SFDR (dBc)
SFDR (dBc)
75
65
60
70
-12dBFS
65
-12dBFS
55
60
50
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
1
2
2
3
OUTPUT FREQUENCY (MHz)
4
5
6
7
8
9
10
OUTPUT FREQUENCY (MHz)
FIGURE 20. SFDR vs fOUT, CLOCK = 5MSPS
FIGURE 21. SFDR vs fOUT, CLOCK = 25MSPS
80
80
75
75
0dBFS
SFDR (dBc)
SFDR (dBc)
70
-6dBFS
70
-12dBFS
65
60
0dBFS
65
-12dBFS
60
55
55
50
-6dBFS
50
0
2
4
6
8
10
12
14
16
18
OUTPUT FREQUENCY (MHz)
FIGURE 22. SFDR vs fOUT, CLOCK = 50MSPS
12
20
45
0
5
10
15
20
25
30
35
40
45
OUTPUT FREQUENCY (MHz)
FIGURE 23. SFDR vs fOUT, CLOCK = 100MSPS
FN4321.5
January 22, 2010
HI5728
Typical Performance Curves, 3V Power Supply
(Continued)
80
80
75
75
70
70
65
SFDR (dBc)
SFDR (dBc)
0dBFS
-6dBFS
60
-12dBFS
100MSPS
125MSPS
60
55
50
50
0
5
10
15
20
25
30
35
40
45
50MSPS
65
55
45
25MSPS
45
-25
50
-20
-15
FIGURE 24. SFDR vs fOUT, CLOCK = 125MSPS
-5
0
FIGURE 25. SFDR vs AMPLITUDE, fCLK / fOUT = 10
75
80
25MSPS
70
75
70
25MSPS
(3.38/3.63MHz)
65
50MSPS
65
60
100MSPS
5MSPS
55
50
2
SFDR (dBc)
SFDR (dBc)
-10
AMPLITUDE (dBFS)
OUTPUT FREQUENCY (MHz)
ND
5A
50
PS
MS
125MSPS
60
50MSPS
(6.75/7.25MHz)
55
100MSPS
(13.5/14.5MHz)
50
125MSPS
(16.9/18.1MHz)
45
45
40
-25
-20
-15
-10
-5
40
-25
0
-20
-15
AMPLITUDE (dBFS)
-10
-5
0
AMPLITUDE (dBFS)
FIGURE 26. SFDR vs AMPLITUDE, fCLK / fOUT = 5
FIGURE 27. SFDR vs AMPLITUDE OF TWO TONES, fCLK/fOUT = 7
80
80
75
75
70
70
65
10MHz
60
20MHz
SFDR (dBc)
SFDR (dBc)
2.5MHz
0dBFS DIFF
65
-6dBFS SINGLE
60
-6dBFS DIFF
55
55
40MHz
50
50
0dBFS SINGLE
45
2
4
6
8
10
12
14
16
18
IOUT (mA)
FIGURE 28. SFDR vs IOUT, CLOCK = 100MSPS
13
20
45
0
5
10
15
20
25
30
35
40
OUTPUT FREQUENCY (MHz)
FIGURE 29. DIFFERENTIAL vs SINGLE-ENDED,
CLOCK = 100MSPS
FN4321.5
January 22, 2010
HI5728
Typical Performance Curves, 3V Power Supply
(Continued)
80
-10
-30
70
10.1MHz
-40
65
AMP (dB)
SFDR (dBc)
fCLK = 100MSPS
fOUT = 9.95MHz
AMPLITUDE = 0dBFS
SFDR = 63dBc
14dB EXTERNAL
ANALYZER ATTENUATION
-20
2.5MHz
75
60
55
-50
-60
-70
-80
50
40.4MHz
-90
45
-100
40
-40
-20
0
20
40
60
-110
80
0
5MHz/DIV.
TEMPERATURE (oC)
FIGURE 30. SFDR vs TEMPERATURE, CLOCK = 100MSPS
FIGURE 31. SINGLE TONE SFDR
-10
-20
fCLK = 100MSPS
fOUT = 13.5/14.5MHz
COMBINED PEAK
AMPLITUDE = 0dBFS
SFDR = 61.5dBc
14dB EXTERNAL
ANALYZER ATTENUATION
-40
AMP (dB)
-50
-60
-30
-40
-70
-50
-60
-80
-70
-90
-80
-100
-90
0
5MHz/DIV.
fCLK = 100MSPS
fOUT = 3.8, 4.4, 5.6, 6.2MHz
COMBINED PEAK
AMPLITUDE = 0dBFS
SFDR = 70.6dBc
(IN A WINDOW)
-20
AMP (dB)
-30
-110
-100
0.5
50
FREQUENCY (MHz)
1.45MHz/DIV.
15
FREQUENCY (MHz)
FIGURE 32. TWO-TONE, CLOCK = 100MSPS
FIGURE 33. FOUR-TONE, CLOCK = 100MSPS
-20
-10
fCLK = 100MSPS
fOUT = 2.6, 3.2, 3.8, 4.4,
5.6, 6.2, 6.8MHz
COMBINED PEAK
AMPLITUDE = 0dBFS
SFDR = 67.4dBc
(IN A WINDOW)
-40
-50
-60
-30
-40
-70
-50
-60
-80
-70
-90
-80
-100
-90
-110
0.5
1.95MHz/DIV.
FREQUENCY (MHz)
FIGURE 34. EIGHT-TONE, CLOCK = 100MSPS
14
fCLK = 50MSPS
fOUT = 1.9, 2.2, 2.8, 3.1MHz
COMBINED PEAK
AMPLITUDE = 0dBFS
SFDR = 74.2dBc
(IN A WINDOW)
-20
AMP (dB)
-30
AMP (dB)
50
FREQUENCY (MHz)
20
-100
0
950kHz/DIV.
FREQUENCY (MHz)
10
FIGURE 35. FOUR-TONE, CLOCK = 50MSPS
FN4321.5
January 22, 2010
HI5728
(Continued)
0.4
0.2
0.2
LSB
0.4
0
0
-0.2
-0.2
-0.4
-0.4
0
200
400
600
800
1000
0
200
400
CODE
600
800
1000
CODE
FIGURE 36. DIFFERENTIAL NONLINEARITY
FIGURE 37. INTEGRAL NONLINEARITY
152
148
144
POWER (mW)
LSB
Typical Performance Curves, 3V Power Supply
140
136
132
128
124
120
0
20
40
60
80
100
120
CLOCK RATE (MSPS)
FIGURE 38. POWER vs CLOCK RATE, fCLK / fOUT = 10, IOUT = 20mA
15
FN4321.5
January 22, 2010
HI5728
Timing Diagrams
50%
CLK
D9-D0
GLITCH AREA = 1/2 (H x W)
V
HEIGHT (H)
1 LSB ERROR BAND
IOUT
t(ps)
WIDTH (W)
tSETT
tPD
FIGURE 40. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
FIGURE 39. OUTPUT SETTLING TIME DIAGRAM
tPW1
tPW2
50%
CLK
tSU
tSU
tHLD
tSU
tHLD
tHLD
D9-D0
tPD
tSETT
IOUT
tPD
tSETT
tPD
tSETT
FIGURE 41. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
Definition of Specifications
Integral Linearity Error, INL, is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Differential Linearity Error, DNL, is the measure of the
step size output deviation from code to code. Ideally the step
size should be 1 LSB. A DNL specification of 1 LSB or less
guarantees monotonicity.
Output Settling Time, is the time required for the output
voltage to settle to within a specified error band measured
from the beginning of the output transition. The
16
measurement was done by switching from code 0 to 256, or
quarter scale. Termination impedance was 25 due to the
parallel resistance of the output 50 and the oscilloscope’s
50 input. This also aids the ability to resolve the specified
error band without overdriving the oscilloscope.
Singlet Glitch Area, is the switching transient appearing on
the output during a code transition. It is measured as the
area under the overshoot portion of the curve and is
expressed as a Volt-Time specification. This is tested under
the same conditions as “Output Settling Time, (tSETT)” on
page 6
FN4321.5
January 22, 2010
HI5728
Full Scale Gain Error, is the error from an ideal ratio of 32
between the output current and the full scale adjust current
(through RSET).
Full Scale Gain Drift, is measured by setting the data inputs to
all ones and measuring the output voltage through a known
resistance as the temperature is varied from TMIN to TMAX. It is
defined as the maximum deviation from the value measured at
room temperature to the value measured at either TMIN or
TMAX. The units are ppm of FSR (full scale range) per °C.
Total Harmonic Distortion, THD, is the ratio of the DAC output
fundamental to the RMS sum of the first five harmonics.
Spurious Free Dynamic Range, SFDR, is the amplitude
difference from the fundamental to the largest harmonically or
non-harmonically related spur within the specified window.
Output Voltage Compliance Range, is the voltage limit
imposed on the output. The output impedance load should
be chosen such that the voltage developed does not violate
the compliance range.
Offset Error, is measured by setting the data inputs to all
zeros and measuring the output voltage through a known
resistance. Offset error is defined as the maximum deviation
of the output current from a value of 0mA.
Offset Drift, is measured by setting the data inputs to all zeros
and measuring the output voltage through a known resistance
as the temperature is varied from TMIN to TMAX. It is defined as
the maximum deviation from the value measured at room
temperature to the value measured at either TMIN or TMAX.
The units are ppm of FSR (Full Scale Range) per °C.
Power Supply Rejection, is measured using a single power
supply. Its nominal +5V is varied 10% and the change in the
DAC full scale output is noted.
Reference Input Multiplying Bandwidth, is defined as the
3dB bandwidth of the voltage reference input. It is measured
by using a sinusoidal waveform as the external reference
with the digital inputs set to all 1s. The frequency is
increased until the amplitude of the output waveform is
0.707 of its original value.
Internal Reference Voltage Drift, is defined as the
maximum deviation from the value measured at room
temperature to the value measured at either TMIN or TMAX .
The units are ppm per °C.
Detailed Description
The HI5728 is a dual, 10-bit, current out, CMOS, digital to
analog converter. Its maximum update rate is 125MSPS and
can be powered by either single or dual power supplies in
the recommended range of +3V to +5V. It consumes less
than 330mW of power when using a +5V supply with the
data switching at 100MSPS. The architecture is based on a
segmented current source arrangement that reduces glitch
by reducing the amount of current switching at any one time.
17
The five MSBs are represented by 31 major current sources
of equivalent current. The five LSBs are comprised of binary
weighted current sources. Consider an input waveform to
the converter which is ramped through all the codes from 0
to 1023. The five LSB current sources would begin to count
up. When they reached the all high state (decimal value of
31) and needed to count to the next code, they would all turn
off and the first major current source would turn on. To
continue counting upward, the 5 LSBs would count up
another 31 codes, and then the next major current source
would turn on and the five LSBs would all turn off. The
process of the single, equivalent, major current source
turning on and the five LSBs turning off each time the
converter reaches another 31 codes greatly reduces the
glitch at any one switching point. In previous architectures
that contained all binary weighted current sources or a
binary weighted resistor ladder, the converter might have a
substantially larger amount of current turning on and off at
certain, worst-case transition points such as mid-scale and
quarter scale transitions. By greatly reducing the amount of
current switching at certain ‘major’ transitions, the overall
glitch of the converter is dramatically reduced, improving
settling times and transient problems.
Digital Inputs And Termination
The HI5728 digital inputs are guaranteed to CMOS levels.
However, TTL compatibility can be achieved by lowering the
supply voltage to 3V due to the digital threshold of the input
buffer being approximately half of the supply voltage. The
internal register is updated on the rising edge of the clock. To
minimize reflections, proper termination should be
implemented. If the lines driving the clock(s) and digital
inputs are 50 lines, then 50 termination resistors should
be placed as close to the converter inputs as possible.
Ground Plane(s)
If separate digital and analog ground planes are used, then all
of the digital functions of the device and their corresponding
components should be over the digital ground plane and
terminated to the digital ground plane. The same is true for the
analog components and the analog ground plane. Refer to the
Application Note on the HI5728 Evaluation Board for further
discussion of the ground plane(s) upon availability.
Noise Reduction
To minimize power supply noise, 0.1µF capacitors should be
placed as close as possible to the converter’s power supply
pins, AVDD and DVDD. Also, should the layout be designed
using separate digital and analog ground planes, these
capacitors should be terminated to the digital ground for
DVDD and to the analog ground for AVDD . Additional filtering
of the power supplies on the board is recommended. See
the Application Note on the HI5728 Evaluation Board for
more information upon availability.
FN4321.5
January 22, 2010
HI5728
Voltage Reference
The internal voltage reference of the device has a nominal
value of +1.2V with a 60 ppm/°C drift coefficient over the full
temperature range of the converter. It is recommended that a
0.1F capacitor be placed as close as possible to the REFIO
pin, connected to the analog ground. The REFLO pin (15)
selects the reference. The internal reference can be selected if
pin 15 is tied low (ground). If an external reference is desired,
then pin 15 should be tied high (to the analog supply voltage)
and the external reference driven into REFIO, pin 23. The full
scale output current of the converter is a function of the voltage
reference used and the value of RSET. IOUT should be within
the 2mA to 20mA range, through operation below 2mA is
possible, with performance degradation.
If the internal reference is used, VFSADJ will equal
approximately 1.16V (pin 22). If an external reference is used,
VFSADJ will equal the external reference. The calculation for
IOUT(Full Scale) is:
I OUT  Full Scale  = V FSADJ  R SET  32
(EQ. 1)
If the full scale output current is set to 20mA by using the
internal voltage reference (1.16V) and a 1.86k RSET
resistor, then the input coding to output current will resemble
the following:
and 17 will be biased at zero volts. It is important to note
here that the negative voltage output compliance range limit
is -300mV, imposing a maximum of 600mVP-P amplitude
with this configuration. The loading as shown in Figure 1 will
result in a 500mV signal at the output of the transformer if
the full scale output current of the DAC is set to 20mA.
50
PIN 17 (20)
100
PIN 16 (21)
VOUT = (2 x IOUT x REQ)V
IOUTB (QOUTB)
IOUTA (QOUTA)
50
50
FIGURE 42.
VOUT = 2 x IOUT x REQ ,where REQ is ~12.5.
Allowing the center tap to float will result in identical
transformer output, however the output pins of the DAC will
have positive DC offset. The 50 load on the output of the
transformer represents the spectrum analyzer’s input
impedance.
TABLE 1. INPUT CODING vs OUTPUT CURRENT (Per DAC)
INPUT CODE (D9-D0)
IOUTA
(mA)
IOUTB
(mA)
11111 11111
20
0
10000 00000
10
10
00000 00000
0
20
Outputs
IOUTA and IOUTB (or QOUTA and QOUTB) are
complementary current outputs. The sum of the two currents
is always equal to the full scale output current minus one
LSB. If single ended use is desired, a load resistor can be
used to convert the output current to a voltage. It is
recommended that the unused output be either grounded or
equally terminated. The voltage developed at the output
must not violate the output voltage compliance range of
-0.3V to 1.25V. RLOAD should be chosen so that the desired
output voltage is produced in conjunction with the output full
scale current, which is described above in the ‘Reference’
section. If a known line impedance is to be driven, then the
output load resistor should be chosen to match this
impedance. The output voltage equation is:
V OUT = I OUT  R LOAD
(EQ. 2)
These outputs can be used in a differential-to-single-ended
arrangement to achieve better harmonic rejection. The
SFDR measurements in this data sheet were performed with
a 1:1 transformer on the output of the DAC (see Figure 1).
With the center tap grounded, the output swing of pins 16
18
FN4321.5
January 22, 2010
HI5728
Thin Plastic Quad Flatpack Packages (LQFP)
Q48.7x7A (JEDEC MS-026BBC ISSUE B)
48 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE
D
D1
-D-
INCHES
-A-
-B-
E E1
e
PIN 1
SEATING
A PLANE
-H-
0.08
0.003
-C-
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.062
-
1.60
-
A1
0.002
0.005
0.05
0.15
-
A2
0.054
0.057
1.35
1.45
-
b
0.007
0.010
0.17
0.27
6
b1
0.007
0.009
0.17
0.23
-
D
0.350
0.358
8.90
9.10
3
D1
0.272
0.280
6.90
7.10
4, 5
E
0.350
0.358
8.90
9.10
3
E1
0.272
0.280
6.90
7.10
4, 5
L
0.018
0.029
0.45
0.75
N
48
48
e
0.020 BSC
0.50 BSC
7
Rev. 2 1/99
NOTES:
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
2. All dimensions and tolerances per ANSI Y14.5M-1982.
3. Dimensions D and E to be determined at seating plane -C- .
0.08
0.003 M
D S
C A-B S
b
11o-13o
0.020
0.008 MIN
b1
0o MIN
A2 A1
GAGE
PLANE
0o-7o
0.25
0.010
11o-13o
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
6. Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall not cause the lead width to exceed
the maximum b dimension by more than 0.08mm (0.003
inch).
0.09/0.16
0.004/0.006
BASE METAL
WITH PLATING
L
4. Dimensions D1 and E1 to be determined at datum plane
-H- .
7. “N” is the number of terminal positions.
0.09/0.20
0.004/0.008
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
19
FN4321.5
January 22, 2010
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