DATASHEET

HI2315
TM
10-Bit, 80 MSPS D/A Converter
(Ultra-Low Glitch Version)
August 1997
Features
Description
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . . 80MHz
The HI2315 is a 10-bit, 80MHz, high speed, low power CMOS
D/A converter. The converter incorporates a 10-bit input data
register with current outputs. The HI2315 includes a power
down feature that reduces power consumption and a blanking
control. The on-chip bandgap reference can be used to set the
output current range of the D/A.
• Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150mW
• Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . +5V
• Differential Linearity Error . . . . . . . . . . . . . . . ±0.5 LSB
• TTL/CMOS Compatible Inputs
Ordering Information
• Built in Bandgap Voltage Reference
• Power Down and Blanking Control Pins
PART
NUMBER
• Low Glitch
• Pin Compatible with Sony CXD2306
HI2315JCQ
TEMP.
RANGE ( oC)
-20 to 75
PACKAGE
32 Ld MQFP
PKG. NO.
Q32.7x7-S
• Direct Replacement for Sony CXD2315Q
Applications
• Wireless Communications
• Direct Digital Frequency Synthesis
• Signal Reconstruction
• Test Equipment
• High Resolution Imaging and Graphics Systems
Pinout
NC
AVSS
DVSS
NC
DVDD
D0 (LSB)
D1
D2
HI2315
(MQFP)
TOP VIEW
22
VG
D6
4
21
AVDD
D7
5
20
AVDD
D8
6
19
VREF
D9 (MSB)
7
18
SREF
NC
8
17
9 10 11 12 13 14 15 16
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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10-1
IO
IREF
NC
VB
3
DVSS
IO
D5
DVDD
23
NC
2
CE
D4
BLK
32 31 30 29 28 27 26 25
24
1
CLK
D3
FN4119.1
HI2315
Functional Block Diagram
(LSB) D0
30
D1
31
D2
32
D3
1
D4
2
D5
3
D6
4
D7
5
D8
6
D9
7
DVDD
28
BLK
10
DVDD
13
4 LSBs
CURRENT
CELLS
25 AVSS
VB
14
CE
11
23 IO
6 MSBs
CURRENT
CELLS
22 VG
DECODER
19 VREF
CURRENT CELLS
(FOR FULL SCALE)
-
+
17 IREF
21 AVDD
CLOCK
GENERATOR
DVSS 27
9
LATCHES
DECODER
DVSS 15
CLK
24 IO
BIAS VOLTAGE
GENERATOR
BAND GAP
REFERENCE
20 AVDD
18 SREF
Pin Descriptions
PIN NO.
SYMBOL
30 to 32
1 to 7
D0 to D9
EQUIVALENT CIRCUIT
DESCRIPTION
Digital Input.
DVDD
30
TO
7
DVSS
10
BLK
Blanking pin. No signal (0V output) at high and
output state at low.
DVDD
10
DVSS
14
VB
DVDD
Connect a capacitor of approximately 0.1µF.
DVDD
+
14
-
DVSS
9
CLK
Clock pin.
DVDD
9
DVSS
10-2
HI2315
Pin Descriptions
(Continued)
PIN NO.
SYMBOL
15, 27
DVSS
Digital GND.
25
AVSS
Analog GND.
17
IREF
19
VREF
22
EQUIVALENT CIRCUIT
AVDD
DESCRIPTION
AVDD
Connect resistance “16R” which is 16 times output
resistance “R”.
Sets output full scale value.
17
AVDD
VG
+
-
AVDD
AVSS
19
Connect a capacitor of approximately 0.1µF.
22
AVSS
AVSS
20, 21
AVDD
24
IO
Analog VDD .
Current Output pin. Output can be retrieved by
connecting resistance. The standard is 200Ω.
AVDD
23
IO
Inverted Current Output pin. Connect to GND
normally.
24
AVSS
AVDD
23
AVSS
13, 28
DVDD
11
CE
Digital VDD .
Chip Enable pin. No signal (0V output) at high makes
power consumption minimum.
DVDD
11
DVSS
18
SREF
Independent Constant-Voltage Source Output pin
using band gap reference. Stable voltage
independent of the fluctuation for supply voltage can
be obtained by connecting to VREF. See Application
Circuit 2 for details.
AVDD
18
AVSS
10-3
HI2315
Absolute Maximum Ratings TA = 25oC
Thermal Information
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Input Voltage (VIN) . . . . . . . . . . . . . . . . . . .VSS -0.5V to VDD + 0.5V
Output Voltage (IOUT). . . . . . . . . . . . . . . . . . . . . . . . . .0mA to 15mA
Thermal Resistance (Typical, Note 1)
Operating Conditions
Supply Voltage
AVDD , AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0V ±±0.25V
DVDD , DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.0V ±±0.25V
Reference Input Voltage (VREF). . . . . . . . . . . . . . . . . . .0.5V to 2.0V
Clock Pulse Width (tPW1, tPW0) . . . . . . . . . . . . . . . . . . 6.25ns (Min)
Temperature Range (TOPR) . . . . . . . . . . . . . . . . . . . . -20oC to 75oC
θJA (oC/W)
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
122
Maximum Junction Temperature (MQFP Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(MQFP - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
TA = 25oC, fCLK = 80MHz, VDD = 5V, R = 200Ω, VREF = 2.0V, 16R = 3.3kΩ
PARAMETER
MIN
TYP
MAX
UNITS
n
-
10
-
Bit
fMAX
80
-
-
MHz
Linearity Error
EL
-1.5
-
1.5
LSB
Differential Linearity Error
ED
-0.5
-
0.5
LSB
Output Full-Scale Voltage
VFS
1.8
1.94
2.0
V
Output Full-Scale Current
IFS
9.0
9.7
10
mA
Output Off-Set Voltage
VOS
-
-
1
mV
-
300
-
kΩ
IDD
-
-
30
mA
High Level
IIH
-
-
5
µA
Low Level
IIL
-5
-
-
µA
High Level
VIH
2.45
-
-
V
Low Level
VIL
-
-
0.85
V
VOC
1.8
1.94
2.0
V
Setup Time
tS
3.0
-
-
ns
Hold Time
tH
3.0
-
-
ns
Rise Time
tr
5.0
-
-
ns
Propagation Delay Time
tPD
-
5
-
ns
Glitch Energy
GE
-
-
30
pV/s
Differential Gain
DG
-
-
1.0
%
Differential Phase
DP
-
-
1.0
Degrees
1.0
1.2
1.4
V
Resolution
Maximum Conversion Rate
SYMBOL
TEST CONDITIONS
Output Impedance
Supply Current
Digital Input Current
Digital Input Voltage
Accuracy Guarantee Output Voltage Range
SREF Output Voltage
SREF
ROUT = 200Ω, 2VP-P
TA = 25oC
10-4
HI2315
Test Circuits
30 D0 (LSB)
10-BIT
COUNTER
WITH
LATCH
IO 23
OSCILLOSCOPE
31
0.1µ
7
D9 (MSB) VG 22
9
CLK
VREF 19
10 BLK
CLK
80MHz (MAX)
SQUARE
WAVE
11 CE
AVDD
2V
5K
AVSS
IREF 17
14 VB
200
3.3K
0.1µ
FIGURE 1. MAXIMUM CONVERSION RATE TEST CIRCUIT
30 D0 (LSB)
DVM
0.1µ
7
D9 (MSB) VG 22
9
CLK
10 BLK
CLK
80MHz
SQUARE
WAVE
IO 23
31
CONTROLLER
VREF 19
11 CE
2V
AVDD
5K
AVSS
IREF 17
14 VB
200
3.3K
0.1µ
FIGURE 2. DC CHARACTERISTICS TEST CIRCUIT
30 D0 (LSB)
IO 23
OSCILLOSCOPE
31
0.1µ
FREQUENCY
DEMULTIPLIER
7
D9 (MSB) VG 22
9
CLK
10 BLK
CLK
10MHz (MAX)
SQUARE
WAVE
11 CE
14 VB
VREF 19
2V
AVDD
5K
AVSS
IREF 17
3.3K
0.1µ
FIGURE 3. PROPAGATION DELAY TIME TEST CIRCUIT
10-5
200
HI2315
Test Circuits
(Continued)
30 D0 (LSB)
10-BIT
COUNTER
WITH
LATCH
0.1µ
DELAY
CONTROLLER
CLK
1MHz
SQUARE
WAVE
7
D9 (MSB) VG 22
9
CLK
10 BLK
VREF 19
11 CE
DELAY
CONTROLLER
IO 23
31
2V
5K
AVSS
IREF 17
14 VB
AVDD
3.3K
0.1µ
FIGURE 4. SETUP HOLD TIME AND GLITCH ENERGY TEST CIRCUIT
10-6
200
OSCILLOSCOPE
HI2315
Timing Diagram
tPW1
TABLE 1. I/O CORRESPONDENCE TABLE
(2.00V Output Full Scale Voltage)
tPW0
CLK
INPUT CODE
tS tH
tS tH
MSB
tS tH
OUTPUT VOLTAGE
LSB
1 1 1 1 1 1 1 1 1 1
DATA
2.0V
•
•
•
tPD
1 0 0 0 0 0 0 0 0 0
100%
1.0V
•
•
•
D/A OUT
50%
0 0 0 0 0 0 0 0 0 0
tPD
tPD
0V
0%
Typical Application Circuits
R3
R1
C
R4
R2
AVDD
DVDD
AVSS
DVSS
C
24
23 22
21
20
19
18
17
IO
IO VG AVDD AVDD VREF SREF IREF
25 AVSS
NC 16
DVSS 15
26 NC
27 DVSS
VB 14
28 DVDD
DVDD 13
C
C
29 NC
NC 12
30 D0
CE 11
31 D1
BLK 10
32 D2
D3
1
D4
D5
D6
D7
D8
D9
2
3
4
5
6
7
CLK 9
NC
CLOCK INPUT
8
NOTE:
2. When 5.0V supply voltage (DVDD and AVDD). Digital input from pins 30 to 32 and pins 1 to 7. Pin 18 is Left Open When Using Normally.
R1 = 200Ω, R2 = 3.3Ω (Resistance 16 Times R1), R3 = 3.0kΩ, R4 = 2.0kΩ, C = 0.1µF.
FIGURE 5. APPLICATION CIRCUIT 1
10-7
HI2315
Typical Application Circuits
(Continued)
R1
C
R2
AVDD
DVDD
AVSS
DVSS
C
24
23 22
21
20
19
18
17
IO
IO VG AVDD AVDD VREF SREF IREF
25 AVSS
NC 16
DVSS 15
26 NC
27 DVSS
VB 14
28 DVDD
DVDD 13
C
C
29 NC
NC 12
30 D0
CE 11
31 D1
BLK 10
32 D2
D3
D4
D5
D6
D7
D8
D9
2
3
4
5
6
7
1
CLK 9
NC
CLOCK INPUT
8
NOTE:
3. When 5.0V supply voltage (DVDD and AVDD). Digital input from pins 30 to 32 and pins 1 to 7. R1 = 200Ω, R2 = 2.0kΩ, C = 0.1µF.
FIGURE 6. APPLICATION CIRCUIT 2
OUTPUT FULL SCALE VOLTAGE (V)
OUTPUT FULL SCALE VOLTAGE (V)
Typical Performance Curves
2.0
1.0
∆V = 0.2mV/oC
1.95
1.93
0
1.0
-25
2.0
0
25
50
75
AMBIENT TEMPERATURE (oC)
REFERENCE VOLTAGE (V)
FIGURE 7. OUTPUT FULL SCALE VOLTAGE (VFS) vs
REFERENCE VOLTAGE (VREF)
FIGURE 8. OUTPUT FULL SCALE VOLTAGE vs AMBIENT
TEMPERATURE
10-8
HI2315
Typical Performance Curves
(Continued)
CURRENT CONSUMPTION (mA)
∆ V = 0.7mV/oC
SREF OUTPUT VOLTAGE (V)
1.25
1.15
0
30
20
0
-25
0
25
50
75
1
AMBIENT TEMPERATURE (oC)
10
20
30
40
OUTPUT FREQUENCY (MHz)
FIGURE 9. SREF vs AMBIENT TEMPERATURE
FIGURE 10. OUTPUT FREQUENCY vs CURRENT CONSUMPTION
NOTE:
4. Standard Measurement Conditions and Description: VDD = 5.0V, VREF = 2.0V, R = 200Ω, 16R - 3.3kΩ, TA = 25oC. The temperature
characteristics of external input data in Figure 10 = all “0” and “1” of rectangular wave; clock frequency = 80MHz.
GE (Glitch Energy)
GE, as described in the HI2315, is a spike noise which
appears synchronizing with the clock falling edge when the
input data (for 1 to 1024 input) changes to 128, 256, 384,
512, 640, 768, 896, and 1024. Figure 11 shows the change
state of GE for the staircase wave output, and Figure 12
shows the repetitive output waveform where the GE
appears. These figures exhibit the difference of this IC from
the convention device.
The HI2315 reduces the GE as shown in Figures 11 and 12.
ANALOG OUTPUT (V)
2.0
CONVENTIONAL
DEVICE
1.0
HI2315
0
512
1024
CLK
DIGITAL INPUT (V)
FIGURE 11. CHANGE OF GE FOR STAIRCASE WAVE OUTPUT
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
10-9
HI5780 (GE TYP = 200pV/S)
HI2315 (GE TYP = 10pV/S)
FIGURE 12. REPETITIVE OUTPUT WAVEFORM WHERE GE APPEARS (FOR 200Ω, 2VP-P OUTPUT)
Notes On Operation
• Selecting the Output Resistance
- HI2315 is a current output type D/A converter. To create
the output voltage, connect the resistor to the current
output pin.
Specifications:
Output full-scale voltage VFS (Max) = 2.0V
Output full-scale current IFS (Max) = 10mA
• Latch up
- The AVDD and DVDD pins must be able to share the
same power supply of the board. This is prevent latch
up caused by potential difference between the two pins
when the power is turned on.
• IREF pin
- Calculate the output resistance from V FS = IFS x R.
Connect a resistance sixteen times the output
resistance to the reference current pin IREF. In some
cases, as this value may not exist, a similar value can
be used instead.
- The IREF pin is very sensitive to improve the AC
characteristics.
Pay
attention
for
capacitance
component not to attach to this pin because its output
may become unstable.
• VG Pin
Note that the VFS will be the following:
VFS = VREF x 16 R/R’.
- R is the resistor to be connected to the IO and R’ is the
resistor to be connected to the IREF. Power consumption can be reduced by increasing the resistance, but
this will on the contrary increase the glitch energy and
data settling time. Set the best values according to the
purpose of use.
- It is recommended to use a 1µF capacitor to improve
the AC characteristics though the typical capacitance
value externally connected to the VG pin is 0.1µF.
• SREF
• Correlation between Data and Clock
- For the HI2315 to display the desired performance as a
D/A converter, the data transmitted form outside and the
clock must be synchronized properly. Adjust the setup
time (tS) and hold time (tH) as specified in “Electrical
Characteristics.”
• VDD , V SS
- Separate the analog and digital signals around the
device to reduce noise effects. By-pass the VDD pin to
each GND with a 0.1µF ceramics capacitor as near to
the pin as possible for both the digital and analog
signals.
10-10
- The SREF is independent regulated current source. By
connecting it to the V REF, stable output amplitudes that
do not depend on fluctuations in the power supply can
be obtained.
- In this case, as VFS = SREF x 16R/R’, set the VFS
according to R’.
- Do not use this pin as a reference power supply for
other ICs because this is dedicated for the D/A
converter.
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