HI5710A 10-Bit, 20 MSPS A/D Converter August 1997 Features Description • Resolution ±0.5 LSB (DNL) . . . . . . . . . . . . . . . . . . 10-Bit The HI5710A is a low power, 10-bit, CMOS analog-to-digital converter. The use of a 2-step architecture realizes low power consumption, 150mW, and a maximum conversion speed of 20MHz with only a 3 clock cycle data latency. The HI5710A can be powered down, disabling the chip and the digital outputs, reducing power to less than 5mW. A built-in, user controllable, calibration circuit is used to provide low linearity error, 1 LSB. The low power, high speed and small package outline make the HI5710A an ideal choice for CCD, battery, and high channel count applications. • Maximum Sampling Frequency . . . . . . . . . . . 20 MSPS • Low Power Consumption (Reference Current Excluded) . . . . . . . . . . . . . .150mW • Standby Mode Power . . . . . . . . . . . . . . . . . . . . . . .5mW • No Sample and Hold Required • TTL Compatible Inputs • Three-State TTL Compatible Outputs • Single +5V Analog Power Supply • Data Communications The HI5710A does not require an external sample and hold but requires an external reference and includes force and sense reference pins for increased accuracy. The digital outputs can be inverted, with the MSB controlled separately, allowing for various digital output formats. The HI5710A includes a test mode where the digital outputs can be set to a fixed state to ease in-circuit testing. • Image Scanners Ordering Information • Single +3.3V or +5V Digital Power Supply Applications • Video Digitizing - Multimedia • Medical Imaging • Video Recording Equipment TEMP. RANGE (oC) PART NO. • Camcorders HI5710AJCQ -20 to 75 PACKAGE 48 Ld MQFP PKG. NO. Q48.7x7-S • QAM Demodulation Pinout D0 TSTR NC VIN AT TS CAL AVSS NC DVDD AVSS NC DVSS HI5710A (MQFP) TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 36 1 AVss 30 VRT D5 8 29 D6 D7 9 28 VRT AVSS 10 27 AVSS 11 12 26 AVDD 25 13 14 15 16 17 18 19 20 21 22 23 24 AVDD D8 TO D9 CE 31 DVDD OE 6 7 NC NC NC MINV CLK 32 TESTMODE LINV 5 D4 DVSS SEL 33 AVDD VRB 4 D2 D3 RESET DVSS VRB 34 D1 TIN 2 3 35 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 4-1531 File Number 3921.5 HI5710A Functional Block Diagram VIN 39 S/H AMP + ∑ 8x 12 D9 (MSB) COURSE CORRECTION AND LATCH VRT 29 VRT 30 11 D8 10 D7 9 D6 8 D5 DAC COURSE COMPARATOR AND ENCODE FINE COMPARATOR AND ENCODE CALIBRATION UNIT FINE LATCH 5 D4 4 D3 3 D2 2 D1 1 D0 (LSB) 21 MINV VRB 34 20 LINV VRB 35 19 TESTMODE CLK 22 OE 23 CE 24 TIMING GEN 41 CAL AUTO CALIBRATION PULSE GENERATOR 17 SEL 15 RESET 4-1532 HI5710A Absolute Maximum Ratings TA = 25oC Thermal Information Supply Voltage, AVDD , DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Reference Voltage, VRT , VRB . . . . . . . . . VDD + 0.5V to VSS - 0.5V Analog Input Voltage, VIN . . . . . . . . . . . . . VDD + 0.5V to VSS - 0.5V Digital Input Voltage, VIH , VIL . . . . . . . . . . VDD + 0.5V to VSS - 0.5V Digital Output Voltage, VOH , VOL . . . . . . . VDD + 0.5V to VSS - 0.5V Thermal Resistance (Typical, Note 1) θJA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range, TSTG . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (Lead Tips Only) Operating Conditions Supply Voltage AVDD , AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±0.25V DVDD , DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3V to 5V ±0.25V |DGND-AGND| . . . . . . . . . . . . . . . . . . . . . . . . . . . .0mV to 100mV Reference Input Voltage VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8V to 2.8V VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.6V to 4.6V Analog Input Range, VIN . . . . . . . .(VRT - VRB) (1.8VP-P to 2.8VP-P) Clock Pulse Width tPW1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25ns (Min) tPW0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25ns (Min) Temperature, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-20oC to 75oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications fC = 20 MSPS, AVDD = +5V, DVDD = +3.3V, VRB = 2.0V, VRT = 4.0V, TA = 25oC (Note 2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EOT 40 90 140 mV EOB -120 -70 -20 mV - ±1.3 ±2.0 LSB - ±0.5 ±1.0 LSB 20 - - MSPS - - 0.5 MSPS SYSTEM PERFORMANCE Offset Voltage Integral Non-Linearity, INL VIN = 2.0V to 4.0V Differential Non-Linearity, DNL DYNAMIC CHARACTERISTICS Maximum Conversion Speed, fC fIN = 1kHz Ramp Minimum Conversion Speed, fC Effective Number of Bits, ENOB fIN = 3MHz - 8.7 - BIts Signal to Noise and Distortion, SINAD fIN = 100kHz - 53 - dB fIN = 500kHz - 52 - dB fIN = 1MHz - 53 - dB fIN = 3MHz - 54 - dB fIN = 7MHz - 47 - dB fIN = 10MHz - 45 - dB fIN = 100kHz - 60 - dB fIN = 500kHz - 59 - dB fIN = 1MHz - 60 - dB fIN = 3MHz - 65 - dB fIN = 7MHz - 50 - dB fIN = 10MHz - 49 - dB NTSC 40 IRE Mod Ramp, fC = 14.3 MSPS - 1.0 - % - 0.3 - Degree Spurious Free Dynamic Range, SFDR Differential Gain Error, DG Differential Phase Error, DP 4-1533 HI5710A Electrical Specifications fC = 20 MSPS, AVDD = +5V, DVDD = +3.3V, VRB = 2.0V, VRT = 4.0V, TA = 25oC (Note 2) (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT - 100 - MHz VIN = 4V - - 50 µA VIN = 2V -50 - - µA VIN = 2.5V + 0.07VRMS - 9 - pF Reference Pin Current, IRT RESET = Low 5 7 11 mA Reference Pin Current, IRB RESET = Low -11 -7 -5 mA 180 280 380 Ω 2.3 - - V - - 0.80 V VIH = DVDD - - 5 µA VIL = 0V - - 5 µA VOH = DVDD -0.5V 3.5 - - mA VOL = 0.4V 3.5 - - mA VOH = DVDD - - 1 µA VOL = 0V - - 1 µA 8 13 18 ns tPZL 10 15 20 ns tPLZ 20 25 30 ns tPZH 10 15 20 ns tPHZ 20 25 30 ns 2 4 6 ns 20 27 34 mA - 3 5 mA - - 1.0 mA - - 1.0 µA ANALOG INPUTS Analog Input Bandwidth (-3dB), BW Analog Input Current Analog Input Capacitance, CIN REFERENCE INPUT Reference Resistance (VRT to VRB), RREF DIGITAL INPUTS Digital Input Voltage VIH AVDD = 4.75V to 5.25V VIL Digital Input Current IIH DVDD = Max IIL DIGITAL OUTPUTS Digital Output Current IOH OE = AVSS , DVDD = Min IOL Digital Output Leakage Current IOZH OE = AVDD , DVDD = Max IOZL TIMING CHARACTERISTICS Output Data Delay, tDL Output Enable/Disable Delay Load is One TTL Gate Sampling Delay, tSD POWER SUPPLY CHARACTERISTIC Analog Supply Current, IADD fIN = 1kHz Ramp Wave Input Digital Supply Current, IDDD Analog Standby Current CE = High Digital Standby Current NOTE: 2. Electrical specifications guaranteed only under the stated operating conditions. 4-1534 HI5710A Timing Diagrams tPW1 tPW0 1.65V 1.65V CLOCK tSD N+2 N+1 ANALOG INPUT N N+3 N+4 N-3 DATA OUTPUT N-2 N-1 N 1.65V (DVDD = 3.3V) 2.5V (DVDD = 5.0V) tDL = INDICATES POINT AT WHICH ANALOG DATA IS SAMPLED FIGURE 1. tPLZ tPHZ 1.65V (DVDD = 3.3V) 2.5V (DVDD = 5.0V) tPZL tPZH 1.65V (DVDD = 3.3V) 2.5V (DVDD = 5.0V) OUTPUT ENABLE (OE) DATA OUTPUT ACTIVE HIGH IMPEDANCE FIGURE 2. 4-1535 HI5710A Calibration Timing Diagrams 10ns OR MORE 7 CLOCKS CLK 1 CLOCK OR MORE CAL D5 TO D9 D0 TO D4 FIGURE 3. EXTERNAL CALIBRATION PULSE TIMING DIAGRAM INPUT CLK CAL FIGURE 4A. CALIBRATION DURING H SYNC INPUT CLK CAL FIGURE 4B. CALIBRATION DURING V SYNC FIGURE 4. EXAMPLES OF EXTERNAL CALIBRATION PULSE INPUT FOR VIDEO APPLICATIONS 4-1536 HI5710A Typical Performance Curves fC = 20MHz fIN = 1kHz RAMP WAVE AVDD = 5.0V DVDD = 3.3V 27 26 25 24 -20 0 25 50 75 35 MAXIMUM OPERATING FREQUENCY (MHz) SUPPLY CURRENT (mA) 28 fIN = 1kHz RAMP WAVE AVDD = 5.0V DVDD = 3.3V 30 25 20 -20 100 FIGURE 5. SUPPLY CURRENT vs AMBIENT TEMPERATURE 50 75 100 8 AVDD = 5.0V DVDD = 3.3V fC = 1MHz CL = 20pF SAMPLING DELAY (ns) OUTPUT DATA DELAY (ns) 25 FIGURE 6. MAXIMUM OPERATING FREQUENCY vs AMBIENT TEMPERATURE 19 17 0 AMBIENT TEMPERATURE (oC) AMBIENT TEMPERATURE (oC) 15 13 AVDD = 5.0V DVDD = 3.3V fC = 1MHz 6 4 2 11 -20 0 25 50 -20 75 0 25 50 75 AMBIENT TEMPERATURE (oC) AMBIENT TEMPERATURE (oC) FIGURE 7. OUTPUT DATA DELAY vs AMBIENT TEMPERATURE FIGURE 8. SAMPLING DELAY vs AMBIENT TEMPERATURE 65 80 60 75 70 55 DVDD = 3.3V SFDR (dB) SINAD (dB) 65 50 DVDD = 5V 45 40 35 30 25 0.1 AVDD = 5.0V DVDD = 3.3V fC = 20MHz VIN = 2VP-P TA = 25oC 60 55 50 AVDD = 5.0V DVDD = 3.3V fC = 20MHz VIN = 2VP-P TA = 25oC 45 40 35 1 10 100 INPUT FREQUENCY (MHz) FIGURE 9. SINAD vs INPUT FREQUENCY 30 0.1 1 10 INPUT FREQUENCY (MHz) FIGURE 10. SFDR vs INPUT FREQUENCY 4-1537 100 HI5710A (Continued) 10 2 9 1 OUTPUT LEVEL (dB) EFFECTIVE NUMBER OF BITS (BITS) Typical Performance Curves 8 DVDD = 3.3V DVDD = 5V 7 AVDD = 5.0V DVDD = 3.3V fC = 20MHz VIN = 2VP-P TA = 25oC 6 5 0 -1 -2 AVDD = 5.0V DVDD = 3.3V fC = 20MHz VIN = 2VP-P TA = 25oC -3 -4 4 0.1 1 10 -5 100 100K 1M INPUT FREQUENCY (MHz) FIGURE 11. EFFECTIVE BITS vs INPUT FREQUENCY 10 EFFECTIVE NUMBER OF BITS (BITS) TA = 25oC 60 INPUT CURRENT (mA) 100M FIGURE 12. INPUT BANDWIDTH 80 40 20 0 -20 -40 -60 9.5 fIN = 1MHz DVDD = 5V/3.3V 9 8.5 8 fIN = 5MHz 7.5 DVDD = 5V fIN = 5MHz 7 DVDD = 3.3V 6.5 6 -80 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 5 4 FIGURE 13. ANALOG INPUT CURRENT vs INPUT VOLTAGE 20 25 30 59 DVDD = 5V -30 57 -35 55 -40 -50 SNR (dB) -45 -60 15 FIGURE 14. ENOB vs CLOCK FREQUENCY -25 -55 10 CLOCK FREQUENCY INPUT VOLTAGE (V) THD (dB) 10M INPUT FREQUENCY (Hz) DVDD = 5V 53 DVDD = 3.3V 51 DVDD = 3.3V 49 -65 47 -70 -75 0.1 1 10 100 INPUT FREQUENCY (MHz) FIGURE 15. THD vs INPUT FREQUENCY 45 100 1,000 10,000 INPUT FREQUENCY (MHz) FIGURE 16. SNR vs INPUT FREQUENCY 4-1538 100,000 HI5710A Pin Description and I/O Pin Equivalent Circuit PIN NUMBER 1 to 5, 8 to 12 SYMBOL D0 to D9 EQUIVALENT CIRCUIT DESCRIPTION Digital Outputs: D0 (LSB) to D9 (MSB). DVDD D1 DVSS 13 TO Test Pin, Leave Pin Open. 7, 45 DVDD Digital VDD . 6, 16, 48 DVSS Digital VSS . 27, 28, 36, 43, 44 AVSS Analog VSS . 17 SEL Controls calibration input pulse selection after completion of the internal start-up calibration function. High: Selects the internal auto calibration pulse generation function Low: Selects the external calibration pulse input, CAL pin 41. AVDD 17 AVSS 22 CLK Clock Pin. AVDD 22 AVSS 41 CAL Calibration Pulse Input, calibration starts on a falling edge, normally high. AVDD 41 AVSS 15 RESET Calibration Circuit Reset and Internal Calibration Function Restart, resets with a negative pulse, normally high. AVDD 15 AVSS 14 TIN Factory Test Signal Input, normally tied to AVSS or AVDD . 4-1539 HI5710A Pin Description and I/O Pin Equivalent Circuit PIN NUMBER SYMBOL 29, 30 VRT 34, 35 VRB EQUIVALENT CIRCUIT (Continued) DESCRIPTION Reference Top, normally 4.0V. AVDD Reference Bottom, normally 2.0V. 29, 30 AVSS 34, 35 38 AT Factory Test Signal Output, leave pin open. 42 TS Factory Test Signal Input, tie to AVDD . 37 TSTR Factory Test Signal Input, tie to AVSS . 23 OE D0 to D9 Output Enable. Low: Outputs Enabled. High: High Impedance State. AVDD 23 AVSS 24 CE Chip Enable. Low: Active State. High: Standby State. AVDD 24 AVSS 19 TESTMODE Test Mode. High: Normal Output State. Low: Output fixed. AVDD 19 AVSS 20 LINV Output Inversion. High: D0 to D8 are inverted. Low: D0 to D8 are normal. AVDD 20 AVSS 4-1540 HI5710A Pin Description and I/O Pin Equivalent Circuit PIN NUMBER SYMBOL 21 MINV (Continued) EQUIVALENT CIRCUIT DESCRIPTION Output Inversion. High: D9 is inverted. Low: D9 is normal. AVDD 21 AVSS 18, 25, 26 AVDD 39 VIN Analog VDD . Analog Input. AVDD 39 - + AVSS A/D OUTPUT CODE TABLE DIGITAL OUTPUT CODE INPUT SIGNAL VOLTAGE STEP MSB VRT 1023 1 • • • • • • • • • • • 512 1 0 0 0 511 0 1 1 1 VRB 0 LSB 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 • • • • • • • • • 0 0 0 0 0 NOTE: 3. This table shows the correlation between the analog input voltage and the digital output code. (TESTMODE = 1, MINV and LINV= 0) DIGITAL OUTPUT DATA FORMAT TABLE TESTMODE LINV MINV D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 1 0 0 N N N N N N N N N N 1 1 0 I I I I I I I I I N 1 0 1 N N N N N N N N N I 1 1 1 I I I I I I I I I I 0 0 0 1 0 1 0 1 0 1 0 1 0 0 1 0 0 1 0 1 0 1 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 NOTES: 4. This table shows the output state for the combination of TESTMODE, LINV, and MINV states. 5. N: Non-Inverted Output. 6. I: Inverted Output. 4-1541 HI5710A Detailed Description Digital Outputs The HI5710A is a two step A/D converter featuring a 5-bit upper comparator group and a 5-bit lower comparator group. A user controllable internal calibration unit is used to improve linearity. The voltage references must be supplied externally, with VRB and VRT typically being set to 2.0V and 4.0V respectively. Both chip enable and output enable pins are provided for flexibility and to reduce power consumption. The digital outputs can be inverted by control inputs LINV and MINV, where LINV controls outputs D0 through D8 and MINV controls output D9 (MSB). This allows for various digital output data formats, such as straight binary, inverted binary, offset two’s complement or inverted offset two’s complement. Analog Input The analog input typically requires a 2VP-P full scale input signal. The full scale input can range from 1.8VP-P to 2.8VP-P dependent on the voltage references used. The input capacitance is small when compared with other flash type A/D converters. However, it is necessary to drive the input with an amplifier with sufficient bandwidth and drive capability. Op amps such as the HA5020 should make an excellent input amplifier depending on the application requirements. In order to prevent parasitic oscillation, it may be necessary to insert a resistor between the output of the amplifier and the A/D input. Be sure to consider the amplifiers settling time in CCD applications or where step inputs are expected. Reference Input The analog input voltage range of the A/D is set by the voltage difference between the VRT and VRB voltage references. The HI5710A is designed for use with external voltage references of 2.0V and 4.0V on VRB and VRT , respectively. The analog input voltage range of the A/D will now be from 2.0V to 4.0V. The VRB voltage reference range is 1.8V to 2.8V and the VRT voltage reference range is 3.6V to 4.6V. The voltage difference between the VRT and VRB voltage references, (VRT - VRB), can range from 1.8V to 2.8V. The VRT and VRB voltage reference input pins must be decoupled to analog ground to minimize noise on these references. A 0.1µF capacitor is usually adequate. Clock Input The HI5710A samples the input signal on the rising edge of the clock with the digital data being latched at the digital outputs (D0 - D9) after 3 clock cycles. The HI5710A is designed for use with a 50% duty cycle square wave, but a 10% variation should not affect performance. The digital outputs are CMOS outputs. The LINV control input will invert outputs D0 through D8 and MINV control input will invert output D9 (MSB). This allows the user to set the digital output data for a number of different digital formats. The outputs can also be three-stated by pulling the OE control input high. The digital output supply can run from +3.3V or +5V. The digital outputs will generate less radiated noise using +3.3V, but the outputs will have less drive capability. The digital outputs will only swing to DVDD , therefore exercise care if interfacing to +5V logic when using a +3.3V supply. The digital output data can also be set to a fixed, predetermined state, through the use of the TESTMODE, LINV and MINV control input signals, see the Digital Output Data Format table. By setting the TESTMODE pin low, the outputs go to a defined digital pattern. This pattern is varied by the MINV and LINV control inputs. This feature can be used for in-circuit testing of the digital output data bus. Calibration Function The HI5710A has a built-in calibration unit which is designed to provide superior linearity by correcting the gain error of the subrange amplification circuitry. In addition to the calibration unit, the HI5710A provides a built-in auto calibration pulse generation function. Figure 20 shows a functional block diagram of the auto calibration pulse generator circuit. The calibration pulse generation functions provided can be subdivided into four operational areas. The first function is the generation of the calibration pulses required to complete the initial (power-up) calibration process when power is first supplied to the converter. The next two functions accommodated are the generation of periodic calibration pulses, either internally or externally, to maintain calibration. The last function is the provision for externally initiating or re-initiating the power-up calibration process. Power-up Calibration Function The initial power-up calibration requires over 600 calibration pulses in order to complete the calibration process when power is first applied to the converter. The power-up calibration function provided by the auto calibration pulse generator automatically generates these pulses internally and completes the initial calibration process. The following five conditions must be satisfied in order for the auto calibration pulse generator power-up calibration process to be initiated : a) The voltage between AVDD and AVSS is approximately 2.5V or more. b) The voltage between VRT and VRB is approximately 1.0V or more. The clock input can be driven from +3.3V CMOS or +5V TTL/CMOS logic. When using a +3.3V digital supply, HC or AC CMOS logic will work well. c) The RESET control input pin (Pin 15) must be high (logic 1). Digital Inputs e) Condition b must be met after condition a. The digital inputs can be driven from +3.3V CMOS or +5V TTL/CMOS logic. When using a +3.3V digital supply, HC or AC CMOS logic will work well. Once all five of these conditions is satisfied the power-up calibration pulses are generated. These power-up calibration pulses are derived from a divided-by sixteen sample clock d) The CE control input pin (Pin 24) must be low (logic 0). 4-1542 HI5710A (CLK/16). A 14-bit counter is also counting the CLK/16 signal and when the 14-bit counter reaches the end of its count range the carry out from the counter is used to gate off or mask the CLK/16 power-up calibration pulses. The time required for the power-up calibration process to be completed after the above five conditions has been met can be calculated using the following equation: tPower-Up Cal = (24 x 214)/(fCLK) = 218/fCLK . For example, if the sample clock frequency is 20MHz, the time required for the power-up calibration process to be completed, after the above five conditions has been met, is tPower-Up Cal = 218/fCLK = 218/20x106 = 262,144/20 x 106 , tPower-Up Cal = 13.1ms. Auto Calibration Pulse Generation Function The auto calibration pulse generator provides the user with the choice of internal or external periodic calibration pulse generation following the completion of the power-up calibration process. The selection of internal or external periodic calibration pulse generation is made through the use of the SEL control input pin (pin 17). Setting the SEL control input pin high (logic 1) selects the internal periodic calibration pulse generation function. Setting the SEL control input pin low (logic 0) selects the external calibration pulse input pin (CAL, pin 41). For the case where the internal periodic calibration pulse generation function has been chosen, SEL control input pin high, the auto calibration pulse generator periodically generates calibration pulses internally so that calibration is performed constantly without the need to provide calibration input pulses from an external source. These periodic calibration pulses are derived from the divided-by sixteen sample clock (CLK/16). The CLK/16 signal drives a 24-bit counter which generates a carry-out that is used as the internal calibration pulse. The time between calibration pulses when using the internal auto calibration pulse generator can be calculated using the following equation: tInternal Cal Pulse = (24 x 224)/(fCLK) = 228/fCLK . For example, if the sample clock frequency is 20MHz, the time between internal auto calibration pulses is: tInternal Cal Pulse = 228/fCLK = 228/20 x 106 = 268,435,456/20 x 106, tInternal Cal Pulse = 13.4s. Since a calibration is completed once every seven calibration pulses, the time required to complete a calibration cycle is: tInternal Cal Cycle = (7 x 228)/fCLK . Therefore, if the sample clock frequency is 20MHz, the internal calibration cycle is: tInternal Cal Cycle = (7 x 228)/20 x 106 = 93.95s. It should be noted that this method of periodic calibration may not be acceptable if the fixing of the lower five output bits during the calibration (see the discussion below on external calibration pulse input function) would cause problems since the calibration is executed asynchronously without regard to the analog input signal. External Calibration Pulse Input Function If the auto calibration pulse generation function cannot be used then periodic calibration can be performed by providing externally input calibration pulses to the CAL input pin (pin 41) and setting the SEL control input pin (pin 17) low. Refer to Figure 3, External Calibration Pulse Timing Diagram, for details on the required timing of the externally supplied calibration pulses. A setup time of 10ns or longer is required for the CAL input and it must stay low for at least one sample clock (CLK) period. Calibration starts when the falling edge of the externally supplied calibration pulse, input to the CAL pin, is detected. One calibration is completed in 11 sample clock cycles. Seven sample clock cycles after the falling edge of the externally supplied calibration pulse is detected, the calibration circuit takes exclusive possession of the lower comparators, D0 through D4, for four sample clock cycles. During this time, the D0 through D4 outputs are latched with the previous data (cycle seven data). The upper 5 bits, D5 through D9, will operate as usual during the calibration. The calibration must be done when the part is first powered up, if the sampling frequency changes, when the supplies vary more than 100mV or when (VRT - VRB) changes more than 200mV. Figure 4 shows several possible external calibration pulse timing schemes where the calibration is performed outside the active video interval by using the video sync signal as the externally supplied CAL input. It is not necessary to calibrate as often as these figures show, these are only design ideas. It is also possible to use only the power-up calibration function by leaving the SEL control input pin (pin 17) low and fixing the CAL input pin (pin 41) either high or low. Note, however, that using only the power-up calibration function will require the above restrictions on the sample frequency and the fluctuation range of the power supply voltage and the reference voltage differential be maintained. Initiating/Re-Initiating Power-up Calibration Function The power-up calibration function can be initiated/re-initiated after the power supply voltage and the reference voltages are stabilized by using the CE (pin 24) or RESET (pin 15) control input pins. This might prove useful in a situation where the turn-on characteristics of the power supply and reference voltages is unstable/indeterminate or where the sequence of power-up does not meet the required conditions stated earlier. Power, Grounding, and Decoupling To reduce noise effects, keep the analog and digital grounds separated. Bypass both the digital and analog VDD pins to their respective grounds with a ceramic 0.1µF capacitor close to the input pin. A larger capacitor (1µF to 10µF) should be placed somewhere on the PC board for low frequency decoupling of both analog and digital supplies. The analog supply should be present before the digital supply to reduce the risk of latch-up. The digital supply can run from +3.3V or +5V. A +3.3V supply generates less radiated noise at the digital outputs, but results in less drive capability. The specifications do not change with digital supply levels. Remember, the digital outputs will only swing to DVDD . 4-1543 HI5710A To obtain full expected performance from the converter be sure that the circuit board has a large ground plane to provide as low an impedance as possible. It is recommended that the converter be mounted directly to the circuit board and the use of a socket is highly discouraged. Test Circuits +V S2 - S1: ON IF A < B S2: ON IF A > B S1 + -V A<B A>B COMPARATOR VIN 10 DUT HI5710A “0” A10 B10 A1 A0 B1 B0 10 BUFFER “1” DVM 10 CLK (20MHz) 000 • • • 00 TO 111 • • • 10 CONTROLLER FIGURE 17. INTEGRAL AND DIFFERENTIAL NON-LINEARITY ERROR TEST CIRCUIT 4.0V fC -1kHz SCOPE SG 2.0V 1 2 NTSC SIGNAL SOURCE 100 IRE 0 -40 SG (CW) VIN AMP DUT HI5710A 10 1 12-BIT D/A 2 CLK 40 IRE MODULATION VECTOR SCOPE 4V DG DP BURST 2V SYNC fC FIGURE 18. MAXIMUM OPERATIONAL SPEED AND DIFFERENTIAL GAIN /PHASE ERROR TEST CIRCUIT 4V VDD VRT 4V IOL VIN 2V 2V CLK VRB CLK VOL GND IOH VIN VRB OE VDD VRT VOH OE + GND - FIGURE 19A. FIGURE 19B. FIGURE 19. DIGITAL OUTPUT TEST CIRCUIT 4-1544 + - HI5710A Test Circuits (Continued) AVDD 14-BIT COUNTER 1 16 CLK D CO CLR AVDD OUT Q CLR SENCE AMP 1 AVSS VRT 24-BIT COUNTER SENCE AMP 2 VRB CO CLR RESET SEL CE CAL FIGURE 20. CALIBRATION PULSE GENERATION CIRCUIT Typical Application Circuits - - +5VA + TSTR 4.0V AT VIN 2.0V NC CAL TS AVSS AVSS +5VA 0.1 AVDD AVDD AVSS VRT AVSS VRT NC NC NC VRB 23 39 22 40 21 41 20 42 HI5710A 43 CE OE CLK MINV 19 TESTMODE 18 AVDD 17 45 16 SEL DVSS NC 46 15 RESET NC DVSS 47 14 TIN 13 8 9 10 11 12 TO 48 1 2 3 4 5 6 7 CLOCK INPUT LINV 44 DVDD 0.1µF 36 35 34 33 32 31 30 29 28 27 26 25 24 +5VA 0.1µF D9 D8 D6 D7 D5 D4 DVSS D3 D2 AVSS D0 D1 +3.3VD 10µF 37 38 VRB 0.1µF AVss 2.0V + 4.0V +3.3VD 0.1 DIGITAL OUTPUTS FIGURE 21A. POWER-UP CALIBRATION WITH INTERNAL AUTO CALIBRATION SELECTED 4-1545 DVSS 10µF HI5710A Typical Application Circuits (Continued) - - +5VA + TSTR 4.0V AT VIN 2.0V NC CAL CALIBRATION PULSE TS AVSS AVSS +5VA 0.1 +3.3VD 10µF AVDD AVDD AVSS VRT AVSS VRT NC NC NC VRB 36 35 34 33 32 31 30 29 28 27 26 25 24 23 39 40 22 21 41 20 42 HI5710A 43 CE OE CLK MINV 19 TESTMODE 18 AVDD 17 45 16 SEL DVSS NC 46 15 RESET NC DVSS 47 14 TIN 48 13 8 9 10 11 12 TO 1 2 3 4 5 6 7 CLOCK INPUT LINV 44 DVDD 0.1µF 37 38 VRB 0.1µF AVss 2.0V + 4.0V +5VA 0.1µF DVSS D9 D8 D6 D7 D5 D4 DVSS D3 D2 D0 D1 AVSS +3.3VD 0.1 DIGITAL OUTPUTS FIGURE 21B. POWER-UP CALIBRATION WITH EXTERNAL CALIBRATION PULSE INPUT SELECTED 4-1546 10µF HI5710A Typical Application Circuits (Continued) - + +5VA TSTR AT VIN NC CAL TS AVSS AVSS AVDD AVDD AVSS VRT AVSS VRT NC NC NC VRB 41 20 42 HI5710A 43 CE OE CLK MINV 19 TESTMODE 18 AVDD 45 16 NC 46 15 RESET NC DVSS 47 14 TIN 48 13 8 9 10 11 12 TO 44 17 1 2 3 4 5 6 7 CLOCK INPUT LINV SEL DVSS DVDD +5VA 0.1µF D9 D8 AVSS D6 D7 0.1µF 40 22 21 D0 D1 +3.3VD 10µF 39 D5 0.1 23 D4 DVSS +5VA 36 35 34 33 32 31 30 29 28 27 26 25 24 D3 2.0V 37 38 D2 4.0V VRB 0.1µF AVss 2.0V + 4.0V +3.3VD 0.1 DIGITAL OUTPUTS FIGURE 21C. ONLY POWER-UP CALIBRATION BEING UTILIZED 4-1547 DVSS 10µF HI5710A Timing Definitions Dynamic Performance Definitions Sampling Delay, is the time delay between the external sample command (the rising edge of the clock) and the time at which the analog input signal is actually sampled. This delay is due to internal clock path propagation delays. Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the HI5710A. A low distortion sine wave is applied to the input, it is sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with a 2048 point FFT and analyzed to evaluate the dynamic performance of the A/D. The analog sine wave input signal to the converter is -0.5dB down from full scale for all these tests. The distortion numbers are quoted in dBc (decibels with respect to carrier) and DO NOT include any correction factors for normalizing to full scale. Data Latency, after the analog sample is taken, the digital representation is output on the digital data output bus after the 3rd cycle of the clock. This is due to the pipeline nature of the converter where the data has to ripple through the stages. This delay is specified as the data latency. After the data latency time, the data representing each succeeding analog input sample is output on the following rising edge of the clock pulse. The digital data output lags the analog input sample by 3 sampling clock cycles. Power-up Initialization, this time is defined as the maximum number of clock cycles that are required to initialize the converter at power-up. The requirement arises from the need to initialize some dynamic circuits within the converter. Static Performance Definitions Differential Linearity Error, DNL, is the worst case deviation of a code width from the ideal value of 1 LSB. The converter is guaranteed to have no missing codes over the operating temperature range. Integral Linearity Error, INL, is the worst case deviation of a code center from a best fit straight line calculated from the measured data. Signal-to-Noise Ratio, SNR, is the measured RMS signal to RMS noise for a specified analog input frequency and sampling frequency. The noise is the RMS sum of all of the spectral components excluding the fundamental and the first five harmonics. Signal-to-Noise + Distortion Ratio, SINAD, is the measured RMS signal to RMS sum of all other spectral components below the Nyquist frequency excluding DC. Effective Number Of Bits, ENOB, the effective number of bits (ENOB) is calculated from the measured SINAD data. as follows: ENOB = (SINAD - 1.76 + VCORR) / 6.02, where: VCORR = 0.5dB. VCORR adjusts the ENOB for the amount the analog input signal is below full scale. 2nd and 3rd Harmonic Distortion, is the ratio of the RMS value of the 2nd and 3rd harmonic component, respectively, to the RMS value of the measured input signal. Analog Input Bandwidth, is the frequency at which the amplitude of the digitally reconstructed output has decreased 3dB below the amplitude of the input sine wave. The input sine wave has a peak-to-peak amplitude equal to the differential reference voltage. The bandwidth given is measured at the specified sampling frequency. 4-1548 HI5710A AMP HFA1135 HFA1245 HA5020 HFA1135: HFA1245: HA5020: HI5710A: HI5767/2/4: HSP9501: HSP48410: HSP48908: HSP48212: HSP43891: HSP43168: HSP43216: HI1171: HI3338: HI3050: HA2842: HFA1115: A/D HI5710A HI5767/2 HI5767/4 DSP/µP HSP9501 HSP48410 HSP48908 HSP48212 HSP43891 HSP43168 HSP43216 D/A HI1171 HI3050 HI3338 AMP HA5020 HA2842 HFA1115 350MHz Op Amp with Output Limiting Dual 350MHz Op Amp with Disable/Enable 100MHz Video Op Amp 10-Bit, 20 MSPS, A/D Converter 10-Bit, 20/40 MSPS, Low Power A/D Converter with Internal Reference Programmable Data Buffer Histogrammer/Accumulating Buffer, 10-Bit Pixel Resolution 2-D Convolver, 3 x 3 Kernal Convolution, 8-Bit Digital Video Mixer Digital Filter, 30MHz, 9-Bit Dual FIR Filter, 10-Bit, 33MHz/45MHz Digital Half Band Filter 8-Bit, 40MHz, Video D/A Converter 8-Bit, 50MHz, Video D/A Converter Triple 10-Bit, 50MHz, Video DAC High Output Current, Video Op Amp 350MHz Programmable Gain Buffer with Output Limiting CMOS Logic Available in HC, HCT, AC, ACT, and FCT. FIGURE 22. 10-BIT VIDEO IMAGING COMPONENTS AMP HFA3600 HFA3102 HFA3101 HFA1100 HFA3600: HFA3102: HFA3101: HFA1100: HI5710A: HI5767/2/4: HSP43168: HSP43216: HSP43891: HSP50016: HSP50110: HSP50210: HI5721: HI5780: HI20201: HI20203: HFA1115: A/D HI5710A HI5767/2 HI5767/4 DSP/µP HSP43168 HSP43216 HSP43891 HSP50016 HSP50110 HSP50210 D/A HI5721 HI20201 HI20203 HI5780 AMP HFA1115 Low Noise Amplifier/Mixer Dual Long-Tailed Pair Transistor Array Gilbert Cell Transistor Array 850MHz Op Amp 10-Bit, 20 MSPS, A/D Converter 10-Bit, 20/40 MSPS, Low Power A/D Converter with Internal Reference Dual FIR Filter, 10-Bit, 33MHz/45MHz Digital Half Band Filter Digital Filter, 30MHz, 9-Bit Digital Down Converter Digital Quadrature Tuner Digital Costas Loop 10-Bit, 100MHz, Communications D/A Converter 10-Bit, 80MHz CMOS D/A Converter 10-Bit, 160MHz, High Speed D/A Converter 8-Bit, 160MHz, High Speed D/A Converter 350MHz Programmable Gain Buffer with Output Limiting CMOS Logic Available in HC, HCT, AC, ACT, and FCT. FIGURE 23. 10-BIT COMMUNICATIONS COMPONENTS 4-1549 HI5710A All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 4-1550 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029