CXD2315Q 10-bit 80MSPS 1ch D/A Converter (Ultra-low Glitch Version) Description The CXD2315Q is a 1-ch 10-bit 80MSPS D/A converter for monitor and video. This IC achieves high specifications for the industrial and information equipment due to the reduction of the glitch energy. Features • 10-bit resolution • Maximum conversion rate 80MSPS • Differential linearity error ±0.5LSB • Low power consumption 150 mW (Max., When 80MSPS 200 Ω load, 2 Vp-p is output) • Pin-compatible with CXD2306Q • Single 5 V power supply • Built-in independent constant-voltage source • Ultra-low glitch • Stand-by function Structure Silicon gate CMOS IC 32 pin QFP (Plastic) Absolute Maximum Ratings (Ta=25 °C) • Supply voltage AVDD, DVDD 7 V • Input voltage (All pins) VIN VDD +0.5 to VSS –0.5 V • Output voltage (for each channel) IOUT 0 to 15 mA • Storage temperature Tstg –55 to +150 Recommended Operating Conditions • Supply voltage AVDD, AVSS 5.0 ± 0.25 DVDD, DVSS 5.0 ± 0.25 • Reference input voltage VREF 0.5 to 2.0 • Clock pulse width tpw1, tpw0 5.6 (min.) • Operating temperature Topr –20 to +85 °C V V V ns °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E95704D01 CXD2315Q Block Diagram (LSB) D0 30 4LSB'S CURRENT CELLS D1 31 D2 32 D3 1 D4 2 D5 3 25 AVSS LATCHES 23 IO DECODER 6MSB'S CURRENT CELLS D6 4 D7 5 D8 6 (MSB) D9 24 IO 22 VG DECODER 19 VREF 7 DVDD 28 CURRENT CELLS (FOR FULL SCALE) BLK 10 17 IREF DVDD 13 DVSS 15 DVSS 27 CLOCK GENERATOR 21 AVDD BIAS VOLTAGE GENERATOR BAND GAP REFERENCE CLK 9 20 AVDD VB 14 CE 11 18 SREF IO IO VG AVDD AVDD VREF SREF IREF Pin Configuration 24 23 22 21 20 19 18 17 AVss 25 16 NC NC 26 15 DVss DVss 27 14 VB DVDD 28 13 DVDD NC 29 12 NC D0 (LSB) 30 11 CE 27 to 15 Digital section 17 to 25 Analog section 4 5 6 7 8 NC 3 D9 (MSB) 2 D8 D3 1 D7 9 CLK D6 D2 32 D5 10 BLK D4 D1 31 —2— CXD2315Q Pin Description and Equivalent Circuit Pin No. Symbol I/O Equivalent circuit Description DVDD 30 to 32 1 to 7 30 D0 to D9 I Digital input. 30 pin D0 (LSB) to 7 pin D9 (MSB) to 7 DVSS 8, 12, 16, 26, 29 9 NC CLK — 10 BLK I No connection. Clock input. Blanking input. This is synchronized with the clock input signal. No signal (0 V output) at high and output state at low. Chip enable input. This is not synchronized with the clock input signal. No signal (0 V output) at high makes power consumption minimum. Digital power supply. DVDD 9 10 11 DVSS 11 CE 13, 28 DVDD — DVDD DVDD 14 VB Connect a capacitor of approximately 0.1 µF. O 14 DVSS 15, 27 DVSS — 17 IREF O Digital ground. AVDD AVDD 19 VREF I VG 17 AVDD AVss 19 AVSS 22 AVDD Reference current output. Connect resistance “RIR” which is 16 times output resistance “ROUT”. Reference voltage input. Sets output full scale value. 22 O AVSS —3— Connect a capacitor of approximately 0.1 µF. CXD2315Q Pin No. Symbol I/O Equivalent circuit Description AVDD Independent constant-voltage source output pin using band gap reference. Stable voltage independent of the fluctuation for supply voltage can be get by connecting to VREF. See Application Circuit 2 for details. 18 18 SREF O AVSS AVSS 20, 21 AVDD 23 IO — Analog VDD AVSS O 24 Inverted current output. Connect to GND normally. 24 Current output. Output can be retrieved by connecting resistance. The standard is 200 Ω. 23 IO AVSS 25 AVSS — Analog ground. —4— CXD2315Q (FCLK=80 MHz, AVDD=DVDD=5 V, ROUT=200 Ω, RIR=3.3 kΩ, VREF=2.0 V, Ta=25 °C) Electrical Characteristics Resolution Symbol n Conversion speed FCLK AVDD=DVDD=4.75 to 5.25 V Ta=–20 to +85 °C Integral non-linearity error Differential non-linearity error Precision guaranteed output voltage range Output full-scale voltage Output full-scale current Output offset voltage Glitch energy Differential gain Differential phase EL ED Endpoint Item Supply current Analog input resistance Input capacitance Digital input voltage Digital input current SREF output voltage Setup time Hold time Rise time Propagation delay time CE enable time ∗ CE disable time ∗ Measurement conditions Min. Typ. 10 Max. Unit bit 0 80 MSPS –1.5 –0.5 1.5 0.5 LSB LSB VOC 1.8 1.94 2.0 V VFS IFS VOS GE DG DP IDD ISTB RIN CI VIH VIL IIH IIL VSR ts th tr tPD tE tD 1.8 9.0 1.94 9.7 2.0 10 1 30 1.0 1.0 30 1 V mA mV pV•s % deg When D0 to D9= “0000000000” input CE= “L” CE= “H” VREF 1 9 AVDD=DVDD=4.75 to 5.25 V Ta=–20 to +75 °C AVDD=DVDD=4.75 to 5.25 V Ta=–20 to +75 °C 2.45 0.85 –5 1.0 3.0 3.0 5 CE= H→L CE= L→H ∗ When the external capacitor for the VGR,VGG and VGB pins are 0.1 µF. Electrical Characteristics Measurement Circuit Analog Input Resistance Measurement Circuit Digital Input Current } +5.25V AVDD, DVDD A CXD2315Q V AVSS, DVSS —5— mA MΩ pF V 5 µA 1.2 1.45 5 1 1 2 2 V ns ns ns ns ms ms CXD2315Q Maximum Conversion Rate Measurement Circuit 30 D0 (LSB) 10bit COUNTER with LATCH 0.1µ 7 D9 (MSB) 9 CLK AVDD 200 VG 22 VREF 19 10 BLK CLK 80MHz (max) SQUARE WAVE OSCILLOSCOPE IO 24 31 2V 5k AVss 11 CE IREF 17 14 VB 3.3k 0.1µ DC Characteristics Measurement Circuit 30 D0 (LSB) 0.1µ 7 D9 (MSB) 9 CLK AVDD 200 VG 22 VREF 19 10 BLK CLK 80MHz SQUARE WAVE DVM IO 24 31 CONTROLLER 2V 5k AVss 11 CE IREF 17 14 VB 3.3k 0.1µ Propagation Delay Time Measurement Circuit 30 D0 (LSB) OSCILLOSCOPE IO 24 31 0.1µ 7 D9 (MSB) FREQUENCY DEMULTIPLIER 9 CLK 10 BLK CLK 10MHz SQUARE WAVE Setup Time Hold Time Glitch Energy VREF 19 2V 5k IREF 17 3.3k 0.1µ Measurement Circuit 30 D0 (LSB) 10bit COUNTER with LATCH 0.1µ 7 D9 (MSB) 9 CLK 10 BLK 11 CE DELAY CONTROLLER IO 24 31 DELAY CONTROLLER CLK 1MHz SQUARE WAVE VG 22 AVss 11 CE 14 VB } AVDD 200 14 VB AVDD VG 22 VREF 19 2V 5k AVss IREF 17 3.3k 0.1µ —6— 200 OSCILLOSCOPE CXD2315Q Description of Operation Timing Chart tPW1 tPW0 CLK 1.5V ts th ts th ts th DATA tPD 100% 50% D/A OUT tPD tPD 0% I/O Correspondence Table (When 2.00 V output full-scale voltage) Input code MSB LSB 1 1 1 1 1 1 1 1 1 1 : 1 0 0 0 0 0 0 0 0 0 : 0 0 0 0 0 0 0 0 0 0 Output voltage 2.0 V 1.0 V 0V —7— CXD2315Q Application Circuit 1 R3 AVDD DVDD AVSS DVSS R4 C R1 R2 C 24 23 22 21 20 IO IO VG AVDD AVDD 19 18 VREF SREF IREF 17 25 AVss NC 16 26 NC DVss 15 27 DVss VB 14 C 28 DVDD DVDD 13 C 29 NC NC 12 30 D0 CE 11 31 D1 BLK 10 D3 D4 D5 D6 D7 D8 D9 CLK 9 NC 1 2 3 4 5 6 7 8 32 D2 Clock input • When 5.0V supply voltage (DVDD and AVDD) • Digital input from Pins 30 to 32 and Pins 1 to 7 • Pin 18 is left open when using normally • R1=200Ω • R2=3.3kΩ (resistance 16 times R1) (RIR) • R3=3.0kΩ • R4=2.0kΩ • C=0.1µF Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. —8— CXD2315Q Application Circuit 2 Cr C R1 AVDD DVDD AVSS DVSS R2 C 24 23 22 21 20 19 IO IO VG AVDD AVDD VREF 18 SREF 17 IREF 25 AVss NC 16 26 NC DVss 15 VB 14 27 DVss C DVDD 13 28 DVDD C 29 NC NC 12 30 D0 CE 11 31 D1 BLK 10 32 D2 D3 D4 D5 D6 D7 D8 D9 1 2 3 4 5 6 7 CLK 9 NC Clock input 8 • When 5.0V supply voltage (DVDD and AVDD) • Digital input from Pins 30 to 32 and Pins 1 to 7 • R1=200Ω • R2=2.0kΩ • C =0.1µF • Cr =4.7µF Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. —9— CXD2315Q Notes on Operation • Selecting the Output Resistance CXD2315Q is a current output type D/A converter. To create the output voltage, connect the resistor to the current output pin IO. Specifications: Output full-scale voltage VFS = 1.8 to 2.0 [V] Output full-scale current IFS = 10 or less [mA] Calculate the output resistance from VFS = IFS × ROUT. Connect a resistance sixteen times the output resistance to the reference current pin IREF. In some cases, as this value may not exist, a similar value can be used instead. Note that the VFS will be the following. VFS = VREF × 16 ROUT/R VREF is the voltage set at the VREF pin, ROUT is the resistor to be connected to the current output pin IO and RIR is the resistor to be connected to the IREF. Power consumption can be reduced by increasing the resistance, but this will on the contrary increase the glitch energy and data settling time. Set the best values according to the purpose of use. • Correlation between Data and Clock For the CXD2315Q to display the desired performance as a D/A converter, the data transmitted from outside and the clock must be synchronized properly. Adjust the setup time (ts) and hold time (th) as specified in “Electrical Characteristics”. • Power supply and ground Separate the analog and digital power supplies and grounds around the device to reduce noise effects. Bypass the power supply pin to each ground with a 0.1 µF ceramics capacitor as near to the pin as possible for both the digital and analog signals. • Latch up Analog and digital power supply must be able to share the same power supply of the board. This is to prevent latch up caused by potential difference between the two pins when the power is turned on. • IREF pin The IREF pin is very sensitive to improve the AC characteristics. Pay attention for capacitance component not to attach to this pin because its output may become unstable. • VG pin It is recommended to use a 1 µF capacitor to improve the AC characteristics though the typical capacitance value externally connected to the VG pin is 0.1 µF. • SREF SREF is an independent regulated voltage source. By connecting the SREF pin and the VREF pin, stable output amplitudes that do not depend on fluctuations in the power supply can be obtained. In this case, as described above, VFS = VSR × 16ROUT/RIR, set the VFS according to RIR. VSR is the output voltage of the SREF pin. Do not use this pin as a reference power supply for other ICs because this is dedicated for the VG pin of the CXD2315Q. —10— CXD2315Q • IO pin The IO pin is the inverted current output pin described in the Pin Description. The sum of the currents output from the IO pin and the IO pin becomes the constant value for any input data. However, the performances such as the linearity error of the IO pin output current is not guaranteed. GE (Glitch energy) GE, described in the CXD2315Q, is a spike noise which appears synchronizing with the clock falling edge when the input data (for 1 to 1024 input) changes to 128, 256, 384, 512, 640, 768, 896, and 1024. Fig. 1 shows the change state of GE for the staircase wave output, and Fig. 2 shows the repetitive output waveform where the GE appears. These figures exhibit the difference of this IC from the conventional device. Analog output [V] 2.0 Conventional device 1.0 CXD2315Q 0 512 1024 Digital input [V] CLK Fig. 1. Change of GE for staircase wave output Conventional device (GE typ.=200pV-s) CXD2315Q (GE typ.=10pV-s) Fig. 2. Repetitive output waveform where GE appears (for 200 Ω, 2 Vp-p output) The CXD2315Q reduces the GE much shown in Fig.s 1 and 2. —11— CXD2315Q Latch Up Prevention The CXD2315Q is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in the voltage rising time of AVDD (Pins 20 and 21) and DVDD (Pins 13 and 28), when power supply is ON. 1. Correct usage a. When analog and digital supplies are from different sources DVDD AVDD 20 21 13 AVDD +5V +5V C 28 DVDD C CXD2315Q AVSS DVSS 15 25 AVSS DIGITAL IC 27 DVSS b. When analog and digital supplies are from a common source (i) DVDD 20 21 13 AVDD 28 DVDD +5V C C CXD2315Q AVSS DVSS 15 25 AVSS DIGITAL IC 27 DVSS (ii) DVDD 20 13 28 21 AVDD DVDD +5V C CXD2315Q C AVSS 25 DVSS 15 27 AVSS DVSS —12— DIGITAL IC CXD2315Q 2. Example when latch up easily occurs a. When analog and digital supplies are from different sources DVDD AVDD 20 21 13 AVDD +5V +5V C 28 DVDD C CXD2315Q AVSS DVSS 15 25 AVSS DIGITAL IC 27 DVSS b. When analog and digital supplies are from common source (i) DVDD AVDD 21 13 28 AVDD DVDD 20 +5V C CXD2315Q C AVSS DVSS 15 25 AVSS DIGITAL IC 27 DVSS (ii) DVDD AVDD 20 21 13 AVDD 28 DVDD +5V C CXD2315Q AVSS AVSS 25 DVSS 15 27 DVSS —13— DIGITAL IC CXD2315Q 2.0 Output full-scale voltage VFS [V] Output full-scale voltage VFS [V] Example of Representative Characteristics 1.0 1.95 1.93 ∆V = 0.20mV/°C 1.0 0 2.0 0 –25 0 25 50 75 Ambient temperature Ta [°C] Fig. 4. Ambient temperature vs. Output full-scale voltage 30 1.25 Supply current IDD [mA] SREF Output voltage VSR [V] Reference voltage VREF [V] Fig. 3. Reference voltage vs.Output full-scale voltage 1.15 20 ∆V = –0.7mV/°C 0 –25 0 25 50 0 75 1 10 20 30 40 Output frequency Fo [MHz] Fig. 6. Output frequency vs. Supply current Ambient temperature Ta [°C] Fig. 5. Ambient temperature vs. SREF output voltage Standard Measurement Conditions and Description • ADDD=DVDD=5V • VREF=2.0V • ROUT=200Ω • RIR=3.3kΩ • FCLK=80MHz • Ta=25°C • Fig. 4 includes the temperature characteristics of external metal film resistor. • Input data in Fig. 6=all “0” and “1” of rectangular wave; clock frequency=80MHz. —14— CXD2315Q Package Outline Unit : mm 32PIN QFP (PLASTIC) 9.0 ± 0.2 24 0.1 + 0.35 1.5 – 0.15 + 0.3 7.0 – 0.1 17 16 32 9 (8.0) 25 1 + 0.2 0.1 – 0.1 0.8 + 0.15 0.3 – 0.1 0.24 M + 0.1 0.127 – 0.05 0° to 10° PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-32P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE QFP032-P-0707 LEAD MATERIAL 42 ALLOY PACKAGE MASS 0.2g JEDEC CODE —15— 0.50 8