an9822

HI5767EVAL1 Evaluation Board User’s Manual
TM
Application Note
January 1999
Description
AN9822
adjustable by way of a potentiometer. This allows the effects
of sample clock duty cycle on the HI5767 to be observed.
The HI5767EVAL1 evaluation board allows the circuit
designer to evaluate the performance of the Intersil HI5767
monolithic 10-bit 20/40/60MSPS analog-to-digital converter
(ADC). As shown in the Evaluation Board Functional Block
Diagram, the evaluation board includes sample clock
generation circuitry, a single-ended to differential analog
input amplifier configuration, an on board external variable
reference voltage generator and a digital data output
header/connector. The digital data outputs are conveniently
provided for easy interfacing to a ribbon connector or logic
probes. In addition, the evaluation board includes some
prototyping area for the addition of user designed custom
interfaces or circuits.
The analog input signal is also connected through an SMA
type RF connector, J1, and applied to a single-ended to
differential analog input amplifier. This input is AC-coupled
and terminated in 50Ω allowing for connection to most
laboratory signal generators. Also, provisions for a
differential RC lowpass filter are incorporated on the output
of the differential amplifier to limit the broadband noise going
into the HI5767 converter.
The converters’ digital data outputs along with two phases
of the sample clock (CLK and CLK) are provided at the
output header/connector. With this output configuration the
digital data output transitions seen at the I/O
header/connector are essentially time aligned with the
rising edge of the sampling clock (CLK) or the falling edge
of the out of phase sampling clock (CLK).
The sample clock generator circuit accepts the external
sampling signal through an SMA type RF connector, J2. This
input is AC-coupled and terminated in 50Ω allowing for
connection to most laboratory signal generators. In addition,
the duty cycle of the clock driving the A/D converter is
Refer to the component layout and the evaluation board
electrical schematic for the following discussions.
Evaluation Board Functional Block Diagram
SAMPLE
CLOCK
INPUT
J2
+5VD
50Ω
CLK
CLOCK
OUT
1.2V
BANDGAP
VOLTAGE
REFERENCE
ANALOG
INPUT
BIAS
TEE
+2.5V
VAR
GAIN
VREFIN
VREFOUT
J1
CLK
CLK
G = +1
VIN+
DIGITAL
DATA
OUT
(D0 - D9)
10
D0-D9
50Ω
VIN-
G = -1
DGND
AGND
HI5767
+5VD
+5VA
3-1
-5VA
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Copyright
© Intersil Corporation 2000
Application Note 9822
External Reference Voltage Generator,
VREFOUT and VREFIN
The HI5767 has an internal reference voltage generator,
therefore no external reference voltage is required. The
evaluation board, however, offers the ability to use the
converters’ internal reference voltage, VREFOUT, or the on
board external variable reference voltage generator.
The external variable reference voltage circuitry is
implemented using the Intersil ICL8069 low voltage, 1.2V,
bandgap reference (D1) sourcing a non-inverting variable
gain operational amplifier circuit based on the Intersil
HA5127 ultra-low noise precision operational amplifier (U1).
Potentiometer VR1 is used to adjust the output voltage level
of this external voltage reference. With this the user is able
to observe the effects of reference voltage variations on the
converters performance. Turning VR1 in a clockwise (CW)
direction will decrease the external reference voltage while
turning VR1 in a counterclockwise (CCW) direction will
decrease the external reference voltage.
Selection of the reference voltage to be used by the
converter is accomplished by placing the P3 header jumper
across the appropriate pins. The converters’ internal
reference voltage generator, VREFOUT, must be connected
to VREFIN when using the converters internal reference and
is selected by placing the P3 header jumper across P3-2 and
P3-3. Alternately, if it is desired to use the on board external
variable reference voltage generator, selection of this option
is done by placing the P3 header jumper across P3-1 and
P3-2. See Appendix A, Board Layout for the location of the
P3 reference voltage selection header.
Analog Input
The fully differential analog input of the HI5767 A/D can be
configured in various ways depending on the signal source
and the required level of performance.
Differential Analog Input Configuration
A fully differential connection (Figure 1) will yield the best
performance from the HI5767 A/D converter. Since the
HI5767 is powered off a single +5V supply, the analog input
must be biased so it lies within the analog input common
mode voltage range of 0.25V to 4.75V. Figure 2 illustrates
the differential analog input common mode voltage, VDC,
range that the converter will accommodate. The
performance of the converter does not change significantly
with the value of the analog input common mode voltage.
VIN+
VIN
HI5767
VDC
-VIN
VIN -
FIGURE 1. AC COUPLED DIFFERENTIAL INPUT
+5V
VIN+
0.5VP-P
VINVDC = 4.75V
+5V
FIGURE 2A.
VIN+
VIN0.5VP-P
0.25V < VDC < 4.75V
FIGURE 2B.
VIN+
VIN0.5VP-P
0V
VDC = 0.25V
0V
FIGURE 2C.
FIGURE 2. DIFFERENTIAL ANALOG INPUT COMMON MODE
VOLTAGE RANGE
A DC bias voltage source, VDC , equal to 3.0V (typical), is
made available to the user to help simplify circuit design
when using an AC coupled differential input. This low output
impedance voltage source is not designed to be a reference
but makes an excellent DC bias source and stays well within
the analog input common mode voltage range over
temperature.
For the AC coupled differential input (Figure 1) and with
VREFIN connected to VREFOUT, full scale is achieved when
the VIN and -VIN input signals are 0.5VP-P, with -VIN being
180 degrees out of phase with VIN . The converter will be at
positive full scale when the VIN+ input is at VDC + 0.25V and
the VIN- input is at VDC - 0.25V (VIN+ - VIN- = +0.5V).
Conversely, the converter will be at negative full scale when
the VIN+ input is equal to VDC - 0.25V and VIN- is at
VDC + 0.25V (VIN+ - VIN- = -0.5V).
It should be noted that overdriving the analog input beyond
the ±0.5V fullscale input voltage range will not damage the
converter as long as the overdrive voltage stays within the
converters analog supply voltages. In the event of an
overdrive condition the converter will recover within one
sample clock cycle.
3-2
Application Note 9822
The evaluation board provides a single-ended to differential
analog front-end for converting the typical laboratory signal
generators 50Ω single-ended output to a differential input
signal for the converters differential-in-differential-out
sample-and-hold front end. The evaluation boards analog
front end is implemented utilizing two Intersil HFA1109
450MHz, low power, current feedback video operational
amplifiers. One operational amplifier of the analog frontend, U3, is configured in a unity gain configuration, AV = 1,
driving the non-inverting input of the converter while the
second operational amplifier, U4, is configured in an
inverting-gain of one, AV = -1, configuration driving the
inverting input of the converter. The input of this analog
front-end, RF SMA connector J1, is AC coupled and
provides a termination impedance of 50Ω. It should be
pointed out that provision for increasing the gain of the
single-ended to differential analog front-end has been
provided. For the non-inverting amplifier a location for R3 is
present but not utilized for the unity gain configuration but
could be installed to change the gain of this amplifier. Of
course, it would also be necessary to match the magnitude
of the new gain in the inverting amplifier signal path. It is
recommended that the user refer to the HFA1109 data
sheets and application notes for specific details on making
any changes to these amplifier configurations.
Evaluation Board Layout and Power
Supplies
The HI5767 evaluation board is a four layer board with a
layout optimized for the best performance of the converter.
This application note includes an electrical schematic of the
evaluation board, a component parts list, a component
placement layout drawing and reproductions of the various
board layers used in the board stack-up. The user should
feel free to copy the layout in their application.
The HI5767 monolithic A/D converter has been designed
with separate analog and digital supply and ground pins to
keep digital noise out of the analog signal path. The
evaluation board provides separate low impedance analog
and digital ground planes on layer 2. Since the analog and
digital ground planes are connected together at a single
point where the power supplies enter the board, DO NOT tie
them together back at the power supplies.
The analog and digital supplies are also kept separate on
the evaluation board and should be driven by clean linear
regulated supplies. The external power supplies are
hooked up with the twisted pair wires soldered to the plated
through holes marked +5VAIN, +5VA1IN, -5VAIN, +5VDIN,
+5VD1IN, +5VD2IN, AGND and DGND near the
prototyping area. +5VDIN, +5VD1IN and +5VD2IN are
digital supplies and are returned to DGND. +5VAIN,
+5VA1IN and -5VAIN are the analog supplies and are
returned to AGND. Table 1 lists the operational supply
voltages, typical current consumption and the evaluation
3-3
board circuit function being powered. Single supply
operation of the converter is possible but the overall
performance of the converter may degrade.
TABLE 1. HI5767EVAL1 EVALUATION BOARD POWER
SUPPLIES
POWER
SUPPLY
NOMINAL
VALUE
CURRENT
(TYP)
FUNCTION(S)
SUPPLIED
+5VAIN
5.0V ±5%
26mA
Analog Input and
External Reference
Voltage Operational
Amplifiers, Bandgap
Reference
-5VAIN
-5.0V ±5%
24mA
Analog Input and
External Reference
Voltage Operational
Amplifiers
+5VA1IN
5.0V ±5%
50mA
A/D AVCC
+5VDIN
5.0V ±5%
63mA
Sample Clock
Generation
+5VD1IN
5.0V ±5%
20mA
A/D DVCC1
+5VD2IN
3.0V ±10%
5mA
A/D DVCC2
Sample Clock Driver
In order to ensure rated performance of the HI5767, the duty
cycle of the sample clock should be held at 50% ±5%. It must
also have low phase noise and operate at standard TTL levels.
It can be difficult to find a low phase noise generator that will
provide a 60MHz squarewave at TTL logic levels.
Consequently, the HI5767EVAL1 evaluation board is
designed with a logic inverter (U5) acting as a voltage
comparator to generate the sampling clock for the HI5767
when a sinewave (<±1.5V) is applied to the AC-coupled, 50Ω
terminated CLK input through SMA type RF connector, J2,
of the evaluation board. The sample clock sinewave is AC
coupled into the input of the inverter and a discrete bias tee
is used to bias the sinewave around the trigger level of the
inverter’s input. A potentiometer (VR2) varies the DC bias
voltage added to the sinewave input allowing the user to
adjust the duty cycle of the sampling clock to obtain the best
performance from the ADC and to evaluate the effects of
sample clock duty cycle on the performance of the converter.
The trigger level for the sample clock input to the HI5767
converter is approximately 1.5V. Therefore, the duty cycle of
the sampling clock should be measured at the 1.5V trigger
level of the HI5767 sample clock input pin.
The sinewave to logic level comparator drives a series of
additional inverters that provide isolation between the three
sample clocks used on the evaluation board. One clock is
used to drive the converter sample clock input pin and the
other two provide CLK and CLK at the data output
header/connector, P2. The clock/data relationship at the P2
output connector is as follows. CLK has rising edges aligned
with digital data transitions and CLK has rising edges
aligned mid-bit.
Application Note 9822
The data corresponding to a particular analog input sample
will be available at the digital outputs of the HI5767 after the
data latency (7 cycles) plus the HI5767 digital data output
delay.
The sample clock and digital output data signals are made
available through two connectors contained on the evaluation
board. Line drivers are not provided for the digital output data
and it should be pointed out that the load presented to the
converter digital output data signals, D0 - D9, should not
exceed the data sheet CMOS drive limits and a load
capacitance of 10pF. The P1 96-pin I/O connector allows the
evaluation board to be interfaced to the DSP evaluation
boards available from Intersil. The digital output data and
sample clock can also be accessed by clipping the test leads
of a logic analyzer or data acquisition system onto the
header/connector pins of connector P2.
The A/D converters OE control input pin allows the digital
output data bus of the converter to be switched to a threestate high impedance mode. This feature enables the
testing and debugging of systems which are utilizing one or
more converters. This three-state control signal is not
intended for use as an enable/disable function on a
common data bus and could result in possible bus
contention issues. The A/D converters OE control input pin
is controlled by the installation or removal of a shunt, JP1,
contained on the evaluation board. Installation of JP1
forces the OE control input pin low for normal operation
while removal of JP1 allows the digital output data bus of
the converter to be switched to a three-state high
impedance mode.
HI5767 Performance Characterization
Dynamic testing is used to evaluate the performance of the
HI5767 A/D converter. Among the tests performed are
Signal-to-Noise and Distortion Ratio (SINAD), Signal-toNoise Ratio (SNR), Total Harmonic Distortion (THD),
Spurious Free Dynamic Range (SFDR) and InterModulation
Distortion (IMD).
Figure 4 shows the test system used to perform dynamic
testing on high-speed ADCs at Intersil. The clock (CLK)
and analog input (VIN) signals are sourced from low phase
noise HP8662A synthesized signal generators that are
phase locked to each other to ensure coherence. The
output of the signal generator driving the ADC analog input
is bandpass filtered to improve the harmonic distortion of
3-4
the analog input signal. The comparator on the evaluation
board will convert the sine wave CLK input signal to a
square wave at TTL logic levels to drive the sample clock
input of the HI5767. The ADC data is captured by a logic
analyzer and then transferred over the GPIB bus to the PC.
The PC has the required software to perform the Fast
Fourier Transform (FFT) and do the data analysis.
Coherent testing is recommended in order to avoid the
inaccuracies of windowing. The sampling frequency and
analog input frequency have the following relationship:
FI/FS = M/N, where FI is the frequency of the input analog
sinusoid, FS is the sampling frequency, N is the number of
samples, and M is the number of cycles over which the
samples are taken. By making M an integer and odd
number (1, 3, 5, ...) the samples are assured of being
nonrepetitive.
Refer to the HI5767 data sheet for a complete list of test
definitions and the results that can be expected using the
evaluation board with the test setup shown. Evaluating the
part with a reconstruction DAC is only suggested when
doing bandwidth or video testing.
HP8662A
HP8662A
REF
BANDPASS
FILTER
VIN
CLK
COMPARATOR
VIN
HI5767
CLK
DIGITAL DATA OUTPUT
HI5767EVAL1
EVALUATION BOARD
14
DAS9200
GPIB
PC
FIGURE 3. HIGH-SPEED A/D PERFORMANCE TEST SYSTEM
Application Note 9822
Appendix A Board Layout
FIGURE 4. HI5767EVAL1 EVALUATION BOARD PARTS LAYOUT (NEAR SIDE)
FIGURE 5. HI5767EVAL1 EVALUATION BOARD COMPONENT NEAR SIDE (LAYER 1)
3-5
Application Note 9822
Appendix A Board Layout
(Continued)
FIGURE 6. HI5767EVAL1 EVALUATION BOARD GROUND PLANE LAYER (LAYER 2)
FIGURE 7. HI5767EVAL1 EVALUATION BOARD POWER PLANE LAYER (LAYER 3)
3-6
Application Note 9822
Appendix A Board Layout
(Continued)
FIGURE 8. HI5767EVAL1 EVALUATION BOARD COMPONENT FAR SIDE (LAYER 4)
FIGURE 9. HI5767EVAL1 EVALUATION BOARD PARTS LAYOUT (FAR SIDE)
3-7
C35 +
4.7µF
C33
0.1µF
D0 - D9, CLK4 (CLK)
TO P1
U2
1
+5VD1
+
2
C26
4.7µF
3
C9
0.1µF
5
6
EXT
VREF
P3
7
8
9
VIN+
10
VIN-
11
VDC
12
13
+5VA1
+
14
+
D0
D1
DVCC1
D2
DGND1
D3
AVCC
D4
AGND
DVCC2
VREFIN
VREFOUT
HI5767
CLK
DGND2
VIN+
D5
VIN-
D6
VDC
D7
AGND
D8
AVCC
D9
OE
DFS
27
P2
D0 1
D1 3
2
6
23
D2 5
D3 7
22
D4 9
10
21
D5 11
12
20
D6 13
14
19
D7 15
16
18
D8 17
18
17
D9 19
20
21
22
23
24
26
25
24
CLK1
4
8
16
15
CLK4
R11
R10
C30
4.7µF
C32
0.1µF
C36 C34 C43
0.1µF 0.1µF 4.7µF
C40
0.1µF
JP1
4.99K
4.99K
+5VD
CLK3
JP2
Application Note 9822
FIGURE 10. A/D CONVERTER
4
C29
0.1µF
DVCC1
DGND1
28
Appendix B Schematic Diagrams
3-8
+5VD2
Application Note 9822
Appendix B Schematic Diagrams
(Continued)
+5VA
1
J1
C12
0.1µF
+
C10
0.1µF
C31
4.7µF
7
3
VIN
NC
+
8
C11
0.1µF
V+
R5
56.2
6
NC
NC
2
-
V5
VIN+
R4
10
U3
HFA1109
4
-5VA
C13
0.1µF
R15
100
C39
+ 4.7µF
R9
0
VDC
R14
499
C16
A/RpF
R3
A/R
R17 499
+5VA
1
7
2
NC
-
C38
4.7µF
8
6
NC
NC
V-
+
VINC15
0.1µF
U4
5
3
C41 C37
0.01µF 0.1µF
R8
10
V+
R6
499
R7
249
R16
100
+
C14
0.1µF
HFA1109
4
-5VA
C17
0.1µF
C44
+ 4.7µF
FIGURE 11. SINGLE-ENDED TO DIFFERENTIAL (OPERATIONAL AMPLIFIER) ANALOG FRONT END
+5VA
+
C3
0.1µF
C5
4.7µF
+5VA
1
R1
4.99K
7
1.2V
3
8
+ C1
4.7µF
4
V+
NC
NC
D1
ICL8069CCBA
2
C6
0.1µF
NC
+
-
V5
4
C2
0.1µF
C4
0.1µF
R2
249
VR1
1.0K
1(CCW)
2
+
C8
0.1µF
8
6
U1
HA5127
C28
4.7µF
R13
0
+
C7
0.1µF
-5VA
C25
+ 4.7µF
R12
499
VEXT
3(CW)
VEXT
FIGURE 12. EXTERNAL REFERENCE VOLTAGE GENERATION CIRCUIT
3-9
2.5V
C27
4.7µF
EXT VREF
Application Note 9822
Appendix B Schematic Diagrams
(Continued)
+5VD
+
C51
0.1µF
J2
C18
C42
4.7µF 0.1µF
U5
C47
0.1µF
AC04
13
U5
1
12
14
2
CLK1
CLK IN
R19
56.2
7
L1
1.5µH
+
U5
9
VR2
1.0K
AC04
U5
11
3(CW)
C46
0.1µF
R18
100
C49
C50
4.7µF 0.1µF
(CLK)
8
1(CCW)
2
+5VD
AC04
10
CLK3
AC04
U5
3
(CLK)
4
AC04
U5
5
6
CLK4
(CLK)
AC04
FIGURE 13. SAMPLE CLOCK DRIVER CIRCUIT
AGND
TEST
POINT
TP1
TP3
DGND
TEST
POINT
TP2
TP4
E1
E9 E10
E2
FB5
+5VAIN
FB1
+5VA
+
AGND
C53
4.7µF
C52
0.1µF
+5VDIN
+5VD
+
DGND
(ANALOG INPUT AND REFERENCE
VOLTAGE GENERATOR OP-AMPS,
BANDGAP REFERENCE)
E11 E12
E5
+
AGND
E7
+5VD1IN
C54
C55
4.7µF 0.1µF
E3
FB4
+
C48
0.1µF
+5VD1
(A/D DVCC1)
E4
(ANALOG INPUT AND REFERENCE
VOLTAGE GENERATOR OP-AMPS,
BANDGAP REFERENCE)
+5VD2IN
DGND
+
FIGURE 14. ANALOG AND DIGITAL POWER SUPPLIES
3-10
C24
C23
4.7µF 0.1µF
FB2
-5VA
C45
4.7µF
+
DGND
AGND AND DGND TIE TOGETHER
AT A SINGLE POINT WHERE
THE POWER SUPPLIES
ENTER THE PWB
-5VAIN
AGND
FB3
+5VA1 (A/D AVCC)
E8
(SAMPLE CLOCK
GENERATOR)
E6
FB6
+5VA1IN
C20
C19
4.7µF 0.1µF
C22
C21
4.7µF 0.1µF
+5VD2
(+5V/+3V)
(A/D DVCC2)
Application Note 9822
Appendix B Schematic Diagrams
(Continued)
P1C
D1
D2
D4
D6
D8
CLK4 (CLK)
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
D0 - D9, CLK4 (CLK)
FIGURE 15. 96 PIN I/O CONNECTOR
3-11
P1A
D0
D3
D5
D7
D9
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
Application Note 9822
Appendix C Parts List
REFERENCE DESIGNATOR
QTY
---
1
Printed Wiring Board
R4, R8
2
10Ω, 1/10W, 805 Chip, 1%
R6, R12, R14, R17
4
499Ω, 1/10W, 805 Chip, 1%
R5, R19
2
56.2Ω, 1/10W, 805 Chip, 1%
R3
1
A/RΩ, 1/10W, 805 Chip, 1%
R15, R16, R18
3
100Ω, 1/10W, 805 Chip, 1%
R9, R13
2
0.0Ω, 1/10W, 805 Chip, 1%
R1, R10, R11
3
4.99kΩ, 1/4W, 805 Chip, 5%
R2, R7
2
249Ω, 1/10W, 805 Chip, 1%
VR1, VR2
2
1kΩ Trim Pot
C1, C5, C18, C20, C22, C24, C25, C26, C27, C28, C30,
C31, C35, C38, C39, C43, C44, C45, C49, C53, C55
21
4.7µF Chip Tant Cap, 10WVDC, 20%, EIA Case A
C2, C3, C4, C6, C7, C8, C9, C10, C11, C12, C13, C14,
C15, C17, C19, C21, C23, C29, C32, C33, C34, C36, C37,
C40, C41, C42, C46, C47, C48, C50, C51, C52, C54
33
0.1µF Cer Cap, 50WVDC, 10%, 805 Case, Y5V Dielectric
C16
1
A/R pF Cer Cap, 50WVDC, 10%, 805 Case
L1
1
1.5µH Chip Inductor, 1210 Case
FB1-6
6
10µH Ferrite Bead
J1,2
2
SMA Straight Jack PCB Mount
---
4
Protective Bumper
JP1,2
2
1x2 Header
JPH1,2
2
1x2 Header Jumper
P3
1
1x2 Header
PH3
1
1x2 Header Jumper
P2
1
2x12 Header
TP1,2,3,4
4
Test Point
U2
1
Intersil HI5767 10-Bit 20/40/60MSPS A/D Converter with Internal
Voltage Reference
U3,4
2
Intersil HFA1109IB 450MHz, Low Power, Current Feedback Video
Operational Amplifier
U1
1
Intersil HA9P5127-5 8.5MHz, Ultra-Low Noise Precision Operational
Amplifier
U5
1
Intersil CD74HC04M High Speed CMOS Logic Hex Inverter
D1
1
Intersil ICL8069CCBA Low Voltage Bandgap Reference
P1
6
64-Pin Eurocard RT Angle Receptacle
3-12
DESCRIPTION
Application Note 9822
Appendix D HI5767 Theory of Operation
The HI5767 is a 10-bit fully differential sampling pipeline A/D
converter with digital error correction logic. Figure 16 depicts
the circuit for the front end differential-in-differential-out
sample-and-hold (S/H). The switches are controlled by an
internal sampling clock which is a non-overlapping two phase
signal, Φ1 and Φ2 , derived from the master sampling clock.
During the sampling phase, Φ1 , the input signal is applied to
the sampling capacitors, CS . At the same time the holding
capacitors, CH , are discharged to analog ground. At the
falling edge of Φ1 the input signal is sampled on the bottom
plates of the sampling capacitors. In the next clock phase, Φ2 ,
the two bottom plates of the sampling capacitors are
connected together and the holding capacitors are switched to
the op-amp output nodes. The charge then redistributes
between CS and CH completing one sample-and-hold cycle.
The front end sample-and-hold output is a fully-differential,
sampled-data representation of the analog input. The circuit
not only performs the sample-and-hold function but will also
convert a single-ended input to a fully-differential output for
the converter core. During the sampling phase, the VIN pins
see only the on-resistance of a switch and CS . The relatively
small values of these components result in a typical full power
input bandwidth of 250MHz for the converter.
As illustrated in the functional block diagram, Figure 17, eight
identical pipeline subconverter stages, each containing a twobit flash converter and a two-bit multiplying digital-to-analog
converter, follow the S/H circuit with the ninth stage being a two
bit flash converter. Each converter stage in the pipeline will be
sampling in one phase and amplifying in the other clock phase.
Each individual subconverter clock signal is offset by 180
degrees from the previous stage clock signal resulting in
alternate stages in the pipeline performing the same operation.
The output of each of the eight identical two-bit
subconverter stages is a two-bit digital word containing a
supplementary bit to be used by the digital error correction
logic. The output of each subconverter stage is input to a
digital delay line which is controlled by the internal
sampling clock. The function of the digital delay line is to
time align the digital outputs of the eight identical two-bit
subconverter stages with the corresponding output of the
ninth stage flash converter before applying the eighteen bit
result to the digital error correction logic. The digital error
correction logic uses the supplementary bits to correct any
error that may exist before generating the final ten bit digital
data output of the converter.
Because of the pipeline nature of this converter, the digital
data representing an analog input sample is output to the
digital data bus on the 7th cycle of the clock after the
analog sample is taken. This time delay is specified as the
data latency. After the data latency time, the digital data
representing each succeeding analog sample is output
during the following clock cycle. The digital output data is
synchronized to the external sampling clock by a double
3-13
buffered latching technique. The digital output data is
available in two’s complement or offset binary format
depending on the state of the Data Format Select (DFS)
control input.
Internal Reference Voltage Output, VREFOUT
The HI5767 is equipped with an internal reference voltage
generator, therefore, no external reference voltage is
required. VREFOUT must be connected to VREFIN when
using the internal reference voltage.
An internal bandgap reference voltage followed by an
amplifier/buffer generates the precision +2.5V reference
voltage used by the converter. A 4:1 array of substrate
PNPs generates the “delta-VBE” and a two-stage op amp
closes the loop to create an internal +1.25V bandgap
reference voltage. This voltage is then amplified by a wideband uncompensated operational amplifier connected in a
gain-of-two configuration. An external, user-supplied,
0.1µF capacitor connected from the VREFOUT output pin to
analog ground is used to set the dominant pole and to
maintain the stability of the operational amplifier.
Reference Voltage Input, VREFIN
The HI5767 is designed to accept a +2.5V reference voltage
source at the VREFIN input pin. Typical operation of the
converter requires VREFIN to be set at +2.5V. The HI5767 is
tested with VREFIN connected to VREFOUT yielding a fully
differential analog input voltage range of ±0.5V.
The user does have the option of supplying an external
+2.5V reference voltage. As a result of the high input
impedance presented at the VREFIN input pin, 2.5kΩ
typically, the external reference voltage being used is only
required to source 1mA of reference input current. In the
situation where an external reference voltage will be used
an external 0.1µF capacitor must be connected from the
VREFOUT output pin to analog ground in order to maintain
the stability of the internal operational amplifier.
In order to minimize overall converter noise it is
recommended that adequate high frequency decoupling be
provided at the reference voltage input pin, VREFIN .
.
Φ1
VIN +
Φ1
Φ1
Φ1
CS
VOUT +
-
Φ2
VIN -
CH
+
VOUT -
CS
Φ1
CH
Φ1
FIGURE 16. ANALOG INPUT SAMPLE-AND-HOLD
Application Note 9822
Appendix D HI5767 Theory of Operation (Continued)
VDC
CLOCK
BIAS
CLK
VINVREFOUT
VIN+
REFERENCE
VREFIN
S/H
STAGE 1
DFS
2-BIT
FLASH
2-BIT
DAC
OE
+
∑
DVCC2
X2
D9 (MSB)
D8
D7
D6
DIGITAL DELAY
AND
DIGITAL ERROR
CORRECTION
STAGE 8
D5
D4
D3
2-BIT
FLASH
2-BIT
DAC
D2
D1
+
∑
D0 (LSB)
-
X2
DGND2
STAGE 9
2-BIT
FLASH
AVCC
AGND
DVCC1
DGND1
FIGURE 17. HI5767 FUNCTIONAL BLOCK DIAGRAM
3-14
Application Note 9822
Appendix E HI5767 Pin Descriptions
PIN NO.
NAME
DESCRIPTION
1
DVCC1
Digital Supply (+5.0V)
2
DGND1
Digital Ground
3
DVCC1
Digital Supply (+5.0V)
4
DGND1
Digital Ground
5
AVCC
Analog Supply (+5.0V)
6
AGND
Analog Ground
7
VREFIN
+2.5V Reference Voltage Input
8
VREFOUT
9
VIN+
Positive Analog Input
10
VIN-
Negative Analog Input
11
VDC
DC Bias Voltage Output
12
AGND
Analog Ground
13
AVCC
Analog Supply (+5.0V)
14
OE
Digital Output Enable Control Input
15
DFS
Data Format Select Input
16
D9
Data Bit 9 Output (MSB)
17
D8
Data Bit 8 Output
18
D7
Data Bit 7 Output
19
D6
Data Bit 6 Output
20
D5
Data Bit 5 Output
21
DGND2
22
CLK
23
DVCC2
24
D4
Data Bit 4 Output
25
D3
Data Bit 3 Output
26
D2
Data Bit 2 Output
27
D1
Data Bit 1 Output
28
D0
Data Bit 0 Output (LSB)
+2.5V Reference Voltage Output
Digital Ground
Sample Clock Input
Digital Output Supply (+3.0V or +5.0V)
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