an9785

HI5905EVAL2 Evaluation Board User’s Manual
TM
Application Note
January 1999
AN9785
Description
adjustable by way of a potentiometer. This allows the effects
of sample clock duty cycle on the HI5905 to be observed.
The HI5905EVAL2 evaluation board allows the circuit
designer to evaluate the performance of the Intersil HI5905
monolithic 14-bit, 5MSPS analog-to-digital converter (ADC).
As shown in the Evaluation Board Functional Block Diagram,
the evaluation board includes sample clock generation
circuitry, a single-ended to differential analog input amplifier
configuration and digital data output latches/buffers. The
buffered digital data outputs are conveniently provided for
easy interfacing to a ribbon connector or logic probes. In
addition, the evaluation board includes some prototyping area
for the addition of user designed custom interfaces or circuits.
The analog input signal is also connected through an SMA
type RF connector, J1, and applied to a single-ended to
differential analog input amplifier. This input is AC-coupled
and terminated in 50Ω allowing for connection to most
laboratory signal generators. Also, provisions for a
differential RC lowpass filter is incorporated on the output of
the differential amplifier to limit the broadband noise going
into the HI5905 converter.
The digital data output latches/buffers consist of a pair of
74ALS574A D-type flip-flops. With this digital output
configuration the digital output data transitions seen at the
I/O connector are essentially time aligned with the rising
edge of the sampling clock.
The sample clock generator circuit accepts the external
sampling signal through an SMA type RF connector, J2. This
input is AC-coupled and terminated in 50Ω allowing for
connection to most laboratory signal generators. In addition,
the duty cycle of the clock driving the A/D converter is
Evaluation Board Functional Block Diagram
TTL COMPARATOR
CLK IN
J2
CLOCK
OUT
(CLK)
50Ω
+5VD
-5VD
CLK
VREFOUT
G = +1
VREFIN
VIN+
ANALOG
IN
D0-D13
J1
14
14
D Q
G = -1
50Ω
>
VIN-
DIGITAL
DATA
OUT
(D0 - D13)
HI5905
DGND
AGND
+5VD
3-1
-5VD
+5VA
-5VA
1-888-INTERSIL or 321-724-7143
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Intersil and Design is a trademark of Intersil Corporation.
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Copyright
© Intersil Corporation 2000
Application Note 9785
Reference Generator, VROUT and VRIN
The HI5905 has an internal reference voltage generator,
therefore no external reference voltage is required. The eval
board, however, offers the ability to use the internal or an
external reference. VROUT must be connected to VRIN when
using the internal reference. Internal to the converter, two
reference voltages of 1.3V and 3.3V are generated making
for a fully differential analog input signal range of ±2V.
The HI5905 can be used with an external reference. The
converter requires only one external reference voltage
connected to the VRIN pin with VROUT left open. The
evaluation board is configured with VROUT connected to VRIN
through a 0Ω resistor, R4. If it is desired to evaluate the
performance of the converter utilizing an externally provided
reference voltage, R4 can be removed and the alternate
reference voltage can be brought in through twisted pair wire or
coaxial cable. The latter would be the recommended method
since it would provide the greatest immunity to externally
coupled noise voltages. In order to minimize overall converter
noise it is recommended that adequate high frequency
decoupling be provided at the reference input pin, VRIN .
The difference between the converter's two internally
generated voltage references is 2V. For the AC coupled
differential input (Figure 1), if VIN is a 2VP-P sinewave with -VIN
being 180 degrees out of phase with VIN, the converter will be
at positive full scale when the VIN+ input is at VDC + 1V and the
VIN- input is at VDC - 1V (VIN+ - VIN- = +2V). Conversely, the
ADC will be at negative full scale when the VIN+ input is equal
to VDC - 1V and VIN- is at VDC + 1V (VIN+ - VIN- = -2V).
It should be noted that overdriving the analog input beyond
the ±2.0V fullscale input voltage range will not damage the
converter as long as the overdrive voltage stays within the
converters analog supply voltages. In the event of an
overdrive condition the converter will recover within one
sample clock cycle.
+5V
VIN+
2.0VP-P
+5V
FIGURE 2A.
VIN+
Analog Input
VIN2.0VP-P
The fully differential analog input of the HI5905 A/D can be
configured in various ways depending on the signal source
and the required level of performance.
1.0V < VDC < 4.0V
FIGURE 2B.
Differential Analog Input Configuration
A fully differential connection (Figure 1) will yield the best
performance from the HI5905 A/D converter. Since the HI5905
is powered off a single +5V supply, the analog input must be
biased so it lies within the analog input common mode voltage
range of 1.0V to 4.0V. Figure 2 illustrates the differential analog
input common mode voltage range that the converter will
accommodate. The performance of the ADC does not change
significantly with the value of the common mode voltage.
VINVDC = 4.0V
VIN+
VIN2.0VP-P
VDC = 1.0V
0V
0V
FIGURE 2C.
FIGURE 2. DIFFERENTIAL ANALOG INPUT COMMON MODE
VOLTAGE RANGE
Evaluation Board Layout and
Power Supplies
FIGURE 1. AC COUPLED DIFFERENTIAL INPUT
The HI5905 evaluation board is a four layer board with a
layout optimized for the best performance of the ADC. This
application note includes an electrical schematic of the
evaluation board, a component parts list, a component
placement layout drawing and reproductions of the various
board layers used in the board stack-up. The user should
feel free to copy the layout in their application. Refer to the
component layout and the evaluation board electrical
schematic for the following discussions.
A 2.3V DC bias voltage source, VDC, half way between the top
and bottom internally generated reference voltages, is made
available to the user to help simplify circuit design when using a
differential input. This low output impedance voltage source is
not designed to be a reference but makes an excellent bias
source and stays within the analog input common mode
voltage range over temperature. The DC voltage source has a
temperature coefficient of about +200ppm/oC.
The HI5905 monolithic A/D converter has been designed
with separate analog and digital supply and ground pins to
keep digital noise out of the analog signal path. The
evaluation board provides separate low impedance analog
and digital ground planes on layer 2. Since the analog and
digital ground planes are connected together at a single
point where the power supplies enter the board, DO NOT tie
them together back at the power supplies.
VIN+
VIN
HI5905
VDC
-VIN
VIN -
3-2
Application Note 9785
The analog and digital supplies are also kept separate on
the evaluation board and should be driven by clean linear
regulated supplies. The external power supplies are hooked
up with the twisted pair wires soldered to the plated through
holes marked +5VAIN, +5VAIN1, -5VAIN, +5VDIN,
+5VD1IN, +5VD2IN, -5VDIN, AGND and DGND near the
analog prototyping area. +5VDIN, +5VD1IN, +5VD2IN
and -5VDIN are digital supplies and are returned to DGND.
+5VAIN, +5VAIN1 and -5VAIN are the analog supplies and
are returned to AGND. Table 1 lists the operational supply
voltages, typical current consumption and the evaluation
board circuit function being powered. Single supply
operation of the converter is possible but the overall
performance of the converter may degrade.
TABLE 1. HI5905EVAL2 EVALUATION BOARD POWER
SUPPLIES
POWER
SUPPLY
NOMINAL
VALUE
CURRENT
(TYP)
FUNCTION(S)
SUPPLIED
+5VAIN
5.0V ±5%
80mA
Op Amps, A/D AVCC
-5VAIN
-5.0V ±5%
30mA
Op Amps
+5VDIN
5.0V ±5%3
60mA
CLK Comparator,
Inverter
D0-D13 D-FF’s
+5VD1IN
5.0V ±5%
14mA
A/D DVCC1
+5VD2IN
5.0V ±5%
6mA
A/D DVCC2
-5VDIN
-5.0V ±5%
3mA
CLK
Comparator
Sample Clock Driver, Timing and I/O
In order to ensure rated performance of the HI5905, the duty
cycle of the sample clock should be held at 50% ±5%. It
must also have low phase noise and operate at standard
TTL levels.
A voltage comparator (U3) with TTL output levels is provided
on the evaluation board to generate the sampling clock for
the HI5905 when a sinewave (< ±3V) or squarewave clock is
applied to the CLK input (J2) of the evaluation board. A
potentiometer (VR1) is provided to allow the user to adjust
the duty cycle of the sampling clock to obtain the best
performance from the ADC and to allow the user to
investigate the effects of expected duty cycle variations on
the performance of the converter. The HI5905 clock input
trigger level is approximately 1.5V. Therefore, the duty cycle
of the sampling clock should be measured at this 1.5V
trigger level. Test point TP2 provides a convenient point to
monitor the sample clock duty cycle and make any required
adjustments.
Figure 3 shows the sample clock and digital data timing
relationship for the evaluation board. The data
corresponding to a particular sample will be available at the
digital data outputs of the HI5905 after the data latency time,
tLAT, of 4 sample clock cycles plus the HI5905 digital data
output delay, tOD. Table 2 lists the values that can be
expected for the indicated timing delays. Refer to the HI5905
data sheet for additional timing information.
SINEWAVE CLK IN
(J2)
tPD1
HI5905 SAMPLE
CLOCK INPUT
(CLK AT TP2)
HI5905 DIGITAL
DATA OUTPUT
(D0 - D13)
tOD
DATA N-1
DATA N
CLOCK OUT
(CLK AT TP1, P2-C20 OR P2-31)
tPD2
DIGITAL DATA OUTPUTS
(74ALS574)
DATA N-1
DATA N
FIGURE 3. EVALUATION BOARD CLOCK AND DATA TIMING RELATIONSHIPS
3-3
Application Note 9785
TABLE 2. TIMING SPECIFICATIONS
PARAMETER
DESCRIPTION
TYP
tOD
HI5905 Digital Output Data Delay
50ns
tPD1
U4 Prop Delay
4.5ns
tPD2
U2/3 Prop Delay
9ns
The sample clock and digital output data signals are made
available through two connectors contained on the
evaluation board. The line buffering provided by the data
output latches allows for driving long leads or analyzer
inputs. These data latches are not necessary for the digital
output data if the load presented to the converter does not
exceed the data sheet load limits of 100µA and 15pF. The P2
I/O connector allows the evaluation board to be interfaced to
the DSP evaluation boards available from Intersil.
Alternatively, the digital output data and sample clock can
also be accessed by clipping the test leads of a logic
analyzer or data acquisition system onto the I/O pins of
connector header P1.
bus to the PC. The PC has the required software to perform the
Fast Fourier Transform (FFT) and do the data analysis.
Coherent testing is recommended in order to avoid the
inaccuracies of windowing. The sampling frequency and
analog input frequency have the following relationship: FI/FS
= M/N, where FI is the frequency of the input analog
sinusoid, FS is the sampling frequency, N is the number of
samples, and M is the number of cycles over which the
samples are taken. By making M an integer and odd number
(1, 3, 5, ...) the samples are assured of being nonrepetitive.
Refer to the HI5905 data sheet for a complete list of test
definitions and the results that can be expected using the
evaluation board with the test setup shown. Evaluating the
part with a reconstruction DAC is only suggested when
doing bandwidth or video testing.
HP8662A
BANDPASS
FILTER
HI5905 Performance Characterization
Dynamic testing is used to evaluate the performance of the
HI5905 A/D converter. Among the tests performed are
Signal-to-Noise and Distortion Ratio (SINAD), Signal-toNoise Ratio (SNR), Total Harmonic Distortion (THD),
Spurious Free Dynamic Range (SFDR) and InterModulation
Distortion (IMD).
Figure 4 shows the test system used to perform dynamic
testing on high-speed ADCs at Intersil. The clock (CLK) and
analog input (VIN) signals are sourced from low phase noise
HP8662A synthesized signal generators that are phase locked
to each other to ensure coherence. The output of the signal
generator driving the ADC analog input is bandpass filtered to
improve the harmonic distortion of the analog input signal. The
comparator on the evaluation board will convert the sine wave
CLK input signal to a square wave at TTL logic levels to drive
the sample clock input of the HI5905. The ADC data is
captured by a logic analyzer and then transferred over the GPIB
3-4
HP8662A
REF
VIN
CLK
COMPARATOR
VIN
HI5905
CLK
DIGITAL DATA OUTPUT
HI5905EVAL2
EVALUATION BOARD
14
DAS9200
GPIB
PC
FIGURE 4. HIGH-SPEED A/D PERFORMANCE TEST SYSTEM
Application Note 9785
HI5905EVAL2 Typical Performance (Input Amplitude at -0.5dBFS)
75
12
11
-THD (dB)
ENOB (BITS)
65
10
9
55
8
7
45
1
10
INPUT FREQUENCY (MHz)
100
1
10
INPUT FREQUENCY (MHz)
100
FIGURE 5. EFFECTIVE NUMBER OF BITS (ENOB) vs INPUT
FREQUENCY
FIGURE 6. TOTAL HARMONIC DISTORTION (THD) vs INPUT
FREQUENCY
75
90
80
-2HD (dB)
SINAD (dB)
65
70
55
60
45
1
10
INPUT FREQUENCY (MHz)
50
100
FIGURE 7. SINAD vs INPUT FREQUENCY
1
10
INPUT FREQUENCY (MHz)
100
FIGURE 8. SECOND HARMONIC DISTORTION (2HD) vs
INPUT FREQUENCY
80
65
70
SNR (dB)
-3HD (BITS)
75
55
45
60
1
10
INPUT FREQUENCY (MHz)
FIGURE 9. SNR vs INPUT FREQUENCY
3-5
50
100
1
10
INPUT FREQUENCY (MHz)
100
FIGURE 10. THIRD HARMONIC DISTORTION (3HD) vs INPUT
FREQUENCY
Application Note 9785
Appendix A Board Layout
FIGURE 11. HI5905EVAL2 EVALUATION BOARD PARTS LAYOUT (NEAR SIDE)
FIGURE 12. HI5905EVAL2 EVALUATION BOARD COMPONENT NEAR SIDE (LAYER 1)
3-6
Application Note 9785
Appendix A Board Layout
(Continued)
FIGURE 13. HI5905EVAL2 EVALUATION BOARD GROUND PLANE LAYER (LAYER 2)
FIGURE 14. HI5905EVAL2 EVALUATION BOARD POWER PLANE LAYER (LAYER 3)
3-7
Application Note 9785
Appendix A Board Layout
(Continued)
FIGURE 15. HI5905EVAL2 EVALUATION BOARD COMPONENT FAR SIDE (LAYER 4)
FIGURE 16. HI5905EVAL2 EVALUATION BOARD PARTS LAYOUT (FAR SIDE)
3-8
FB6
VCC
+
C18
4.7µF
C17
0.1µF
C14
0.1µF
R5
4.99K
+5VD2
+
C16
4.7µF
C15
0.1µF
CLK
D0 - D13, CLK
C13
0.1µF
U2
34
2
U1
3
NC
35
NC
36
D2
37
D1
38
D0
39
NC
40
CLK
42
43
41
DVCC1
NC
DGND1
NC
1
JP1
1
DVCC1
C11
0.1µF
R6
4.99K
44
+
C12
4.7µF
D3
4
33
5
NC
D4
32
3
DGND1
D5
31
7
D6
30
8
D7
29
9
NC
28
DVCC2
27
2
DGND2
26
3
25
4
4
5
6
7
8
NC
AVCC
HI5905
AGND
NC
NC
D8
VIN-
10
VIN-
D9
VDC
11
10
1
5
24
6
23
NC
7
8
9
22
D10
21
D11
20
NC
D12
19
18
17
D13
NC
AVCC
16
15
14
13
NC
VDC
AGND
VIN+
VRIN
9
VROUT
VIN+
6
10
OE
D0
D1
VCC
20
Q0 19
Q1 18
Q2 17
Q3 16
D3
‘ALS574
Q4 15
D4
Q5 14
D5
Q6 13
D6
Q7 12
D7
11
CP
GND
20
VCC
OE
Q0 19
D0
Q1 18
D1
Q2 17
D2
Q3 16
D3
‘ALS574
Q4 15
D4
Q5 14
D5
Q6 13
D6
Q7 12
D7
11
CP
GND
D1
D2
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D13
CLK
U3
R4
0
P1
D0
Application Note 9785
2
12
3-9
+5VD1
CLK
C6
0.1µF
+5VA
C10
4.7µF
+
1
C9
0.1µF
C7
0.1µF
U7
ALS04
CLK
3
Appendix B Schematic Diagrams
+5VD
U7
ALS04
2
4
Application Note 9785
Appendix B Schematic Diagrams
(Continued)
+5VA
1
C37
ANALOG 0.1µF
IN
J1
7
3
NC
+
6
V+
V-
-
C1
0.1µF
8
V+
R13
56.2
2
+
C39
4.7µF
C38
0.1µF
V-
5
VIN+
R16
10
U5
OPA628AU
4
-5VA
C40
0.1µF
+
R2
100
C41
4.7µF
R12
0
VDC
R15
22.1
C3
A/R
+
R14
A/R
R17
499
+5VA
1
2
NC
-
R18
499
V+
8
3
+
V-
OPA628U
4
-5VA
C45
0.1µF
C44
+ 4.7µF
+5VD
+
1
J2
C20
0.1µF
2
CLK IN
3
-5VD
C22
4.7µF +
2
3(CW)
TP2
V+
7
+
3-10
C25
0.1µF
CLK
Q
LE
8
GND
V5
U4
6
MAX9686BCSA
4
-
C21
0.1µF
R11
249
1 (CCW)
-5VD
+5VD
R8
249
C24
4.7µF
C23
0.1µF
Q
R7
49.9
R9
249
VR1
5K
C4
0.1µF
VINC2
0.1µF
U6
5
C5
4.7µF
R19
10
6
V+
VR20
249
+
C42
4.7µF
C43
0.1µF
7
R3
100
C26
0.1µF
R10
249
CLK
TP1
Application Note 9785
Appendix B Schematic Diagrams
(Continued)
P2C
D1
D3
D5
D6
D8
D10
D12
CLK
P2A
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
A1
A2
D0
A3
D2 A4
D4
A5
A6
D7
A7
D9
A8
D11
A9
D13
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
D0 - D13, CLK
VCC
C8
0.1µF
U7
U7
5
14
6
7
U7
ALS04
3-11
8
ALS04
ALS04
11
9
U7
10
13
ALS04
12
E2
E3
FB1
+5VAIN
+
AGND
C28
0.1µF
C27
4.7µF
+5VA
(A/D AVCC, OP-AMPS)
E4
FB2
+5VD
+5VDIN
+
DGND
C29
4.7µF
C30
0.1µF
(COMPARATOR, D-FF AND INVERTER VIA LPF)
AGND AND DGND TIE TOGETHER
AT A SINGLE POINT WHERE
THE POWER SUPPLIES
ENTER THE PWB
-5VA
(OP-AMPS)
-5VAIN
AGND
+
E5
FB7
C46
4.7µF
C47
0.1µF
E6
FB3
+5VD1IN
+
DGND
E7
C31
4.7µF
E8
C32
0.1µF
FB4
+5VD2
+5VD2IN
TP3
TP4
+
DGND
E9
C33
4.7µF
E10
C34
0.1µF
(A/D DVCC2)
FB5
-5VDIN
DGND
+5VD1
(A/D DVCC1)
+
C35
4.7µF
C36
0.1µF
-5VD
(COMPARATOR)
Application Note 9785
E12
(Continued)
E11
Appendix B Schematic Diagrams
3-12
E1
Application Note 9785
Appendix C Parts List
REFERENCE
DESIGNATOR
QTY
-
1
Printed Wiring Board
R16, R19
2
10Ω, 1/10W
805 Chip, 1%
R17, R18
2
499Ω, 1/10W
805 Chip, 1%
R13
1
56.2Ω, 1/10W
805 Chip, 1%
R14
1
A/RΩ, 1/10W
805 Chip, 1%
R15
1
22.1Ω, 1/10W
805 Chip, 1%
R2, R3
2
100Ω, 1/10W
805 Chip, 1%
R4, R12
2
0.0Ω, 1/4W
805 Chip, 5%
R5, R6
2
4.99kΩ, 1/10W
805 Chip, 1%
R7
1
49.9Ω, 1/10W
805 Chip, 1%
R8, R9, R10, R11, R20
5
249Ω, 1/10W
805 Chip, 1%
VR1
1
5kΩ Trim Pot
C5, C10, C12, C16, C18,
C22, C24, C27, C29, C31,
C33, C35, C39, C41, C42,
C44, C46
17
4.7µF Chip Tant Cap,
10WVDC, 20%, EIA Case A
C1, C2, C4, C6, C7, C8,
C9, C11, C13, C14, C15,
C17, C20, C21, C23, C25,
C26, C28, C30, C32, C34,
C36, C37, C38, C40, C43,
C45, C47
28
0.1µF Cer Cap, 50WVDC,
10%, 805 Case, Y5V
Dielectric
C3
1
A/R pF Cer Cap, 50WVDC,
10%, 805 Case
FB1-7
7
10µH Ferrite Bead
J1, J2
2
SMA Straight Jack PCB
Mount
-
5
Protective Bumper
JP1
1
1x2 Header
JPH1
1
1x2 Header Jumper
P1
1
2x17 Header
TP1, 2, 3, 4
4
Test Point
U1
1
Intersil HI5905IN, 14-Bit 5
MSPS A/D Converter
U4
1
Ultrafast Voltage
Comparator
U2, U3
2
Octal D-type Flip-flop
3-13
DESCRIPTION
REFERENCE
DESIGNATOR
QTY
U5, U6
2
Op-amp
U7
1
Hex Inverter
P2
DESCRIPTION
64-Pin Eurocard RT Angle
Receptacle
Appendix D HI5905 Theory of Operation
The HI5905 is a 14-bit fully differential sampling pipelined A/D
converter with digital error correction. Figure 17 depicts the
internal circuit for the converters front-end differential-indifferential-out sample-and-hold (S/H). The sampling switches
are controlled by internal sampling clock signals which consist
of two phase non-overlapping clock signals, φ1 and φ2,
derived from the master clock (CLK) driving the converter.
During the sampling phase, φ1, the input signal is applied to
the sampling capacitors, CS. At the same time the holding
capacitors, CH, are discharged to analog ground. At the falling
edge of φ1 the input analog signal is sampled on the bottom
plates of the sampling capacitors. In the next clock phase, φ2,
the two bottom plates of the sampling capacitors are
connected together and the holding capacitors are switched to
the op amp output nodes. The charge then redistributes
between CS and CH, completing one sample-and-hold cycle.
The output of the sample-and-hold is a fully-differential,
sampled-data representation of the analog input. The circuit
not only performs the sample-and-hold function, but can also
convert a single-ended input to a fully-differential output for
the converter core. During the sampling phase, the VIN pins
see only the on-resistance of the switches and CS. The
relatively small values of these components result in a typical
full power input bandwidth of 100MHz for the converter.
As illustrated in the HI5905 Functional Block Diagram and
the timing diagram contained in Figure 18, three identical
pipeline subconverter stages, each containing a four-bit
flash converter, a four-bit digital-to-analog converter and an
amplifier with a voltage gain of 8, follow the S/H circuit with
the fourth stage being only a 4-bit flash converter. Each
converter stage in the pipeline will be sampling in one
phase and amplifying in the other clock phase. Each
individual sub-converter clock signal is offset by 180
degrees from the previous stage clock signal, with the
result that alternate stages in the pipeline will perform the
same operation. The output of each of the three identical
four-bit subconverter stages is a four-bit digital word
containing a supplementary bit to be used by the digital
error correction logic. The output of each subconverter
stage is input to a digital delay line which is controlled by
the internal clock. The function of the digital delay line is to
time align the digital outputs of the three identical four-bit
subconverter stages with the corresponding output of the
fourth stage flash converter before inputting the sixteen bit
result into the digital error correction logic. The digital error
Application Note 9785
correction logic uses the supplementary bits to correct any
error that may exist before generating the final fourteen-bit
digital data output (D0-D14) of the converter.
φ1
Because of the pipeline nature of this converter, the digital
data representing an analog input sample is presented on
the digital data output bus on the 4th cycle of the clock after
the analog sample is taken. This delay is specified as the
data latency. After the data latency time, the data
representing each succeeding analog sample is output on
the following clock pulse. The output data is synchronized to
the external sampling clock with a data latch and is
presented in offset binary format.
φ1
VIN +
CS
φ2
VIN -
φ1
φ1
CH
VOUT +
+
VOUT -
CS
CH
φ1
φ1
FIGURE 17. ANALOG INPUT SAMPLE-AND-HOLD
ANALOG
INPUT
CLOCK
INPUT
SN-1
HN-1
HN
SN
SN+1
HN+1
SN+2
HN+2
SN+3
HN+3
SN+4
HN+4
SN+5
HN+5
SN+6
HN+6
INPUT
S/H
1ST
STAGE
2ND
STAGE
B1, N-1
B2, N-2
3RD
STAGE
4TH
STAGE
B1, N
B2, N-1
B3, N-2
B4, N-3
5TH
STAGE
DATA
OUTPUT
B1, N+1
B2, N
B3, N-1
B4, N-2
B1, N+2
B2, N+1
B3, N
B4, N-1
B2, N+2
B3, N+1
B4, N
B5, N-3
B5, N-2
B5, N-1
DN-4
DN-3
DN-2
B1, N+3
B2, N+3
B3, N+2
B4, N+1
B5, N
DN-1
B5, N+1
DN
NOTES:
1. SN: N-th sampling period.
2. HN: N-th holding period.
3. BM, N: M-th stage digital output corresponding to N-th sampled input.
4. DN: Final data output corresponding to N-th sampled input.
FIGURE 18. HI5905 INTERNAL CIRCUIT TIMING
B1, N+5
B2, N+4
B3, N+3
B4, N+2
tLAT
3-14
B1, N+4
B3, N+4
B4, N+3
B5, N+2
B5, N+3
DN+1
DN+2
Application Note 9785
HI5905 Functional Block Diagram
BIAS
VDC
CLOCK
VINVIN+
REF
S/H
CLK
VROUT
VRIN
STAGE 1
DVCC2
4-BIT
FLASH
4-BIT
DAC
+
∑
D13 (MSB)
-
D12
D11
X8
D10
STAGE 4
4-BIT
FLASH
4-BIT
DAC
DIGITAL DELAY
AND
DIGITAL ERROR CORRECTION
D9
D8
D7
D6
D5
D4
+
D3
∑
D2
X8
D1
D0 (LSB)
STAGE 5
4-BIT
FLASH
AVCC
3-15
AGND
DGND2
DVCC1
DGND1
Application Note 9785
Appendix E Pin Descriptions
PIN #
NAME
1
NC
2
DESCRIPTION
PIN #
NAME
DESCRIPTION
No Connection
23
NC
No Connection
NC
No Connection
24
D9
Data Bit 9 Output
3
DGND1
Digital Ground
25
D8
Data Bit 8 Output
4
NC
No Connection
26
DGND2
Digital Ground
5
AVCC
Analog Supply (5.0V)
27
DVCC2
Digital Supply (5.0V)
6
AGND
Analog Ground
28
NC
No Connection
7
NC
No Connection
29
D7
Data Bit 7 Output
8
NC
No Connection
30
D6
Data Bit 6 Output
9
VIN+
Positive Analog Input
31
D5
Data Bit 5 Output
10
VIN-
Negative Analog Input
32
D4
Data Bit 4 Output
11
VDC
DC Bias Voltage Output
33
D3
Data Bit 3 Output
12
NC
No Connection
34
NC
No Connection
13
VROUT
Reference Voltage Output
35
NC
No Connection
14
VRIN
Reference Voltage Input
36
D2
Data Bit 2 Output
15
AGND
Analog Ground
37
D1
Data Bit 1 Output
16
AVCC
Analog Supply (5.0V)
38
D0
Data Bit 0 Output (LSB)
17
NC
No Connection
39
NC
No Connection
18
D13
Data Bit 13 Output (MSB)
40
CLK
Input Clock
19
D12
Data Bit 12 Output
41
DVCC1
Digital Supply (5.0V)
20
D11
Data Bit 11 Output
42
DGND1
Digital Ground
21
D10
Data Bit 10 Output
43
DVCC1
Digital Supply (5.0V)
22
NC
No Connection
44
NC
No Connection
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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