DATASHEET

16-Bit, 250MSPS/200MSPS/130MSPS ADC
ISLA216P
Features
The ISLA216P is a family of low power, high performance
16-bit analog-to-digital converters. Designed with Intersil’s
proprietary FemtoCharge™ technology on a standard CMOS
process, the family supports sampling rates of up to
250MSPS. The ISLA216P is part of a pin-compatible portfolio
of 12 to 16-bit A/Ds with maximum sample rates ranging from
130MSPS to 500MSPS.
• Single supply 1.8V operation
A serial peripheral interface (SPI) port allows for extensive
configurability, as well as fine control of various parameters
such as gain and offset.
Digital output data is presented in selectable LVDS or CMOS
formats. The ISLA216P is available in a 72-contact QFN
package with an exposed paddle. Operating from a 1.8V
supply, performance is specified over the full industrial
temperature range (-40°C to +85°C).
Key Specifications
16-BIT
250 MSPS
ADC
RESETN
NAPSLP
AVSS
December 10, 2012
FN7574.2
DIGITAL
ERROR
CORRECTION
SPI
CONTROL
1
- SPI Programmable fine gain and offset control
- Support for multiple ADC synchronization
- Optimized output timing
• Nap and sleep modes
- 200µs Sleep wake-up time
• Data output clock
• DDR LVDS-compatible or LVCMOS outputs
• Software defined radios
• Broadband communications
• High-performance data acquisition
• Communications test equipment
MODEL
RESOLUTION
SPEED
(MSPS)
ISLA216P25
16
250
ISLA216P20
16
200
CLKOUTP
ISLA216P13
16
130
CLKOUTN
ISLA214P50
14
500
ISLA214P25
14
250
ISLA214P20
14
200
ISLA214P13
14
130
ISLA212P50
12
500
ISLA212P25
12
250
ISLA212P20
12
200
ISLA212P13
12
130
D[14:0]N
OVSS
+
–
VCM
• Multi-ADC support
• Radar array processing
D[14:0]P
RLVDS
VINN
CSB
SCLK
SDIO
SDO
SHA
• Programmable built-in test patterns
Applications
OVDD
CLKDIVRSTN
CLKDIVRSTP
CLKDIV
AVDD
VINP
• 700MHz Bandwidth
Pin-Compatible Family
CLOCK
MANAGEMENT
CLKN
• 75fs Clock jitter
• Selectable Clock Divider
• SNR @ 250/200/130MSPS
- 75.0/76.6/77.5dBFS fIN = 30MHz
- 72.1/72.6/72.4dBFS fIN = 363MHz
• SFDR @ 250/200/130MSPS
- 87/91/96dBc fIN = 30MHz
- 81/80/82dBc fIN = 363MHz
• Total Power Consumption = 786mW @ 250MSPS
CLKP
• Clock duty cycle stabilizer
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISLA216P
Pin Configuration - LVDS MODE
AVDD
AVDD
AVDD
SDIO
SCLK
CSB
SDO
OVSS
D0P
D0N
OVDD
OVSS
D2P
D2N
DNC
DNC
D4P
D4N
ISLA216P
(72 LD QFN)
TOP VIEW
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
DNC
1
54 DNC
DNC
2
53 DNC
NAPSLP
3
52 D6P
VCM
4
51 D6N
AVSS
5
50 DNC
AVDD
6
49 DNC
AVSS
7
48 CLKOUTP
VINN
8
47 CLKOUTN
VINN
9
46 RLVDS
VINP 10
45 OVSS
VINP 11
44 D8P
AVSS 12
43 D8N
AVDD 13
42 DNC
AVSS 14
41 DNC
CLKDIV 15
40 D10P
IPTAT 16
39 D10N
Thermal Pad Not Drawn to Scale,
Consult Mechanical Drawing
for Physical Dimensions
DNC 17
Connect Thermal Pad to AVSS
38 DNC
RESETN 18
28
29
30
31
32
OVDD
DNC
DNC
D14N
D14P
OVDD
33
34
35
36
D12P
27
D12N
26
DNC
25
DNC
24
OVSS
AVDD
23
CLKDIVRSTN
AVDD
22
CLKDIVRSTP
21
CLKN
20
CLKP
19
AVDD
37 DNC
Pin Descriptions - 72 Ld QFN, LVDS Mode
PIN NUMBER
LVDS PIN NAME
1, 2, 17, 28, 29, 33, 34, 37,
38, 41, 42, 49, 50, 53, 54,
57, 58
DNC
Do Not Connect
6, 13, 19, 20, 21, 70, 71, 72
AVDD
1.8V Analog Supply
5, 7, 12, 14
AVSS
Analog Ground
27, 32, 62
OVDD
1.8V Output Supply
26, 45, 61, 65
OVSS
Output Ground
3
NAPSLP
2
LVDS PIN FUNCTION
Tri-Level Power Control (Nap, Sleep modes)
FN7574.2
December 10, 2012
ISLA216P
Pin Descriptions - 72 Ld QFN, LVDS Mode
(Continued)
PIN NUMBER
LVDS PIN NAME
LVDS PIN FUNCTION
4
VCM
Common Mode Output
8, 9
VINN
Analog Input Negative
10, 11
VINP
Analog Input Positive
15
CLKDIV
Tri-Level Clock Divider Control
16
IPTAT
18
RESETN
22, 23
CLKP, CLKN
24, 25
CLKDIVRSTP, CLKDIVRSTN
30
D14N
DDR Logical Bits 14, 15 Complement
31
D14P
DDR Logical Bits 14, 15 True
35
D12N
DDR Logical Bits 12, 13 Complement
36
D12P
DDR Logical Bits 12, 13 True
39
D10N
DDR Logical Bits 10, 11 Complement
40
D10P
DDR Logical Bits 10, 11 True
43
D8N
DDR Logical Bits 8, 9 Complement
44
D8P
DDR Logical Bits 8, 9 True
46
RLVDS
47, 48
CLKOUTN, CLKOUTP
51
D6N
DDR Logical Bits 6, 7 Complement
52
D6P
DDR Logical Bits 6, 7 True
55
D4N
DDR Logical Bits 4, 5 Complement
56
D4P
DDR Logical Bits 4, 5 True
59
D2N
DDR Logical Bits 2, 3 Complement
60
D2P
DDR Logical Bits 2, 3 True
63
D0N
DDR Logical Bits 0, 1 Complement
64
D0P
DDR Logical Bits 0, 1 True
66
SDO
SPI Serial Data Output
67
CSB
SPI Chip Select (active low)
68
SCLK
SPI Clock
69
SDIO
SPI Serial Data Input/Output
Exposed Paddle
AVSS
Analog Ground
3
Temperature Monitor (Output current proportional to absolute temperature)
Power On Reset (Active Low)
Clock Input True, Complement
Synchronous Clock Divider Reset True, Complement
LVDS Bias Resistor (Connect to OVSS with 1%10kΩ)
LVDS Clock Output Complement, True
FN7574.2
December 10, 2012
ISLA216P
Pin Configuration - CMOS MODE
AVDD
AVDD
AVDD
SDIO
SCLK
CSB
SDO
OVSS
D0
DNC
OVDD
OVSS
D2
DNC
DNC
DNC
D4
DNC
ISLA216P
(72 LD QFN)
TOP VIEW
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
DNC
1
54 DNC
DNC
2
53 DNC
NAPSLP
3
52 D6
VCM
4
51 DNC
AVSS
5
50 DNC
AVDD
6
49 DNC
AVSS
7
48 CLKOUT
VINN
8
47 DNC
VINN
9
46 RLVDS
VINP 10
45 OVSS
VINP 11
44 D8
AVSS 12
43 DNC
AVDD 13
42 DNC
AVSS 14
41 DNC
CLKDIV 15
40 D10
39 DNC
IPTAT 16
Thermal Pad Not Drawn to Scale,
Consult Mechanical Drawing
for Physical Dimensions
27
28
29
30
31
32
DNC
DNC
DNC
D14
OVDD
33
34
35
36
D12
26
37 DNC
DNC
25
38 DNC
DNC
24
OVDD
AVDD
23
OVSS
AVDD
22
CLKDIVRSTN
21
CLKDIVRSTP
20
CLKN
19
AVDD
RESETN 18
CLKP
Connect Thermal Pad to AVSS
DNC
DNC 17
Pin Descriptions - 72 Ld QFN, CMOS Mode
PIN NUMBER
CMOS PIN NAME
1, 2, 17, 28, 29, 30, 33, 34,
35, 37, 38, 39, 41, 42, 43,
47, 49, 50, 51, 53, 54, 55,
57, 58, 59, 63
DNC
Do Not Connect
6, 13, 19, 20, 21, 70, 71, 72
AVDD
1.8V Analog Supply
5, 7, 12, 14
AVSS
Analog Ground
27, 32, 62
OVDD
1.8V Output Supply
26, 45, 61, 65
OVSS
Output Ground
3
NAPSLP
4
CMOS PIN FUNCTION
Tri-Level Power Control (Nap, Sleep modes)
FN7574.2
December 10, 2012
ISLA216P
Pin Descriptions - 72 Ld QFN, CMOS Mode
PIN NUMBER
CMOS PIN NAME
4
VCM
Common Mode Output
8, 9
VINN
Analog Input Negative
10, 11
VINP
Analog Input Positive
15
CLKDIV
(Continued)
CMOS PIN FUNCTION
Tri-Level Clock Divider Control
16
IPTAT
18
RESETN
Temperature Monitor (Output current proportional to absolute temperature)
22, 23
CLKP, CLKN
24, 25
CLKDIVRSTP, CLKDIVRSTN
31
D14
DDR Logical Bits 14, 15
36
D12
DDR Logical Bits 12, 13
40
D10
DDR Logical Bits 10, 11
44
D8
DDR Logical Bits 8, 9
46
RLVDS
LVDS Bias Resistor (Connect to OVSS with 1%10kΩ)
48
CLKOUT
CMOS Clock Output
52
D6
DDR Logical Bits 6, 7
56
D4
DDR Logical Bits 4, 5
60
D2
DDR Logical Bits 2, 3
64
D0
DDR Logical Bits 0, 1
66
SDO
SPI Serial Data Output
67
CSB
SPI Chip Select (active low)
68
SCLK
SPI Clock
69
SDIO
SPI Serial Data Input/Output
Exposed Paddle
AVSS
Analog Ground
Power On Reset (Active Low)
Clock Input True, Complement
Synchronous Clock Divider Reset True, Complement
Ordering Information
PART NUMBER
(Notes 1, 2)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISLA216P13IRZ
ISLA216P13 IRZ
-40°C to +85°C
72 Ld QFN
L72.10x10E
ISLA216P20IRZ
ISLA216P20 IRZ
-40°C to +85°C
72 Ld QFN
L72.10x10E
ISLA216P25IRZ
ISLA216P25 IRZ
-40°C to +85°C
72 Ld QFN
L72.10x10E
Coming Soon
ISLA216P13IR1Z
ISLA216P13 IR1Z
-40°C to +85°C
48 Ld QFN
TBD
Coming Soon
ISLA216P20IR1Z
ISLA216P20 IR1Z
-40°C to +85°C
48 Ld QFN
TBD
Coming Soon
ISLA216P25IR1Z
ISLA216P25 IR1Z
-40°C to +85°C
48 Ld QFN
TBD
ISLA216IR72EV1Z
Evaluation Board (72 pin QFN ADC)
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISLA216P. For more information on MSL please see techbrief TB363.
5
FN7574.2
December 10, 2012
ISLA216P
Table of Contents
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-On Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
User Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Temperature Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nap/Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
19
19
20
20
20
20
20
Clock Divider Synchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Configuration/Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
24
25
25
26
27
SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
A/D Evaluation Platform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Input Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVCMOS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
32
32
32
32
32
32
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6
FN7574.2
December 10, 2012
ISLA216P
Absolute Maximum Ratings
Thermal Information
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Latchup (Tested per JESD-78C;Class 2,Level A) . . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
72 Ld QFN (Notes 3, 4) . . . . . . . . . . . . . . . .
23
0.9
48 Ld QFN (Notes 3, 4) . . . . . . . . . . . . . . . .
24
1.0
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
4. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply
over the operating temperature range, -40°C to +85°C.
ISLA216P25
PARAMETER
SYMBOL
CONDITIONS
ISLA216P20
MIN
MAX
MIN
(Note 5) TYP (Note 5) (Note 5) TYP
ISLA216P13
MAX
MIN
(Note 5) (Note 5) TYP
MAX
(Note 5)
UNITS
2.2
VP-P
DC SPECIFICATIONS (Note 6)
Analog Input
Full-Scale Analog Input
Range
VFS
Differential
1.95
2.0
2.2
1.95
2.0
2.2
1.95
2.0
Input Resistance
RIN
Differential
300
300
300
Ω
Input Capacitance
CIN
Differential
9
9
9
pF
180
180
180
ppm/°C
Full Scale Range Temp.
Drift
AVTC
Input Offset Voltage
VOS
Common-Mode Output
Voltage
VCM
0.94
0.94
0.94
V
Common-Mode Input
Current (per pin)
ICM
5.2
5.2
5.2
µA/MSPS
Inputs Common Mode
Voltage
0.9
0.9
0.9
V
CLKP,CLKN Input Swing
1.8
1.8
1.8
V
Full Temp
-5.0
-1.7
5.0
-5.0
-1.7
5.0
-5.0
-1.7
5.0
mV
Clock Inputs
Power Requirements
1.8V Analog Supply
Voltage
AVDD
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
1.8V Digital Supply
Voltage
OVDD
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
1.8V Analog Supply
Current
IAVDD
372
397
342
360
293
310
mA
1.8V Digital Supply
Current (Note 6)
I
OVDD
3mA LVDS
64
73
58
68
50
58
mA
Power Supply Rejection
Ratio
PSRR
30MHz, 50mVP-P signal
on AVDD
-65
7
-65
-65
dB
FN7574.2
December 10, 2012
ISLA216P
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply
over the operating temperature range, -40°C to +85°C. (Continued)
ISLA216P25
PARAMETER
SYMBOL
CONDITIONS
ISLA216P20
MIN
MAX
MIN
(Note 5) TYP (Note 5) (Note 5) TYP
ISLA216P13
MAX
MIN
(Note 5) (Note 5) TYP
MAX
(Note 5)
UNITS
Total Power Dissipation
Normal Mode
PD
Nap Mode
PD
Sleep Mode
PD
2mA LVDS
771
3mA LVDS
786
CMOS
760
CSB at logic high
Nap/Sleep Mode
Wakeup Time
Sample Clock Running
706
846
720
603
770
616
685
mW
662
580
mW
mW
88
103
83
99
77
94
mW
7
19
7
19
7
19
mW
200
400
630
µs
±0.25
LSB
±5
LSB
AC SPECIFICATIONS
Differential Nonlinearity
DNL
fIN = 30MHz
No Missing Codes
Integral Nonlinearity
INL
fIN = 30MHz
Minimum Conversion
Rate (Note 7)
fS MIN
Maximum Conversion
Rate
fS MAX
Signal-to-Noise Ratio
(Note 8)
SNR
Signal-to-Noise and
Distortion
(Note 8)
Effective Number of Bits
(Note 8)
-0.99
±0.35
-0.99
±10
±0.25
±6
40
250
fIN = 30MHz
fIN = 105MHz
SINAD
8
200
74.9
40
130
76.6
74.8
76.4
75.5
MSPS
MSPS
77.5
dBFS
76.9
dBFS
fIN = 190MHz
74.2
75.3
75.3
dBFS
fIN = 363MHz
72.1
72.6
72.4
dBFS
fIN = 461MHz
71.1
71.1
70.8
dBFS
fIN = 605MHz
69.2
69.2
68.9
dBFS
fIN = 30MHz
74.7
76.5
77.4
dBFS
76.1
dBFS
fIN = 105MHz
ENOB
40
75.0
71.7
-0.99
70.0
74.1
73.2
76.1
72.6
fIN = 190MHz
73.1
74.7
74.6
dBFS
fIN = 363MHz
71.6
71.7
71.9
dBFS
fIN = 461MHz
69.2
68.6
67.9
dBFS
fIN = 605MHz
65.7
64.9
66.3
dBFS
fIN = 30MHz
12.12
12.42
12.56
Bits
fIN = 105MHz
11.34 12.02
11.87 12.35
11.77 12.35
Bits
fIN = 190MHz
11.85
12.12
12.10
Bits
fIN = 363MHz
11.60
11.62
11.65
Bits
fIN = 461MHz
11.20
11.10
10.99
Bits
fIN = 605MHz
10.62
10.49
10.72
Bits
FN7574.2
December 10, 2012
ISLA216P
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply
over the operating temperature range, -40°C to +85°C. (Continued)
ISLA216P25
PARAMETER
SYMBOL
Spurious-Free Dynamic
Range
(Note 8)
SFDR
CONDITIONS
MIN
MAX
MIN
(Note 5) TYP (Note 5) (Note 5) TYP
fIN = 30MHz
fIN = 105MHz
ISLA216P20
87
74
83
ISLA216P13
MAX
MIN
(Note 5) (Note 5) TYP
91
74
89
72
MAX
(Note 5)
UNITS
96
dBc
83
dBc
fIN = 190MHz
81
84
83
dBc
fIN = 363MHz
81
80
82
dBc
fIN = 461MHz
73
72
70
dBc
fIN = 605MHz
67
67
67
dBc
Spurious-Free Dynamic SFDRX23 fIN = 30MHz
Range Excluding H2, H3
fIN = 105MHz
(Note 8)
89
91
99
dBc
96
dBc
80
92
82
93
82
fIN = 190MHz
88
92
96
dBc
fIN = 363MHz
83
87
94
dBc
fIN = 461MHz
82
85
91
dBc
fIN = 605MHz
79
82
89
dBc
fIN = 70MHz
94
92
88
dBFS
fIN = 170MHz
87
87
87
dBFS
Intermodulation
Distortion
IMD
Word Error Rate
WER
10-12
10-12
10-12
Full Power Bandwidth
FPBW
700
700
700
MHz
NOTES:
5. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
6. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load on each digital output.
7. The DLL Range setting must be changed for low-speed operation.
8. Minimum specification guaranteed when calibrated at +85°C.
Digital Specifications
Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5) UNITS
0
1
10
µA
-25
-12
-7
µA
4
12
µA
-600
-415
-300
µA
40
58
75
µA
5
10
µA
INPUTS
Input Current High (RESETN)
IIH
VIN = 1.8V
Input Current Low (RESETN)
IIL
VIN = 0V
Input Current High (SDIO)
IIH
VIN = 1.8V
Input Current Low (SDIO)
IIL
VIN = 0V
Input Current High (CSB)
IIH
VIN = 1.8V
Input Current Low (CSB)
IIL
VIN = 0V
Input Voltage High (SDIO, RESETN)
VIH
Input Voltage Low (SDIO, RESETN)
VIL
Input Current High (CLKDIV) (Note 9)
IIH
16
Input Current Low (CLKDIV)
IIL
-34
Input Capacitance
CDI
9
1.17
V
0.63
V
25
34
µA
-25
-16
µA
4
pF
FN7574.2
December 10, 2012
ISLA216P
Digital Specifications
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5) UNITS
LVDS INPUTS (CLKDIVRSTP,CLKDIVRSTN)
Input Common Mode Range
VICM
825
1575
mV
Input Differential Swing (peak to peak, single-ended)
VID
250
450
mV
CLKDIVRSTP Input Pull-down Resistance
RIpd
100
kΩ
CLKDIVRSTN Input Pull-up Resistance
RIpu
100
kΩ
612
mVP-P
LVDS OUTPUTS
Differential Output Voltage (Note 10)
Output Offset Voltage
VT
3mA Mode
VOS
3mA Mode
1120
1150
1200
mV
Output Rise Time
tR
240
ps
Output Fall Time
tF
240
ps
OVDD - 0.1
V
CMOS OUTPUTS
Voltage Output High
VOH
IOH = -500µA
Voltage Output Low
VOL
IOL = 1mA
OVDD - 0.3
0.1
0.3
V
Output Rise Time
tR
1.8
ns
Output Fall Time
tF
1.4
ns
NOTES:
9. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending
on desired function.
10. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential swing.
Timing Diagrams
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUTN
CLKOUTP
tDC
D[14/12/…/2/0]N
D[14/12/…/2/0]P
tPD
ODD
N-L
EVEN
N-L
ODD
N-L+1
EVEN
N-L+1
EVEN
N-1
ODD
N
EVEN
N
FIGURE 1A. LVDS
10
FN7574.2
December 10, 2012
ISLA216P
Timing Diagrams
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUT
tDC
tPD
D[14/12/…/2/0]
ODD
N-L
EVEN
N-L
ODD
N-L+1
EVEN
N-L+1
EVEN
N-1
ODD
N
EVEN
N
FIGURE 1B. CMOS
FIGURE 1. TIMING DIAGRAMS
Switching Specifications
PARAMETER
Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
CONDITION
MIN
(Note 5)
TYP
MAX
(Note 5)
UNITS
ADC OUTPUT
Aperture Delay
tA
114
ps
RMS Aperture Jitter
jA
75
fs
Input Clock to Output Clock Propagation
Delay
Relative Input Clock to Output Clock
Propagation Delay (Note 13)
tCPD
AVDD, OVDD = 1.7V to 1.9V,
TA = -40°C to +85°C
1.65
2.4
3
ns
tCPD
AVDD, OVDD = 1.8V, TA = +25°C
1.9
2.3
2.75
ns
dtCPD
AVDD, OVDD = 1.7V to 1.9V,
TA = -40°C to +85°C
-450
450
ps
Input Clock to Data Propagation Delay
tPD
Output Clock to Data Propagation Delay,
LVDS Mode
tDC
Output Clock to Data Propagation Delay,
CMOS Mode
tDC
Synchronous Clock Divider Reset Setup
Time (with respect to the positive edge of
CLKP)
tRSTS
Synchronous Clock Divider Reset Hold Time
(with respect to the positive edge of CLKP)
tRSTH
Synchronous Clock Divider Reset Recovery
Time
tRSTRT
Latency (Pipeline Delay)
L
11
1.65
2.4
3.5
ns
Rising/Falling Edge
-0.1
0.16
0.5
ns
Rising/Falling Edge
-0.1
0.2
0.65
ns
0.4
0.06
0.02
DLL recovery time after
Synchronous Reset
ns
0.35
ns
52
µs
10
cycles
FN7574.2
December 10, 2012
ISLA216P
Switching Specifications
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
Overvoltage Recovery
MIN
(Note 5)
CONDITION
tOVR
TYP
MAX
(Note 5)
UNITS
1
cycles
SPI INTERFACE (Notes 11, 12)
t
SCLK Period
CLK
Write Operation
16
cycles
tCLK
Read Operation
16
cycles
CSB↓ to SCLK↑ Setup Time
tS
Read or Write
28
cycles
CSB↑ after SCLK↑ Hold Time
tH
Write
5
cycles
Data Valid to SCLK↑ Setup Time
tDS
Write
6
cycles
Data Valid after SCLK↑ Hold Time
tDH
Read or Write
4
cycles
Data Valid after SCLK↓ Time
tDVR
Read
5
cycles
NOTES:
11. SPI Interface timing is directly proportional to the ADC sample period (tS). Values above reflect multiples of a 4ns sample period, and must be scaled
proportionally for lower sample rates. ADC sample clock must be running for SPI communication.
12. The SPI may operate asynchronously with respect to the ADC sample clock.
13. The relative propagation delay is the difference in propagation time between any two devices that are matched in temperature and voltage, and is
specified over the full operating temperature and voltage range.
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -2dBFS,
fIN = 105MHz, fSAMPLE = 250MSPS.
-65
HD2 AND HD3 MAGNITURE (dBc)
SNR (dBFS) AND SFDR (dBc)
95
SFDR @ 130MSPS
90
SFDR @ 250MSPS
85
80
75
70
SNR @ 130MSPS
SNR @ 250MSPS
65
60
0
100
200
300
400
500
INPUT FREQUENCY (MHz)
-75
-80
-85
HD3 @ 250MSPS
-90
-95
HD3 @ 130MSPS
-100
-105
600
HD2 @ 250MSPS
-70
HD2 @ 130MSPS
0
100
500
600
-10
0
HD2 AND HD3 MAGNITUDE
-40
90
SFDR(dBfs)
80
SNR AND SFDR
200
300
400
INPUT FREQUENCY (MHz)
FIGURE 3. HD2 AND HD3 vs fIN
FIGURE 2. SNR AND SFDR vs fIN
70
SNR(dBfs)
60
SFDR(dBc)
50
SNR(dBc)
40
30
HD2 (dBc)
-50
-60
-70
HD3 (dBc)
-80
HD2 (dBfs)
-90
HD3 (dBfs)
-100
20
10
100
-60
-50
-40
-30
-20
INPUT AMPLITUDE (dBFS)
FIGURE 4. SNR AND SFDR vs AIN
12
-10
0
-110
-60
-50
-40
-30
-20
INPUT AMPLITUDE (dBFS)
FIGURE 5. HD2 AND HD3 vs AIN
FN7574.2
December 10, 2012
ISLA216P
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -2dBFS,
fIN = 105MHz, fSAMPLE = 250MSPS. (Continued)
-75
HD2 AND HD3 MAGNITUDE (dBc)
SNR (dBFS) AND SFDR (dBc)
90
SFDR
85
80
SNR
75
70
70
90
110
130
150
170
190
210
230
-80
H3
-85
-90
-95
H2
-100
-105
70
250
90
110
130
SAMPLE RATE (MSPS)
FIGURE 6. SNR AND SFDR vs fSAMPLE
170
190
210
230
250
FIGURE 7. HD2 AND HD3 vs fSAMPLE
800
1.5
750
1.0
700
DNL (LSBs)
TOTAL POWER (mW)
150
SAMPLE RATE (MSPS)
650
600
LVDS
550
0.5
0
-0.5
-1.0
500
CMOS
450
40
-1.5
60
80
100 120 140 160 180 200 220 240
SAMPLE RATE (MSPS)
0
FIGURE 8. POWER vs fSAMPLE IN 3mA LVDS MODE
20,000
30,000 40,000
CODES
50,000
60,000
FIGURE 9. DIFFERENTIAL NONLINEARITY
20
85
SNR (dBFS) AND SFDR (dBc)
15
10
INL (LSBs)
10,000
5
0
-5
-10
-15
-20
0
10,000
20,000
30,000 40,000
CODES
50,000
FIGURE 10. INTEGRAL NONLINEARITY
13
60,000
SFDR
80
75
SNR
70
65
60
0.75
0.85
0.95
1.05
1.15
INPUT COMMON MODE (V)
FIGURE 11. SNR AND SFDR vs VCM
FN7574.2
December 10, 2012
ISLA216P
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -2dBFS,
fIN = 105MHz, fSAMPLE = 250MSPS. (Continued)
0
25000
AMPLITUDE (dBFS)
NUMBER OF HITS
20000
15000
10000
5000
0
-60
-80
-120
0
32696 32700 32704 32708 32712 32716 32720 32724
CODE
20
40
60
80
FREQUENCY (MHz)
120
0
-40
-60
-80
AIN = -2 dBFS
SNR = 72.4 dBFS
SFDR = 80 dBc
SINAD = 71.3 dBFS
-20
AMPLITUDE (dBFS)
AIN = -2 dBFS
SNR = 74.5 dBFS
SFDR = 81 dBc
SINAD = 73.67 dBFS
-20
-100
-40
-60
-80
-100
0
20
40
60
80
100
-120
120
0
20
40
60
80
100
FIGURE 14. SINGLE-TONE SPECTRUM @ 190MHz
FIGURE 15. SINGLE-TONE SPECTRUM @ 363MHz
0
0
IMD3 = -94dBFS
IMD2
IMD3
2nd Harmonics
3rd Harmonics
-40
-60
-80
-100
IMD3 = -87dBFS
IMD2
IMD3
2nd Harmonics
3rd Harmonics
-20
AMPLITUDE (dBFS)
-20
120
FREQUENCY (MHz)
FREQUENCY (MHz)
AMPLITUDE (dBFS)
100
FIGURE 13. SINGLE-TONE SPECTRUM @ 105MHz
0
AMPLITUDE (dBFS)
-40
-100
FIGURE 12. NOISE HISTOGRAM
-120
AIN = -2 dBFS
SNR = 75.4 dBFS
SFDR = 82 dBc
SINAD = 74.5 dBFS
-20
-40
-60
-80
-100
-120
0
20
40
60
80
FREQUENCY (MHz)
FIGURE 16. TWO-TONE SPECTRUM
(F1 = 70MHz, F2 = 71MHz AT -7dBFS)
14
100
120
-120
0
20
40
60
80
100
120
FREQUENCY (MHz)
FIGURE 17. TWO-TONE SPECTRUM
(F1 = 170MHz, F2 = 171MHz AT -7dBFS)
FN7574.2
December 10, 2012
ISLA216P
Theory of Operation
following conditions must be adhered to for the power-on
calibration to execute successfully:
Functional Description
The ISLA216P is based upon a 16-bit, 250MSPS A/D converter
core that utilizes a pipelined successive approximation
architecture (Figure 18). The input voltage is captured by a
Sample-Hold Amplifier (SHA) and converted to a unit of charge.
Proprietary charge-domain techniques are used to successively
compare the input to a series of reference charges. Decisions
made during the successive approximation operations determine
the digital code for each input value. Digital error correction is also
applied, resulting in a total latency of 10 clock cycles. This is
evident to the user as a latency between the start of a conversion
and the data being available on the digital outputs.
The ISLA216P family operates by simultaneously sampling the
input signal with two ADC cores in parallel and summing the
digital result. Since the input signal is correlated between the two
cores and noise is not, an increase in SNR is achieved. As a result,
the offset, gain, or operational mode of both cores should be
adjusted when a change to the ADC's offset, gain, or operational
mode is desired.
Power-On Calibration
As mentioned previously, the cores perform a self-calibration at
start-up. An internal power-on-reset (POR) circuit detects the
supply voltage ramps and initiates the calibration when the
analog and digital supply voltages are above a threshold. The
• A frequency-stable conversion clock must be applied to the
CLKP/CLKN pins
• DNC pins must not be connected
• SDO has an internal pull-up and should not be driven externally
• RESETN is pulled low by the ADC internally during POR.
External driving of RESETN is optional.
• SPI communications must not be attempted
A user-initiated reset can subsequently be invoked in the event
that the above conditions cannot be met at power-up.
After the power supply has stabilized the internal POR releases
RESETN and an internal pull-up pulls it high, which starts the
calibration sequence. If a subsequent user-initiated reset is
desired, the RESETN pin should be connected to an open-drain
driver with an off-state/high impedance state leakage of less
than 0.5mA to assure exit from the reset state so calibration can
start.
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 19. Calibration status can be
determined by reading the cal_status bit (LSB) at 0xB6. This bit is
‘0’ during calibration and goes to a logic ‘1’ when calibration is
complete. The data outputs produce 0xCCCC during calibration;
this can also be used to determine calibration status.
If the selectable clock divider is set to 1 (default), the output
clock (CLKOUTP/CLKOUTN) will not be affected by the assertion
of RESETN. If the selectable clock divider is set to 2 or 4, the
output clock is set low while RESETN is asserted (low). Normal
operation of the output clock resumes at the next input clock
edge (CLKP/CLKN) after RESETN is de-asserted. At 250MSPS the
nominal calibration time is 200ms, while the maximum
calibration time is 550ms.
CLOCK
GENERATION
INP
2.5-BIT
FLASH
SHA
INN
1.25V
+
–
2.5-BIT
FLASH
6- STAGE
1.5-BIT/ STAGE
3- STAGE
1- BIT/ STAGE
3-BIT
FLASH
DIGITAL
ERROR
CORRECTION
LVDS/ LVCMOS
OUTPUTS
FIGURE 18. A/D CORE BLOCK DIAGRAM
15
FN7574.2
December 10, 2012
ISLA216P
CLKN
CLKP
CALIBRATION
TIME
RESETN
CAL_STATUS
BIT
CALIBRATION
BEGINS
CALIBRATION
COMPLETE
CLKOUTP
FIGURE 19. CALIBRATION TIMING
User Initiated Reset
Recalibration of the A/D can be initiated at any time by driving
the RESETN pin low for a minimum of one clock cycle. An
open-drain driver with a drive strength in its high impedance
state of less than 0.5mA is recommended, as RESETN has an
internal high impedance pull-up to OVDD. As is the case during
power-on reset, RESETN and DNC pins must be in the proper
state for the calibration to successfully execute.
The performance of the ISLA216P25 changes with variations in
temperature, supply voltage or sample rate. The extent of these
changes may necessitate recalibration, depending on system
performance requirements. Best performance will be achieved
by recalibrating the A/D under the environmental conditions at
which it will operate.
A supply voltage variation of <100mV will generally result in an
SNR change of <0.5dBFS and SFDR change of <3dBc.
In situations where the sample rate is not constant, best results
will be obtained if the device is calibrated at the highest sample
rate. Reducing the sample rate by less than 80MSPS will typically
result in an SNR change of <0.5dBFS and an SFDR change of
<3dBc.
Figures 20 through 25 show the effect of temperature on SNR
and SFDR performance with power on calibration performed at
-40°C, +25°C, and +85°C. Each plot shows the variation of
SNR/SFDR across temperature after a single power on
calibration at -40°C, +25°C and +85°C. Best performance is
typically achieved by a user-initiated power on calibration at the
operating conditions, as stated earlier. However, it can be seen
that performance drift with temperature is not a very strong
function of the temperature at which the power on calibration is
performed; also note that SFDR performance typically improves
as the analog input level moves away from full-scale as Figure 4
shows.
16
FN7574.2
December 10, 2012
ISLA216P
Temperature Calibration
95
78
130MSPS
SFDR (dBc)
SNR (dBFS)
250MSPS
200MSPS
77
250MSPS
76
200MSPS
90
130MSPS
85
75
74
-40
-35
-30
-25
80
-40
-20
-35
-30
-25
-20
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 20. TYPICAL SNR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT -40°C, fIN = 105MHz, -2dBFS
FIGURE 21. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT -40°C, fIN = 105MHz, -2dBFS
78
95
130MSPS
200MSPS
200MSPS
SFDR (dBc)
SNR (dBFS)
77
76
90
130MSPS
85
75 250MSPS
250MSPS
74
5
10
15
20
25
30
35
40
80
45
5
10
15
TEMPERATURE (°C)
FIGURE 22. TYPICAL SNR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +25°C, fIN = 105MHz, -2dBFS
30
35
40
45
95
76
200MSPS
SFDR (dBc)
130MSPS
77
SNR (dBFS)
25
FIGURE 23. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +25°C, fIN = 105MHz, -2dBFS
78
90
200MSPS
85
130MSPS
75
250MSPS
74
65
20
TEMPERATURE (°C)
67
69
71
73
75
77
79
81
83
85
TEMPERATURE (°C)
FIGURE 24. TYPICAL SNR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +85°C, fIN = 105MHz, -2dBF
Analog Input
A single fully differential input (VINP/VINN) connects to the
17
80
65
250MSPS
70
75
TEMPERATURE (°C)
80
85
FIGURE 25. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +85°C, fIN = 105MHz, -2dBFS
sample and hold amplifier (SHA) of each unit A/D. The ideal
full-scale input voltage is 2.0V, centered at the VCM voltage of
FN7574.2
December 10, 2012
ISLA216P
0.94V as shown in Figure 26.
VINN
1.8
VINP
1.4
VCM
0.94V
1.0V
1.0
0.6
0.2
FIGURE 26. ANALOG INPUT RANGE
Best performance is obtained when the analog inputs are driven
differentially. The common-mode output voltage, VCM, should be
used to properly bias the inputs as shown in Figures 27 through
29. An RF transformer will give the best noise and distortion
performance for wideband and/or high intermediate frequency
(IF) inputs. Two different transformer input schemes are shown in
Figures 27 and 28.
ADT1-1WT
ADT1-1WT
1000pF
A/D
VCM
0.1µF
FIGURE 27. TRANSFORMER INPUT FOR GENERAL PURPOSE
APPLICATIONS
ADTL1-12
TX-2-5-1
1000pF
A/D
VCM
1000pF
FIGURE 28. TRANSMISSION-LINE TRANSFORMER INPUT FOR
HIGH IF APPLICATIONS
18
FN7574.2
December 10, 2012
ISLA216P
This dual transformer scheme is used to improve common-mode
rejection, which keeps the common-mode level of the input
matched to VCM. The value of the shunt resistor should be
determined based on the desired load impedance. The
differential input resistance of the ISLA216P25 is 300Ω.
The SHA design uses a switched capacitor input stage (see
Figure 42), which creates current spikes when the sampling
capacitance is reconnected to the input voltage. This causes a
disturbance at the input which must settle before the next
sampling point. Lower source impedance will result in faster
settling and improved performance. Therefore a 2:1 or 1:1
transformer and low shunt resistance are recommended for
optimal performance.
A/D
TC4-19G2+
1000pF
CLKP
200
0.01µF
CLKN
1000pF
1000pF
FIGURE 30. RECOMMENDED CLOCK DRIVE
A selectable 2x or 4x frequency divider is provided in series with
the clock input. The divider can be used in the 2x mode with a
sample clock equal to twice the desired sample rate or in 4x
mode with a sample clock equal to four times the desired
sample rate. This allows the use of the Phase Slip feature, which
enables synchronization of multiple ADCs. The Phase Slip feature
can be used as an alternative to using the CLKDIVRST pins to
synchronize ADCs in a multiple ADC system.
TABLE 1. CLKDIV PIN SETTINGS
FIGURE 29. DIFFERENTIAL AMPLIFIER INPUT
A differential amplifier, as shown in the simplified block diagram
in Figure 29, can be used in applications that require
DC-coupling. In this configuration, the amplifier will typically
dominate the achievable SNR and distortion performance.
Intersil’s new ISL552xx differential amplifier family can also be
used in certain AC applications with minimal performance
degradation. Contact the factory for more information.
Clock Input
The clock input circuit is a differential pair (see Figure 43).
Driving these inputs with a high level (up to 1.8VP-P on each
input) sine or square wave will provide the lowest jitter
performance. A transformer with 4:1 impedance ratio will
provide increased drive levels. The clock input is functional with
AC-coupled LVDS, LVPECL, and CML drive levels. To maintain the
lowest possible aperture jitter, it is recommended to have high
slew rate at the zero crossing of the differential clock input
signal.
The recommended drive circuit is shown in Figure 30. A duty
range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may impact
SNR performance. The clock inputs are internally self-biased to
AVDD/2 to facilitate AC coupling.
19
CLKDIV PIN
DIVIDE RATIO
AVSS
2
Float
1
AVDD
4
The clock divider can also be controlled through the SPI port,
which overrides the CLKDIV pin setting. See “SPI Physical
Interface” on page 24. A delay-locked loop (DLL) generates
internal clock signals for various stages within the charge
pipeline. If the frequency of the input clock changes, the DLL may
take up to 52μs to regain lock at 250MSPS. The lock time is
inversely proportional to the sample rate.
The DLL has two ranges of operation, slow and fast. The slow
range can be used for sample rates between 40MSPS and
100MSPS, while the default fast range can be used from
80MSPS to the maximum specified sample rate.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
between clock jitter (tJ) and SNR is shown in Equation 1 and is
illustrated in Figure 31.
1
SNR = 20 log 10 ⎛ --------------------⎞
⎝ 2πf t ⎠
IN J
(EQ. 1)
FN7574.2
December 10, 2012
ISLA216P
Nap/Sleep
100
95
Portions of the device may be shut down to save power during
times when operation of the A/D is not required. Two power saving
modes are available: Nap, and Sleep. Nap mode reduces power
dissipation to <103mW while Sleep mode reduces power
dissipation to <19mW.
tj = 0.1ps
90
14 BITS
SNR (dB)
85
80
tj = 1ps
75
12 BITS
70
tj = 10ps
65
60
10 BITS
tj = 100ps
55
50
1M
10M
100M
INPUT FREQUENCY (Hz)
1G
FIGURE 31. SNR vs CLOCK JITTER
This relationship shows the SNR that would be achieved if clock
jitter were the only non-ideal factor. In reality, achievable SNR is
limited by internal factors such as linearity, aperture jitter and
thermal noise. Internal aperture jitter is the uncertainty in the
sampling instant shown in Figure1A. The internal aperture jitter
combines with the input clock jitter in a root-sum-square fashion,
since they are not statistically correlated, and this determines
the total jitter in the system. The total jitter, combined with other
noise sources, then determines the achievable SNR.
Voltage Reference
A temperature compensated internal voltage reference provides
the reference charges used in the successive approximation
operations. The full-scale range of each A/D is proportional to the
reference voltage. The nominal value of the voltage reference is
1.25V.
Digital Outputs
Output data is available as a parallel bus in LVDS-compatible
(default) or CMOS modes. In either case, the data is presented in
double data rate (DDR) format. Figures 1A and 1B show the timing
relationships for LVDS and CMOS modes, respectively.
Additionally, the drive current for LVDS mode can be set to a
nominal 3mA(default) or a power-saving 2mA. The lower current
setting can be used in designs where the receiver is in close
physical proximity to the A/D. The applicability of this setting is
dependent upon the PCB layout, therefore the user should
experiment to determine if performance degradation is
observed.
All digital outputs (Data, CLKOUT and OR) are placed in a high
impedance state during Nap or Sleep. The input clock should
remain running and at a fixed frequency during Nap or Sleep, and
CSB should be high. Recovery time from Nap mode will increase
if the clock is stopped, since the internal DLL can take up to 52µs
to regain lock at 250MSPS.
By default after the device is powered on, the operational state is
controlled by the NAPSLP pin as shown in Table 2.
TABLE 2. NAPSLP PIN SETTINGS
NAPSLP PIN
MODE
AVSS
Normal
Float
Sleep
AVDD
Nap
The power-down mode can also be controlled through the SPI
port, which overrides the NAPSLP pin setting. Details on this are
contained in “Serial Peripheral Interface” on page 24.
Data Format
Output data can be presented in three formats: two’s
complement (default), Gray code and offset binary. The data
format can also be controlled through the SPI port, by writing to
address 0x73. Details on this are contained in “Serial Peripheral
Interface” on page 24.
Offset binary coding maps the most negative input voltage to
code 0x000 (all zeros) and the most positive input to 0xFFF (all
ones). Two’s complement coding simply complements the MSB
of the offset binary representation.
When calculating Gray code the MSB is unchanged. The
remaining bits are computed as the XOR of the current bit
position and the next most significant bit. Figure 32 shows this
operation.
BINARY
15
14
13
••••
1
0
The output mode can be controlled through the SPI port, by
writing to address 0x73, see “Serial Peripheral Interface” on
page 24.
An external resistor creates the bias for the LVDS drivers. A 10kΩ,
1% resistor must be connected from the RLVDS pin to OVSS.
Power Dissipation
The power dissipated by the ISLA216P25 is primarily dependent
on the sample rate and the output modes: LVDS vs CMOS and
DDR vs SDR. There is a static bias in the analog supply, while the
remaining power dissipation is linearly related to the sample
rate. The output supply dissipation changes to a lesser degree in
LVDS mode, but is more strongly related to the clock frequency in
CMOS mode.
20
••••
GRAY CODE
15
14
13
••••
1
0
FIGURE 32. BINARY TO GRAY CODE CONVERSION
FN7574.2
December 10, 2012
ISLA216P
Converting back to offset binary from Gray code must be done
recursively, using the result of each bit for the next lower bit as
shown in Figure 33.
GRAY CODE
15
14
13
••••
1
0
••••
••••
Clock Divider Synchronous Reset
If the selectable clock divider is used, the ADC's internal sample
clock will be at half the frequency (DIV=2) or one quarter the
frequency (DIV=4) of the device clock. The phase relationship
between the sample clock and the device clock is initially
indeterminate. An output clock (CLKOUTP, CLKOUTN) is provided
to facilitate latching of the sampled data and estimation of the
internal sample clock's phase. The output clock has a fixed
phase relationship to the sample clock. When the selectable
clock divider is set to 2 or 4, the output clock's phase relationship
to the sample clock remains fixed but is initially indeterminate
with respect to the device clock. When the selectable clock
divider is set to 2 or 4, the synchronous clock divider reset
feature allows the phase of the internal sample clock and the
output clock to be synchronized (refer to Figure 34) with respect
to the device clock. This simplifies data capture in systems
employing multiple A/Ds where sampling of the inputs is desired
to be synchronous.
The reset signal must be well-timed with respect to the sample
clock (See “Switching Specifications” on page 11).
BINARY
15
14
13
••••
1
0
FIGURE 33. GRAY CODE TO BINARY CONVERSION
Mapping of the input voltage to the various data formats is
shown in Table 3.
A 100Ω differential termination resistor must be supplied
between CLKDIVRSTP and CLKDIVRSTN, external to the ADC, (on
the PCB) and should be located as close to the CLKDIVRSTP/N
pins as possible.
TABLE 3. INPUT VOLTAGE TO OUTPUT CODE MAPPING
INPUT
VOLTAGE
OFFSET BINARY
TWO’S
COMPLEMENT
GRAY CODE
–Full Scale
0000 0000 0000
0000
1000 0000 0000
0000
0000 0000 0000
0000
–Full Scale
+ 1LSB
0000 0000 0000
0001
1000 0000 0000
0001
0000 0000 0000
0001
Mid–Scale
1000 0000 0000
0000
0000 0000 0000
0000
1100 0000 0000
0000
+Full Scale
– 1LSB
1111 1111 1111
1110
0111 1111 1111
1110
1000 0000 0000
0001
+Full Scale
1111 1111 1111
1111
0111 1111 1111
1111
1000 0000 0000
0000
21
FN7574.2
December 10, 2012
ISLA216P
DEVICE CLOCK INPUT
L+td (Note 14)
ANALOG INPUT
s1
tRSTH
CLKDIVRSTP (Note 15)
tRSTS
tRSTRT
ADC1 OUTPUT DATA
s0
ODD
S0
EVEN
s1
ODD
s0
ODD
S0
EVEN
s1
ODD
s1
EVEN
ADC1 CLKOUTP
ADC2 OUTPUT DATA
S1
EVEN
ADC2 CLKOUTP
(PHASE 1) (Note 16)
ADC2 CLKOUTP
(PHASE 2) (Note 16)
FIGURE 34. SYNCHRONOUS RESET OPERATION, CLOCK DIVIDE = 2
NOTES:
14. Delay equals fixed pipeline latency (L cycles of sample clock) plus fixed analog propagation delay, td.
15. CLKDIVRSTP setup and hold times are with respect to input sample clock rising edge.CLKDIVRSTN is not
shown, but must be driven, and is the compliment of CLKDIVRSTP.
16. Either Output Clock Phase (phase 1 or phase 2 ) equally likely prior to synchronization.
CSB
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
FIGURE 35. MSB-FIRST ADDRESSING
22
FN7574.2
December 10, 2012
ISLA216P
CSB
SCLK
SDIO
A0
A1
A2
A11
A12
W0
W1
R/W
D1
D0
D2
D3
D4
D5
D6
D7
FIGURE 36. LSB-FIRST ADDRESSING
tDSW
CSB
tDHW
tS
tCLK
tHI
tH
tLO
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
SPI WRITE
FIGURE 37. SPI WRITE
tDSW
CSB
tCLK
tHI
tDHW
tH
tDVR
tS
tLO
SCLK
WRITING A READ COMMAND
READING DATA ( 3 WIRE MODE )
SDIO
R/W
W1
W0
A12
A11
A10
A9
A2
A1
A0
D7
SDO
D6
D3
D2
D1
D0
( 4 WIRE MODE)
D7
D3
D2
D1
D0
SPI READ
FIGURE 38. SPI READ
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD 2
FIGURE 39. 2-BYTE TRANSFER
23
FN7574.2
December 10, 2012
ISLA216P
LAST LEGAL
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD N
FIGURE 40. N-BYTE TRANSFER
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to facilitate
configuration of the device and to optimize performance. The SPI
bus consists of chip select (CSB), serial clock (SCLK) serial data
output (SDO), and serial data input/output (SDIO). The maximum
SCLK rate is equal to the A/D sample rate (fSAMPLE) divided by 16
for both write operations and read operations. At fSAMPLE =
250MHz, maximum SCLK is 15.63MHz for writing and read
operations. There is no minimum SCLK rate.
The following sections describe various registers that are used to
configure the SPI or adjust performance or functional parameters.
Many registers in the available address space (0x00 to 0xFF) are
not defined in this document. Additionally, within a defined
register there may be certain bits or bit combinations that are
reserved. Undefined registers and undefined values within defined
registers are reserved and should not be selected. Setting any
reserved register or value may produce indeterminate results.
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for the data
transfer. By default, all data is presented on the serial data
input/output (SDIO) pin in three-wire mode. The state of the SDIO
pin is set automatically in the communication protocol
(described in the following). A dedicated serial data output pin
(SDO) can be activated by setting 0x00[7] high to allow operation
in four-wire mode.
The SPI port operates in a half duplex master/slave
configuration, with the ISLA216P25 functioning as a slave.
Multiple slave devices can interface to a single master in
three-wire mode only, since the SDO output of an unaddressed
device is asserted in four wire mode.
The chip-select bar (CSB) pin determines when a slave device is
being addressed. Multiple slave devices can be written to
concurrently, but only one slave device can be read from at a
given time (again, only in three-wire mode). If multiple slave
devices are selected for reading at the same time, the results will
be indeterminate.
The communication protocol begins with an instruction/address
phase. The first rising SCLK edge following a high-to-low
transition on CSB determines the beginning of the two-byte
instruction/address command; SCLK must be static low before
the CSB transition. Data can be presented in MSB-first order or
LSB-first order. The default is MSB-first, but this can be changed
by setting 0x00[6] high. Figures 35 and 36 show the appropriate
bit ordering for the MSB-first and LSB-first modes, respectively. In
24
MSB-first mode, the address is incremented for multi-byte
transfers, while in LSB-first mode it’s decremented.
In the default mode, the MSB is R/W, which determines if the
data is to be read (active high) or written. The next two bits, W1
and W0, determine the number of data bytes to be read or
written (see Table 4). The lower 13 bits contain the first address
for the data transfer. This relationship is illustrated in Figure 37,
and timing values are given in “Switching
Specifications Boldface limits apply over the operating
temperature range, -40°C to +85°C.” on page 11.
After the instruction/address bytes have been read, the
appropriate number of data bytes are written to or read from the
A/D (based on the R/W bit status). The data transfer will
continue as long as CSB remains low and SCLK is active. Stalling
of the CSB pin is allowed at any byte boundary
(instruction/address or data) if the number of bytes being
transferred is three or less. For transfers of four bytes or more,
CSB is allowed to stall in the middle of the instruction/address
bytes or before the first data byte. If CSB transitions to a high
state after that point the state machine will reset and terminate
the data transfer.
TABLE 4. BYTE TRANSFER SELECTION
[W1:W0]
BYTES TRANSFERRED
00
1
01
2
10
3
11
4 or more
Figures 39 and 40 illustrate the timing relationships for 2-byte
and N-byte transfers, respectively. The operation for a 3-byte
transfer can be inferred from these diagrams.
SPI Configuration
ADDRESS 0X00: CHIP_PORT_CONFIG
Bit ordering and SPI reset are controlled by this register. Bit order
can be selected as MSB to LSB (MSB first) or LSB to MSB (LSB
first) to accommodate various micro controllers.
Bit 7 SDO Active
Bit 6 LSB First
Setting this bit high configures the SPI to interpret serial data
as arriving in LSB to MSB order.
FN7574.2
December 10, 2012
ISLA216P
ADDRESS 0X22: GAIN_COARSE_ADC0
Bit 5 Soft Reset
Setting this bit high resets all SPI registers to default values.
Bit 4 Reserved
ADDRESS 0X23: GAIN_MEDIUM_ADC0
ADDRESS 0X24: GAIN_FINE_ADC0
This bit should always be set high.
Bits 3:0 These bits should always mirror bits 4:7 to avoid
ambiguity in bit ordering.
ADDRESS 0X02: BURST_END
If a series of sequential registers are to be set, burst mode can
improve throughput by eliminating redundant addressing. The
burst is ended by pulling the CSB pin high. Setting the burst_end
address determines the end of the transfer. During a write
operation, the user must be cautious to transmit the correct
number of bytes based on the starting and ending addresses.
Bits 7:0 Burst End Address
This register value determines the ending address of the burst
data.
Device Information
Gain of the A/D core can be adjusted in coarse, medium and fine
steps. Coarse gain is a 4-bit adjustment while medium and fine
are 8-bit. Multiple Coarse Gain Bits can be set for a total
adjustment range of ±4.2%. (‘0011’ ≅ -4.2% and ‘1100’ ≅ +4.2%)
It is recommended to use one of the coarse gain settings (-4.2%,
-2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the
registers at 0x0023 and 0x24.
The default value of each register will be the result of the selfcalibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register. Bit 0 in register 0xFE must be set high
to enable updates written to 0x23 and 0x24 to be used by the
ADC (see description for 0xFE).
TABLE 6. COARSE GAIN ADJUSTMENT
0x22[3:0] core 0
0x26[3:0] core 1
ADDRESS 0X08: CHIP_ID
NOMINAL COARSE GAIN ADJUST
(%)
Bit3
+2.8
ADDRESS 0X09: CHIP_VERSION
Bit2
+1.4
The generic die identifier and a revision number, respectively, can
be read from these two registers.
Bit1
-2.8
Bit0
-1.4
Device Configuration/Control
A common SPI map, which can accommodate single-channel or
multi-channel devices, is used for all Intersil A/D products.
ADDRESS 0X20: OFFSET_COARSE_ADC0
ADDRESS 0X21: OFFSET_FINE_ADC0
The input offset of the A/D core can be adjusted in fine and
coarse steps. Both adjustments are made via an 8-bit word as
detailed in Table 5. The data format is twos complement.
The default value of each register will be the result of the selfcalibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register. Bit 0 in register 0xFE must be set high
to enable updates written to 0x20 and 0x21 to be used by the
ADC (see description for 0xFE).
TABLE 5. OFFSET ADJUSTMENTS
TABLE 7. MEDIUM AND FINE GAIN ADJUSTMENTS
PARAMETER
0x23[7:0]
MEDIUM GAIN
0x24[7:0]
FINE GAIN
Steps
256
256
–Full Scale (0x00)
-2%
-0.20%
Mid–Scale (0x80)
0.00%
0.00%
+Full Scale (0xFF)
+2%
+0.2%
Nominal Step Size
0.016%
0.0016%
ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By default,
the tri-level NAPSLP pin can select normal operation, nap or
sleep modes (refer to“Nap/Sleep” on page 20). This functionality
can be overridden and controlled through the SPI. This is an
indexed function when controlled from the SPI, but a global
function when driven from the pin. This register is not changed by
a Soft Reset.
PARAMETER
0x20[7:0]
COARSE OFFSET
0x21[7:0]
FINE OFFSET
Steps
255
255
–Full Scale (0x00)
-133LSB (-47mV)
-5LSB (-1.75mV)
VALUE
0x25[2:0]
POWER DOWN MODE
Mid–Scale (0x80)
0.0LSB (0.0mV)
0.0LSB
000
Pin Control
+Full Scale (0xFF)
+133LSB (+47mV)
+5LSB (+1.75mV)
001
Normal Operation
Nominal Step Size
1.04LSB (0.37mV)
0.04LSB (0.014mV)
010
Nap Mode
100
Sleep Mode
25
TABLE 8. POWER-DOWN CONTROL
FN7574.2
December 10, 2012
ISLA216P
ADDRESS 0X26: OFFSET_COARSE_ADC1
ADDRESS 0X27: OFFSET_FINE_ADC1
controlled through the SPI, as shown in Table 9. This register is
not changed by a Soft Reset.
TABLE 9. CLOCK DIVIDER SELECTION
The input offset of A/D core#1 can be adjusted in fine and
coarse steps in the same way that offset for core#0 can be
adjusted. Both adjustments are made via an 8-bit word as
detailed in Table 5. The data format is two’s complement.
The default value of each register will be the result of the selfcalibration after initial power-up. If a register is to be incremented or
decremented, the user should first read the register value then write
the incremented or decremented value back to the same register.
Bit 0 in register 0xFE must be set high to enable updates written to
0x26 and 0x27 to be used by the ADC (see description for 0xFE).
VALUE
0x72[2:0]
CLOCK DIVIDER
000
Pin Control
001
Divide by 1
010
Divide by 2
other
Not Allowed
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output format
of the data, as well as the logical coding. The ISLA216P25 can
present output data in two physical formats: LVDS (default) or
LVCMOS. Additionally, the drive strength in LVDS mode can be set
high (default,3mA or low (2mA).
ADDRESS 0X28: GAIN_COARSE_ADC1
ADDRESS 0X29: GAIN_MEDIUM_ADC1
ADDRESS 0X2A: GAIN_FINE_ADC1
Gain of A/D core #1 can be adjusted in coarse, medium and fine
steps in the same way that core #0 can be adjusted. Coarse gain is
a 4-bit adjustment while medium and fine are 8-bit. Multiple
Coarse Gain Bits can be set for a total adjustment range of ±4.2.
Bit 0 in register 0xFE must be set high to enable updates written to
0x29 and 0x2A to be used by the ADC (see description for 0xFE).
Data can be coded in three possible formats: two’s complement
(default), Gray code or offset binary. See Table 11.
This register is not changed by a Soft Reset.
TABLE 10. OUTPUT MODE CONTROL
Global Device Configuration/Control
ADDRESS 0X71: PHASE_SLIP
The output data clock is generated by dividing down the A/D input
sample clock. Some systems with multiple A/Ds can more easily latch
the data from each A/D by controlling the phase of the output data
clock. This control is accomplished through the use of the phase_slip
SPI feature, which allows the rising edge of the output data clock to be
advanced by one input clock period, as shown in the Figure 41.
Execution of a phase_slip command is accomplished by first writing a
'0' to bit 0 at address 0x71, followed by writing a '1' to bit 0 at address
0x71.
2ns
4ns
2ns
0x73[7:5]
OUTPUT MODE
000
LVDS 3mA (Default)
001
LVDS 2mA
100
LVCMOS
TABLE 11. OUTPUT FORMAT CONTROL
ADC Input
Clock (500MHz)
Output Data
Clock (250MHz)
No clock_slip
VALUE
VALUE
0x73[2:0]
OUTPUT FORMAT
000
Two’s Complement (Default)
010
Gray Code
100
Offset Binary
ADDRESS 0X74: OUTPUT_MODE_B
Bit 6 DLL Range
This bit sets the DLL operating range to fast (default) or slow.
Internal clock signals are generated by a delay-locked loop (DLL),
which has a finite operating range. Table 12 shows the allowable
sample rate ranges for the slow and fast settings.Note that Bit 4
at 0x74 is reserved and must not change value. A user writing to
Bit 6 should first read 0x74 to determine proper value to write
back to Bit 4 when writing to 0x74
Output Data
Clock (250MHz)
1 clock_slip
Output Data
Clock (250MHz)
2 clock_slip
FIGURE 41. PHASE SLIP
ADDRESS 0X72: CLOCK_DIVIDE
The ISLA216P25 has a selectable clock divider that can be set to
divide by two or one (no division). By default, the tri-level CLKDIV
pin selects the divisor This functionality can be overridden and
26
TABLE 12. DLL RANGES
DLL RANGE
MIN
MAX
UNIT
Slow
40
100
MSPS
Fast
80
250
MSPS
FN7574.2
December 10, 2012
ISLA216P
ADDRESS 0XB6: CALIBRATION STATUS
ADDRESS 0XC3: USER_PATT2_LSB
The LSB at address 0xB6 can be read to determine calibration
status. The bit is ‘0’ during calibration and goes to a logic ‘1’
when calibration is complete.This register is unique in that it can
be read after POR at calibration, unlike the other registers on
chip, which can’t be read until calibration is complete.
DEVICE TEST
The ISLA216P25 can produce preset or user defined patterns on
the digital outputs to facilitate in-situ testing. A user can pick
from preset built-in patterns by writing to the output test mode
field [7:4] at 0xC0 or user defined patterns by writing to the user
test mode field [2:0] at 0xC0. The user defined patterns should
be loaded at address space 0xC1 through 0xD0, see the “SPI
Memory Map” on page 29 for more detail.The predefined
patterns are shown in Table 13. The test mode is enabled
asynchronously to the sample clock, therefore several sample
clock cycles may elapse before the data is present on the output
bus.
ADDRESS 0XC4: USER_PATT2_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 2
ADDRESS 0XC5: USER_PATT3_LSB
ADDRESS 0XC6: USER_PATT3_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 3
ADDRESS 0XC7: USER_PATT4_LSB
ADDRESS 0XC8: USER_PATT4_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 4.
ADDRESS 0XC9: USER_PATT5_LSB
ADDRESS 0XCA: USER_PATT5_MSB
ADDRESS 0XC0: TEST_IO
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 5.
Bits 7:4 Output Test Mode
These bits set the test mode according to Table 13. Other
values are reserved.User test patterns loaded at 0xC1 through
0xD0 are also available by writing ‘1000’ to [7:4] at 0xC0 and a
pattern depth value to [2:0] at 0xC0. See “SPI Memory Map”
on page 29.
Bits 2:0 User Test Mode
The three LSBs in this register determine the test pattern in
combination with registers 0xC1 through 0xD0. Refer to the
“SPI Memory Map” on page 29.
TABLE 13. OUTPUT TEST MODES
VALUE
0xC0[7:4]
OUTPUT TEST MODE
0000
Off
0001
Midscale
0x8000
N/A
0010
Positive Full-Scale
0xFFFF
N/A
0011
Negative Full-Scale
0x0000
N/A
0100
Reserved
N/A
N/A
0101
Reserved
N/A
N/A
0110
Reserved
N/A
N/A
0111
Reserved
1000
User Pattern
user_patt1
user_patt2
1001
Reserved
N/A
N/A
1010
Ramp
N/A
N/A
WORD 1
WORD 2
ADDRESS 0XCB: USER_PATT6_LSB
ADDRESS 0XCC: USER_PATT6_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 6
ADDRESS 0XCD: USER_PATT7_LSB
ADDRESS 0XCE: USER_PATT7_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 7.
ADDRESS 0XCF: USER_PATT8_LSB
ADDRESS 0XD0: USER_PATT8_MSB
ADDRESS 0XC1: USER_PATT1_LSB
ADDRESS 0XC2: USER_PATT1_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 1.
27
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 8.
ADDRESS 0XFE: OFFSET/GAIN_ADJUST_ENABLE
Bit 0 at this register must be set high to enable adjustment of
offset coarse and fine adjustments ADC0 (0x20 and 0x21), ADC1
(0x26 and 0x27) and gain medium and gain fine adjustments
ADC0 (0x23 and 0x24), ADC1 (0x29 and 0x2A). It is
recommended that new data be written to the offset and gain
adjustment registers ADC0(0x20, 0x21, 0x23, 0x24) and
ADC1(0x26, 0x27, 0x29, 0x2A) while Bit 0 is a '0'. Subsequently,
Bit 0 should be set to '1' to allow the values written to the
aforementioned registers to be used by the ADC. Bit 0 should be
set to a '0' upon completion
Digital Temperature Sensor
ADDRESS 0X4B: TEMP_COUNTER_HIGH
Bits [2:0] of this register hold the 3 MSBs of the 11-bit
temperature code.
FN7574.2
December 10, 2012
ISLA216P
Bit [7] of this register indicates a valid temperature_counter read
was performed. A logic ‘1’ indicates a valid read.
ADDRESS 0X4C: TEMP_COUNTER_LOW
Bits [7:0] of this register hold the lower 8 LSBs of the 11-bit
temperature code.
ADDRESS 0X4D: TEMP_COUNTER_CONTROL
Bit [7] Measurement mode select bit, set to ‘1’ for recommended
PTAT mode. ‘0’ (default) is IPTAT mode and is less accurate and
not recommended.
Bit [6] Temperature counter enable bit. Set to ‘1’ to enable.
Bit [5] Temperature counter power down bit. Set to ‘1’ to
power-down temperature counter.
Bit [4] Temperature counter reset bit. Set to ‘1’ to reset count.
Bit [3:1] Three bit frequency divider field. Sets temperature
counter update rate. Update rate is proportional to ADC sample
clock rate and divide ratio. A ‘101’ updates the temp counter
every ~ 66µs (for 250MSPS). Faster updates rates result in lower
precision.
Bit [0] Select sampler bit. Set to ‘0’.
This set of registers provides digital access to an PTAT or
IPTAT-based temperature sensor, allowing the system to
estimate the temperature of the die, allowing easy access to
information that can be used to decide when to recalibrate the
A/D as needed.
The nominal transfer function of the temperature monitor should
be estimated for each device by reading the temperature sensor
at two temperatures and extrapolating a line through these two
points.
A typical temperature measurement can occur as follows:
1. Write ‘0xCA’ to address 0x4D - enable temp counter,
divide=’101’
2. Wait ≥ 132µs (at 250Msps) - longer wait time ensures the
sensor completes one valid cycle.
3. Write ‘0x20’ to address 0x4D - power down, disable temp
counter-recommended between measurements. This
ensures that the output does not change between MSB and
LSB reads.
4. Read address 0x4B (MSBs)
5. Read address 0x4C (LSBs)
6. Record temp code value
7. Write ‘0x20’ to address 0x4D - power-down, disable temp
counter. Contact the factory for more information if needed.
28
FN7574.2
December 10, 2012
ISLA216P
Device Config/Control
DUT Info
SPI Config/Control
SPI Memory Map
ADDR.
(Hex)
PARAMETER NAME
BIT 7 (MSB)
BIT 6
BIT 5
00
port_config
SDO Active
LSB First
Soft Reset
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
Mirror (bit5) Mirror (bit6) Mirror (bit7)
01
Reserved
Reserved
02
burst_end
Burst end address [7:0]
03-07
Reserved
Reserved
DEF. VALUE
(HEX)
00h
00h
08
chip_id
Chip ID #
Read only
09
chip_version
Chip Version #
Read only
0A-0F
Reserved
Reserved
10-1F
Reserved
Reserved
20
offset_coarse_adc0
Coarse Offset
cal. value
21
offset_fine_adc0
Fine Offset
cal. value
22
gain_coarse_adc0
23
gain_medium_adc0
24
gain_fine_adc0
25
modes_adc0
26
offset_coarse_adc1
27
offset_fine_adc1
28
gain_coarse_adc1
Reserved
Coarse Gain
cal. value
Medium Gain
cal. value
Fine Gain
Reserved
cal. value
00h
NOT reset by
Soft Reset
Power Down Mode ADC0 [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
100 = Sleep
Other codes = Reserved
Coarse Offset
cal. value
Fine Offset
Reserved
cal. value
Coarse Gain
cal. value
29
gain_medium_adc1
Medium Gain
cal. value
2A
gain_fine_adc1
Fine Gain
cal. value
2B
modes_adc1
Reserved
2C-2F
Reserved
Reserved
30-4A
Reserved
Reserved
4B
temp_counter_high
4C
temp_counter_low
4D
temp_counter_control
4E-6F
Reserved
70
skew_diff
71
phase_slip
72
clock_divide
00h
NOT reset by
Soft Reset
Power Down Mode ADC1 [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
100 = Sleep
Other codes = Reserved
Temp Counter [10:8]
Read only
Temp Counter [7:0]
Enable
PD
Reset
Read only
Divider [2:0]
Select
00h
Reserved
Differential Skew
Reserved
80h
Next Clock
Edge
Clock Divide [2:0]
000 = Pin Control
001 = divide by 1
010 = divide by 2
100 = divide by 4
Other codes = Reserved
29
00h
00h
NOT reset by
Soft Reset
FN7574.2
December 10, 2012
ISLA216P
Device Config/Control
SPI Memory Map (Continued)
ADDR.
(Hex)
PARAMETER NAME
73
output_mode_A
Output Mode [7:5]
000 = LVDS 3mA (Default)
001 = LVDS 2mA
100 = LVCMOS
Other codes = Reserved
74
output_mode_B
DLL Range
0 = Fast
1 = Slow
Default=’0’
75-B5
Reserved
B6
cal_status
B7-BF
Reserved
C0
test_io
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 1
BIT 0 (LSB)
Output Format [2:0]
000 = Two’s Complement (Default)
010 = Gray Code
100 = Offset Binary
Other codes = Reserved
Reserved
DEF. VALUE
(HEX)
00h
NOT reset by
Soft Reset
00h
NOT reset by
Soft Reset
Reserved
Calibration
Done
Output Test Mode [7:4]
Read Only
00h
User Test Mode [2:0]
0 = user pattern 1 only
1 = cycle pattern 1,3
2 = cycle pattern 1,3,5
3 = cycle pattern 1,3,5,7
4-7 = NA
0 = Off (Note 17)
1 = Midscale Short
2 = +FS Short
3 = -FS Short
4 = Reserved (Note18)
5-6 = Reserved
7 = Reserved (Note19)
8 = User Pattern (1 to 4 deep)
9 = Reserved
10 = Ramp
11-15 = Reserved
Device Test
BIT 2
C1
user_patt1_lsb
B7
B6
B5
B4
B3
B2
B1
B0
0x00
C2
user_patt1_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C3
user_patt2_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C4
user_patt2_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C5
user_patt3_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C6
user_patt3_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C7
user_patt4_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C8
user_patt4_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C9
user_patt5_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
CA
user_patt5_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
CB
user_patt6_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
CC
user_patt6_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
CD
user_patt7_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
CE
user_patt7_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
CF
user_patt8_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
B15
B14
B13
B12
B11
B10
B9
B8
00h
Enable
1 = Enable
00h
D0
user_patt8_msb
D1-FD
Reserved
FE
Offset/Gain_Adjust_Enable
FF
Reserved
Reserved
Reserved
Reserved
NOTES:
17. During Calibration xCCCC (MSB justified) is presented at the output data bus, toggling on the LSB (and higher) data bits occurs at completion of
calibration. This behavior can be used as an option to determine calibration state.
18. Use test_io = 0x80 and User Pattern 1 = 0x9999 for Checkerboard outputs on DDR Outputs.
19. Use test_io = 0x80 and User Pattern 1 = 0xAAAA for all ones/zeroes outputs on DDR Outputs
30
FN7574.2
December 10, 2012
ISLA216P
Equivalent Circuits
AVDD
TO
CLOCK-PHASE
GENERATION
AVDD
CLKP
AVDD
AVDD
CSAMP
9pF
TO
CHARGE
PIPELINE
INP
E2
E1
300
AVDD
TO
CHARGE
PIPELINE
INN
E2
E1
18k
E3
CSAMP
9pF
AVDD
11k
CLKN
E3
FIGURE 42. ANALOG INPUTS
AVDD
18k
11k
FIGURE 43. CLOCK INPUTS
AVDD
(20k PULL-UP
ON RESETN
ONLY)
AVDD
75k
AVDD
OVDD
TO
SENSE
LOGIC
75k
280
INPUT
OVDD
OVDD
20k
INPUT
75k
TO
LOGIC
280
75k
FIGURE 45. DIGITAL INPUTS
FIGURE 44. TRI-LEVEL DIGITAL INPUTS
OVDD
2mA OR
3mA
OVDD
DATA
DATA
OVDD
OVDD
D[14:0]P
OVDD
DATA
D[14:0]
D[14:0]N
DATA
DATA
2mA OR
3mA
FIGURE 46. LVDS OUTPUTS
31
FIGURE 47. CMOS OUTPUTS
FN7574.2
December 10, 2012
ISLA216P
Equivalent Circuits (Continued)
AVDD
VCM
0.94V
+
–
FIGURE 48. VCM_OUT OUTPUT
A/D Evaluation Platform
LVDS Outputs
Intersil offers an A/D Evaluation platform which can be used to
evaluate any of Intersil’s high speed A/D products. The platform
consists of a FPGA based data capture motherboard and a family
of A/D daughtercards. This USB based platform allows a user to
quickly evaluate the A/D’s performance at a user’s specific
application frequency requirements. More information is
available at
http://www.intersil.com/converters/adc_eval_platform/
Output traces and connections must be designed for 50Ω (100Ω
differential) characteristic impedance. Keep traces direct and
minimize bends where possible. Avoid crossing ground and
power-plane breaks with signal traces.
Layout Considerations
Split Ground and Power Planes
Data converters operating at high sampling frequencies require
extra care in PC board layout. Many complex board designs
benefit from isolating the analog and digital sections. Analog
supply and ground planes should be laid out under signal and
clock inputs. Locate the digital planes under outputs and logic
pins. Grounds should be joined under the chip.
Clock Input Considerations
Use matched transmission lines to the transformer inputs for the
analog input and clock signals. Locate transformers and
terminations as close to the chip as possible.
Exposed Paddle
The exposed paddle must be electrically connected to analog
ground (AVSS) and should be connected to a large copper plane
using numerous vias for optimal thermal performance.
Bypass and Filtering
Bulk capacitors should have low equivalent series resistance.
Tantalum is a good choice. For best performance, keep ceramic
bypass capacitors very close to device pins. Longer traces will
increase inductance, resulting in diminished dynamic
performance and accuracy. Make sure that connections to
ground are direct and low impedance. Avoid forming ground
loops.
32
LVCMOS Outputs
Output traces and connections must be designed for 50Ω
characteristic impedance.
Unused Inputs
Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO) which will
not be operated do not require connection to ensure optimal A/D
performance. These inputs can be left floating if they are not
used. Tri-level inputs (NAPSLP) accept a floating input as a valid
state, and therefore should be biased according to the desired
functionality.
Definitions
Analog Input Bandwidth is the analog input frequency at which
the spectral output power at the fundamental frequency (as
determined by FFT analysis) is reduced by 3dB from its full-scale
low-frequency value. This is also referred to as Full Power
Bandwidth.
Aperture Delay or Sampling Delay is the time required after the
rise of the clock input for the sampling switch to open, at which
time the signal is held for conversion.
Aperture Jitter is the RMS variation in aperture delay for a set of
samples.
Clock Duty Cycle is the ratio of the time the clock wave is at logic
high to the total time of one clock period.
Differential Non-Linearity (DNL) is the deviation of any code width
from an ideal 1 LSB step.
FN7574.2
December 10, 2012
ISLA216P
Effective Number of Bits (ENOB) is an alternate method of
specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it
is calculated as: ENOB = (SINAD - 1.76)/6.02
Gain Error is the ratio of the difference between the voltages that
cause the lowest and highest code transitions to the full-scale
voltage less than 2 LSB. It is typically expressed in percent.
I2E The Intersil Interleave Engine. This highly configurable
circuitry performs estimates of offset, gain, and sample time
skew mismatches between the core converters, and updates
analog adjustments for each to minimize interleave spurs.
Integral Non-Linearity (INL) is the maximum deviation of the
A/D’s transfer function from a best fit line determined by a least
squares curve fit of that transfer function, measured in units of
LSBs.
Least Significant Bit (LSB) is the bit that has the smallest value or
weight in a digital word. Its value in terms of input voltage is
VFS/(2N-1) where N is the resolution in bits.
Missing Codes are output codes that are skipped and will never
appear at the A/D output. These codes cannot be reached with
any input value.
Most Significant Bit (MSB) is the bit that has the largest value or
weight.
Pipeline Delay is the number of clock cycles between the
initiation of a conversion and the appearance at the output pins
of the data.
Power Supply Rejection Ratio (PSRR) is the ratio of the observed
magnitude of a spur in the A/D FFT, caused by an AC signal
superimposed on the power supply voltage.
Signal to Noise-and-Distortion (SINAD) is the ratio of the RMS
signal amplitude to the RMS sum of all other spectral
components below one half the clock frequency, including
harmonics but excluding DC.
Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS
signal amplitude to the RMS sum of all other spectral
components below one-half the sampling frequency, excluding
harmonics and DC.
SNR and SINAD are either given in units of dB when the power of
the fundamental is used as the reference, or dBFS (dB to full
scale) when the converter’s full-scale input power is used as the
reference.
Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS
signal amplitude to the RMS value of the largest spurious
spectral component. The largest spurious spectral component
may or may not be a harmonic.
33
FN7574.2
December 10, 2012
ISLA216P
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
CHANGE
November 28, 2012
FN7574.2
Datasheet update for better accuracy and clarity.
April 15, 2011
FN7574.1
-Updated Ordering Information by Changing Eval board name from ISLA216P25EVAL TO ISLA216IR72EV1Z
and updating description
-Electrical Specifications Table change:
DC Specifications ->Analog Input->Common-Mode Input Current (per pin) -> TYP "10.8" to "5.2"
Added CMOS Power Typical Specs under Total Power Dissipation ->Normal Mode
Digital Specifications Table ->Input Capacitance->TYP "3" to "4"
Digital Specifications Table ->LVDS INPUTS (CLKRSTP, CLKRSTN) TO LVDS INPUTS (CLKDIVRSTP,
CLKDIVRSTN)
-Updated temperature calibration curves
-Added clkdiv description in Clock Input Section
-Removed '2-wire mode' text in "Address 0x02:Burst_End" section
-Updated Bit6 at Address 0x74:Output_Mode_B section
January 13, 2011
FN7574.0
Initial Release
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the fastest growing markets within the industrial and infrastructure,
personal computing and high-end consumer markets. For more information about Intersil or to find out how to become a member of
our winning team, visit our website and career page at www.intersil.com.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective product information page.
Also, please check the product information page to ensure that you have the most updated datasheet: ISLA216P
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
Reliability reports are available from our website at: http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
34
FN7574.2
December 10, 2012
ISLA216P
Package Outline Drawing
L72.10x10E
72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 11/09
A
X
10.00
9.75
72
Z
EXPOSED
PAD AREA
B
6
PIN #1
INDEX AREA
72
1
1
6
PIN 1
INDEX AREA
8.500 REF. (4X)
9.75
3.000
REF.
6.000 REF.
10.00
0.100 M C A B
(4X)
0.15
4.150 REF.
TOP VIEW
7.150 REF.
0.100 M C A B
BOTTOM VIEW
11°
ALL AROUND
9.75 ±0.10
Y
C0.400X45° (4X)
10.00 ±0.10
(0.350)
0.450
R0.200
SIDE VIEW
25
.1
(0
(4X 9.70)
LL
A
A
O
R
D
N
)
1
C0.190X45°
(4.15 REF)
U
(1.500)
(7.15)
0.500 ±0.100
72
R0.115 TYP.
(3.00 )
(4X 8.50)
(6.00)
DETAIL "Z"
R0.200 MAX.
ALL AROUND
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ANSI Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.10
Angular ±2.50°
4.
Dimension applies to the metallized terminal and is measured
between 0.015mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
7.
Package outline compliant to JESD-M0220.
0.190~0.245
SEATING
PLANE
0.080 C
0.50
0.025 ±0.020
0.23 ±0.050
0.85 ±0.050
0.100 C
( 72X 0 .70)
0.650 ±0.050
( 72X 0 .23)
DETAIL "X"
C
0.100 M C A B
0.050 M C
DETAIL "Y"
either a mold or mark feature.
35
FN7574.2
December 10, 2012
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