DATASHEET

ISL5586
®
Data Sheet
November 3, 2004
Low Power Ringing SLIC for Home
Gateways
FN4924.2
Features
• Interfaces to Broadcom 3352 cable modem device
• Very low on-hook power consumption
- 64mW @ Vbh = 75V
• User Programmable constant current to the subscriber
loop
• On Chip ring generation
- Balanced to 95Vpk
• Sinewave, Trapezoid, DC offset
• Programmable loop start and ring trip detectors
• Loop start, Ground Start, Polarity Reversal (soft/hard)
• On-Hook transmission and pulse metering support
• Integrated battery switch
• Open circuit line voltage clamp
• Compatible with 3.3V devices
• TR-57 compliant Longitudinal balance
• 28 PLCC packaging
• Latch-up free Bipolar design
• Thermal protection
• Pb-Free Available (RoHS Compliant)
The ISL5586 is a very low
power Ringing Subscriber
Interface circuit designed for
use with the Broadcom
BCM3352 Cable Modem Chip,
with on-board voiceband codecs, or other 3.3V voiceband
codec devices.
The ISL5586 provides on board ringing signal generation up
to 95V peak supporting sinusoidal or trapezoidal
waveshapes with DC offset. Loop start and ground start
trunks are supported, and an open circuit DC voltage of less
than 56V is maintained on the subscriber loop in the on-hook
condition, in compliance with MTU operation and the safety
requirements of UL-1950.
Together with the Broadcom BCM3352, the ISL5586
provides resistive and complex two wire impedance
matching and transhybrid balancing. Also supported are onhook transmission of caller id signals, soft and hard polarity
reversal and 12/16kHz subscriber pulse metering systems
used in Europe and Asia, thereby allowing a low cost, low
risk, global product design to be achieved.
Applications
•
•
•
•
•
•
•
Related Literature
• Evaluation Board for the ISL5586 family AN9918
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Cable Modems
Voice Over DSL (VoDSL)
Broadband Wireless Access
Voice Over Internet Protocol (VoIP)
ISDN Terminal Adapters (TA)
Small Office Home Office PBX
Wireless Local Loop
Block Diagram
POL CDCP CDCM
ILIM
TIP
RING
TL
DC
CONTROL
VBL
VBH
BATTERY
SWITCH
RINGING
PORT
VRSM
VRXP
2-WIRE
PORT
TRANSIENT
CURRENT
LIMIT
VRSP
VRXM
TRANSMIT
SENSING
4-WIRE
PORT
-IN
VZO
VFB
VTXP
VTXM
INTERNAL
LOOP BACK
DETECTOR
LOGIC
RTD RD
1
DET
CONTROL
LOGIC
F2
F1
F0
BSEL
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2000, 2001, 2004. All Rights Reserved
RSLIC18™ is a trademark of Intersil Corporation. All other trademarks mentioned are the property of their respective owners.
ISL5586
Ordering Information
LONGITUDINAL
BALANCE
HIGH BATTERY (VBH)
PART NUMBER
100V
85V
75V
58dB
53dB
TEMP.
RANGE (°C)
PKG.
DWG. #
PACKAGE
ISL5586FCM
•
•
0 to 75
28 Ld PLCC
N28.45
ISL5586FCMZ (Note)
•
•
0 to 75
28 Ld PLCC (Pb-free)
N28.45
ISL5586FCMZ-T (Note)
•
•
0 to 75
28 Ld PLCC Tape and Reel (Pb-free)
N28.45
ISL5586BIM
•
•
-40 to 85
28 Ld PLCC
N28.45
ISL5586BIMZ (Note)
•
•
-40 to 85
28 Ld PLCC (Pb-free)
N28.45
ISL5586CIM
•
•
-40 to 85
28 Ld PLCC
N28.45
ISL5586CIMZ (Note)
•
•
-40 to 85
28 Ld PLCC (Pb-free)
N28.45
ISL5586DIM
•
•
-40 to 85
28 Ld PLCC
N28.45
ISL5586DIMZ (Note)
•
•
-40 to 85
28 Ld PLCC (Pb-free)
N28.45
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
Device Operating Modes
MODE
F2
F1
F0
DET
DESCRIPTION
Low Power Standby (LPS)
0
0
0
SHD
MTU compliant on hook operating mode.
Forward Active (FA)
0
0
1
SHD
MTU compliant and OHT capable on hook mode, off hook loop feed mode.
Unused
0
1
0
n/a
Reverse Active (RA)
0
1
1
SHD
Signalling mode which reverses direction of loop current, otherwise like Forward Active.
Ringing
1
0
0
RTD
Signalling mode used to generate high voltage balanced ringing signal.
Forward Loop Back (FLB)
1
0
1
SHD
Internal loop back mode which connects internal load across Tip and Ring terminals.
Tip Open/Ground Start (TO)
1
1
0
SHD
Signalling mode sets Tip to high impedance state, Ring output still active.
Power Denial (PD)
1
1
1
n/a
Loop disconnect mode which forces both Tip and Ring to high impedance.
Reserved for internal purposes.
Pinout
2
VBH
VBL
BGND
TIP
RING
RD
ILIM
ISL5586 (PLCC)
TOP VIEW
4
3
2
1
28
27
26
BSEL
5
25 RTD
F2
6
24 CDCM
F1
7
23 CDCP
F0
8
22 VCC
DET
9
21 TL
VRSP
10
VRSM
11
20 VFB
13
14
15
16
17
18
VTXP
VTXM
AGND
POL
VRXP
VRXM
VZO
19 -IN
12
FN4924.2
November 3, 2004
ISL5586
Absolute Maximum Ratings TA = 25oC
Thermal Information
Maximum Supply Voltages
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
VCC - VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110V
ESD (Human Body Model) . . . . . . . . . . . . . . . . . . . . . . . . . . 500V
Maximum Tip/Ring Negative Voltage Pulse (Note 7) . . . . . .VBH-15V
Maximum Tip/Ring Positive Voltage Pulse (Note 7). . . . . . . . . . + 8V
Thermal Resistance (Typical, Note 1)
PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(PLCC - Lead Tips Only)
Operating Conditions
Die Characteristics
Temperature Range
Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Positive Power Supply (VCC). . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V
Negative Power Supply (VBH, VBL) . . . . . . . . . . . . . . -100V to -24V
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VBH
Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
θJA (oC/W)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Unless Otherwise Specified, TA = -40oC to 85oC, VBL = -24V, VBH = -100V, VCC = +5V, AGND = BGND = 0V,
loop current limit = 25mA. All AC Parameters are specified at 600Ω, 2-wire terminating impedance over the
frequency band of 300Hz to 3.4kHz. Protection resistors = 0Ω . These parameters apply generically to each
product offering.
Electrical Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
RINGING PARAMETERS
VRSP Input Impedance (Note 2)
35
-
-
MΩ
VRSM input impedance (Note 2)
10
-
-
MΩ
V/V
Differential Ringing Gain (Note 3)
VRS to 2-Wire, RLOAD = 5 REN
-
99.5
-
Ringing voltage Total Distortion
RL = 1.3 kΩ, VT-R = |VBH| -5
-
0.8
5
%
4-Wire to 2-Wire Ringing Off Isolation
Forward Active Mode, Referenced to VRS Input.
-
100
-
dB
2-Wire to 4-Wire Transmit Isolation
Ringing Mode Referenced to the Differential
Ringing Amplitude.
-
100
-
dB
Centering Voltage Accuracy
Tip, Referenced to VBH/2 + 0.5V
-3.0
0.2
3.0
V
Ring, Referenced to VBH/2 + 0.5V
-3.0
0.2
3.0
V
Receive Input Impedance, VRXP (Note 2)
379
541
-
kΩ
Receive input Impedance, VRXM (Note 2)
100
142
-
kΩ
-
0.01
-
Ω
0.30
1.0
-
mA
AC TRANSMISSION PARAMETERS
Transmit Output Impedance (Note 2)
DC
Transmit Output Drive Capability (Note 2)
Current
-
1.0
100
pF
4-Wire Port Overload Level
Capacitance to Ground
THD = 1%
3.1
3.5
-
VPEAK
2-Wire Port Overload Level
THD = 1%
3.1
3.5
-
VPEAK
2-Wire Return Loss (Note 2)
200Hz ≤ f ≤ 1kHz
-
35
-
dB
1kHz ≤ f ≤ 3.4kHz
-
23
-
dB
20
-
-
mARMS
Longitudinal Current Capability per Wire (Note 2)
False Detect
False Detect in Low Power Standby
10
-
-
mARMS
2-Wire Longitudinal Balance (ON-Hook and OFF-Hook)
(Notes 4, 5)
200Hz, 500Hz, 1000Hz
58
61
-
dB
3000Hz
53
61
-
dB
4-Wire Longitudinal Balance (ON-Hook and OFF-Hook)
(Notes 4, 5)
200Hz, 500Hz, 1000Hz
58
64
-
dB
4-Wire to 2-Wire Insertion Loss
0dBmo at 1kHz
2-Wire to 4-Wire Insertion Loss
0dBmo at 1kHz
-0.2
0
0.2
dB
4-Wire to 4-Wire Insertion Loss
0dBmo at 1kHz
2.72
2.92
3.12
dB
Frequency Response, On Hook, 2-Wire to 4-Wire, 4-Wire Referenced to 0dBmo at 1004Hz,
to 2-Wire, 4-Wire to 4-Wire
400Hz ≤ f ≤ 2800Hz
-0.15
0.03
0.15
dB
Frequency Response, Off Hook
2-Wire to 4-Wire, 4-Wire to 2-Wire, 4-Wire to 4-Wire
-0.15
0.03
.15
dB
3
3000Hz
Referenced to 0dBmo at 1004Hz, f = 400Hz,
2800Hz
53
62
-
dB
2.72
2.92
3.12
dB
FN4924.2
November 3, 2004
ISL5586
Unless Otherwise Specified, TA = -40oC to 85oC, VBL = -24V, VBH = -100V, VCC = +5V, AGND = BGND = 0V,
loop current limit = 25mA. All AC Parameters are specified at 600Ω, 2-wire terminating impedance over the
frequency band of 300Hz to 3.4kHz. Protection resistors = 0Ω . These parameters apply generically to each
product offering. (Continued)
Electrical Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
0.02
-
dB
-37 to -50dBmo
-
0.05
-
dB
-50 to -55dBmo
-
0.10
-
dB
Amplitude Tracking, ON-Hook
0dBmo to -37dBmo, f = 1004Hz,
Referenced to 0dBmo
-
0.01
-
dB
Signal to Distortion, 2-Wire to 4-Wire, 4-Wire to 2-Wire,
4-Wire to 4-Wire, ON-Hook and OFF-Hook
Input level 0dBmo to -30dBmo
33
45
-
dB
Input Level -30 to -40dBmo
27
40
-
dB
Input Level -40 to -45dBmo
22
29
-
dB
Signal Frequency Distortion (0Hz to 12kHz)
0dBmo input, 0 Hz ≤ f ≤ 12kHz
28
45
-
dB
Single Frequency Distortion (0Hz to 4kHz)
0dBmo Input, 1004Hz ≤ f ≤ 1024Hz
40
50
-
dB
Intermodulation Distortion, 2-Wire to 4-Wire,
4-Wire to 2-Wire, 4-Wire to 4-Wire
(IEEE Standard 743-1984)
4-Tone Second-Order Intermodulation Products
43
50
-
dB
4-Tone Third-order Intermodulation Products
44
62
-
dB
Idle Channel Noise, 2-Wire (Note 5)
C-Message, Forward Active, Low Battery Enabled
-
10.0
13.0
dBrnc
Idle Channel Noise, 4-Wire (Note 5)
C-Message, Forward Active, Low Battery Enabled
-
10.0
13.0
dBrnc
Amplitude Tracking, Off Hook, 2-Wire to 4-Wire, 4-Wire to +3dBmo to -37dBmo, f = 1004Hz,
2-Wire, 4-Wire to 4-Wire
Referenced to 0dBmo
DC PARAMETERS
OFF-Hook Loop Current Limit
Programming Accuracy (1% External Resistor)
OFF-Hook Transient Current Limit
-8.5
1.0
+8.5
%
Programming Range
15
-
45
mA
Programming Accuracy
-10
-
+10
%
Programming Range
40
-
100
mA
Loop Current During Low Power Standby
Forward Polarity Only (RL = 600Ω)
-
24
-
mA
Open Circuit Voltage
(|Tip - Ring|)
Forward and Reverse Active modes
VBL = -16V
-
7.0
-
VDC
VBL = -24V
13.5
14.5
16.5
VDC
VBH > -60V
43
48
-
VDC
Open Circuit Voltage (|Tip-Ring|) LPS
VBH > -60V
43
51
-
VDC
Absolute Open Circuit Voltage (Relative to GND)
VRG in FA, VTG in RA, VBH > -60V
-
-53
-56
VDC
Absolute Open Circuit Voltage
VRG in LPS
-
-52
-56
VDC
-
-
52
V
TEST ACCESS FUNCTIONS
Loopback Max Battery
LOOP DETECTORS AND SUPERVISORY FUNCTIONS
Switch Hook Programming Range
5
-
15
mA
-10
-
+10
%
-
1.0
-
%
Ring Trip Comparator Threshold
2.3
2.60
2.9
V
Ring Trip Programming Current Accuracy
-10
-
+10
%
-
175
-
oC
Switch Hook Programming Accuracy
Assumes 1% External Programming Resistor
Dial Pulse Distortion
Thermal Shutdown Threshold
IC Junction Temperature
LOGIC INPUTS (F0, F1, F2, BSEL)
Input Low Voltage
-
-
0.8
V
Input High Voltage
2.0
-
-
V
µA
Input Low Current (F0, F1, F2)
VIL = 0.4V
-
7.5
20
Input Low Current (BSEL)
VIL = 0.4V
-
1.0
-
µA
Input High Current (F0, F1, F2, BSEL)
VIH = 2.4V
-
0.01
-
µA
-
0.15
0.4
V
2.4
3.2
3.5
V
mA
LOGIC OUTPUT (DET)
Output Low Voltage
IOL = 5mA
Output High Voltage
IOH = 100µA
SUPPLY CURRENTS
Low Power Standby, BSEL = 2.0V, VBH = -75V to -100V ICC
-
3.2
5.0
IBH
-
0.65
0.9
mA
ICC
-
5.0
6.5
mA
IBL
-
1.5
2.5
mA
Forward or Reverse, BSEL =.8V
4
FN4924.2
November 3, 2004
ISL5586
Unless Otherwise Specified, TA = -40oC to 85oC, VBL = -24V, VBH = -100V, VCC = +5V, AGND = BGND = 0V,
loop current limit = 25mA. All AC Parameters are specified at 600Ω, 2-wire terminating impedance over the
frequency band of 300Hz to 3.4kHz. Protection resistors = 0Ω . These parameters apply generically to each
product offering. (Continued)
Electrical Specifications
PARAMETER
Forward Active, BSEL = 2.0V, VBH = -100V
Forward Active, BSEL = 2.0V, VBH = -85V
Forward Active, BSEL = 2.0V, VBH = -75V
Ringing, BSEL = 2.0V, VBH = -100V
Ringing, BSEL = 2.0V, VBH = -85V
Ringing, BSEL = 2.0V, VBH = -75V
MIN
TYP
MAX
UNITS
ICC
TEST CONDITIONS
-
7.0
9.0
mA
IBL
-
1.4
2.0
mA
IBH
-
1.8
3.0
mA
ICC
-
6.6
8.5
mA
IBL
-
1.35
2.0
mA
IBH
-
1.60
2.75
mA
ICC
-
6.3
8.0
mA
IBL
-
1.25
2.0
mA
IBH
-
1.45
2.5
mA
ICC
-
7.4
10.0
mA
IBL
-
1.5
2.0
mA
IBH
-
2.2
3.0
mA
ICC
-
6.80
9.25
mA
IBL
-
1.36
2.0
mA
IBH
-
2.1
3.0
mA
ICC
-
6.4
8.5
mA
IBL
-
1.26
2.0
mA
IBH
-
2.0
3.0
mA
Forward Loopback, BSEL = 0.8V, VBL = -24V
ICC
-
10.3
13.5
mA
IBL
-
23.0
32.0
mA
Tip Open, BSEL = 2.0V
ICC
-
3.2
-
mA
IBL
-
0.1
-
mA
ICC
-
3.4
6.0
mA
IBL
-
0.22
0.50
mA
Power Denial, BSEL = 0.8V or 2.0V
ON HOOK POWER DISSIPATION (Note 6)
Forward or Reverse
VBL = -24V
-
57
-
mW
Low Power Standby
VBH = -100V
-
83
-
mW
VBH = -85V
-
70
-
mW
VBH = -75V
-
64
-
mW
VBH = -100V
-
294
-
mW
VBH = -85V
-
236
-
mW
VBH = -75V
-
206
-
mW
VBL = -24V, ILIM = 25mA, RL = 300Ω
-
305
-
mW
Ringing
OFF HOOK POWER DISSIPATION (Note 6)
Forward or Reverse
POWER SUPPLY REJECTION RATIO
VCC to 2-Wire, BSEL = 0.8V
VCC to 4-Wire, BSEL = 0.8V
VBL to 2-Wire, BSEL = 0.8V
VBL to 4-Wire, BSEL = 0.8V
VBH to 2-Wire, BSEL = 2.0V
5
f = 50kHz
-
50
-
dB
f = 300Hz ≤ f ≤ 3400Hz
-
45
-
dB
f = 8kHz ≤ f ≤ 16kHz
-
28
-
dB
f = 50Hz
-
70
-
dB
f = 300Hz ≤ f ≤ 3400Hz
-
55
-
dB
f = 8kHz ≤ f ≤ 16kHz
-
40
-
dB
f = 50Hz
-
25
-
dB
f = 300Hz ≤ f ≤ 3400Hz
-
38
-
dB
f = 8kHz ≤ f ≤ 16kHz
-
28
-
dB
f = 50Hz
-
27
-
dB
f = 300Hz ≤ f ≤ 3400Hz
-
36
-
dB
f = 8kHz ≤ f ≤ 16kHz
-
23
-
dB
f = 50Hz
-
27
-
dB
f = 300Hz ≤ f ≤ 3400Hz
-
35
-
dB
f = 8kHz ≤ f ≤ 16kHz
-
23
-
dB
FN4924.2
November 3, 2004
ISL5586
Unless Otherwise Specified, TA = -40oC to 85oC, VBL = -24V, VBH = -100V, VCC = +5V, AGND = BGND = 0V,
loop current limit = 25mA. All AC Parameters are specified at 600Ω, 2-wire terminating impedance over the
frequency band of 300Hz to 3.4kHz. Protection resistors = 0Ω . These parameters apply generically to each
product offering. (Continued)
Electrical Specifications
PARAMETER
VBH to 4-Wire, BSEL = 2.0V
MIN
TYP
MAX
UNITS
f = 50Hz
TEST CONDITIONS
-
76
-
dB
f = 300Hz ≤ f ≤ 3400Hz
-
55
-
dB
f = 8kHz ≤ f ≤ 16kHz
-
42
-
dB
NOTES:
2. These parameters are controlled via design and Statistical Process Control and are not directly tested. These parameters are characterized upon
initial design release and upon design changes which would affect these characteristics.
3. Input voltage = 0.636VRMS for VBH = -100V, 0.530VRMS for VBH = -85V and 0.460VRMS for -75V devices.
4. Tested per IEEE455-1985, with 368Ω resistors connected to the Tip and Ring terminals.
5. These parameters are tested 100% at room temperature, and are guaranteed but not tested across the full temperature range via statistical
characterization and design.
6. The power dissipation is based on actual device measurements and will be less than worst case calculations based on data sheet supply current limits.
7. Characterized with 2 x 10us and 10 x 1000us first level lightning surge waveform (GR-1089-CORE).
Design Equations
Refer to Figure 14 for programming resistor connections.
Loop Supervision Thresholds
SWITCH HOOK DETECT
The desired switch hook detect threshold current (ISH) is set by
a single external resistor, RSH as follows
(EQ. 1)
R SH = 615 ⁄ I SH
The loop current threshold programming range is from 5mA
to 15mA.
RING TRIP DETECT
The ring trip detect threshold (IRT) is set by a single external
resistor, RRT as follows.
(EQ. 2)
R RT = 1800 ⁄ I RT
IRT should be set between the peak ringing current and the
peak off hook current while still ringing. In addition, the ring
trip current must be set below the transient current limit
including tolerances. The ringing signal filter capacitor CRT,
in parallel with RRT sets the ring trip response time.
LOOP CURRENT LIMIT
The AC source resistance of the SLIC is synthesized with a
single external resistor RS as follows:
400
R S = Z 0 ×  ---------- = 133.3 ( Z 0 )
 3 
(EQ. 4)
The synthesized resistance (Z0) is determined by the
characteristic line resistance and protection resistors as
shown in Equation 5.
(EQ. 5)
Z O = R L – ( RP 1 + RP 2 )
COMPLEX IMPEDANCE SYNTHESIS
A complex network is used in place of RS when the termination
impedance of the line is complex as shown in Figure 1.
2-WIRE TERMINATION
IMPEDANCE (ZL)
C2
R1
PROGRAMMING
NETWORK (ZS)
CP
RS
RP
FIGURE 1. COMPLEX PROGRAMMING NETWORK
(EQ. 3)
The loop current limit programming range is from 15mA to
45mA.
Impedance Matching
The AC source impedance of the SLIC is programmed with
the external impedance network ZS as described next. To
synthesize and match Resistive line terminations the
programming network is simply a resistor (RS) as shown in
6
RESISTIVE IMPEDANCE SYNTHESIS
R2
The DC loop current limit (ILIM) is programmed by the
external resistor RIL as follows.
1760
R IL = ------------I LIM
Figure 14. For complex line terminations such as the one
illustrated in Figure 1, a complex programming network is
required.
The component RS has a different design equation than the
RS used for resistive impedance synthesis. The design
equations for each component are provided below where
RP1 and RP2 are the protection resistors and RP is a
component of the programming network.
R S = 133.3 × ( R1 – RP 1 – RP 2 )
(EQ. 6)
R P = 133.3 × R 2
(EQ. 7)
FN4924.2
November 3, 2004
ISL5586
C P = C 2 ⁄ 133.3
(EQ. 8)
Z O = ( R1 – RP1 – RP2 ) + R2 C2
(EQ. 9)
4-WIRE TO 2-WIRE GAIN
The 4-wire to 2-wire gain (G42) is defined as the receive
gain. It is a function of the terminating impedance,
synthesized impedance and protection resistors. The gain is
defined from the Receive input terminals (VRXP, VRXM) to
the terminating impedance (ZL) on the 2-wire side, and is
illustrated in Figure 12.
ZL


G 42 = – 2.8  ------------------------------------------
 Z O + 2R P + Z L
(EQ. 10)
When the device source impedance and the protection
resistors equal the terminating impedance, the receive gain
equals 2.92dB and is inverted with respect to the input.
2-WIRE TO 4-WIRE GAIN
The 2-wire to 4-wire gain (G24) is the gain from tip and ring to
the transmit differential output. The transmit gain is given by
Equation 11. Note that VTR is defined on the line side of the
protection resistors (reference Figure 13). With ZL set to 600
ohms, the protection resistors set to 50Ω/terminal and
Z0 = ZL-2RP the Transmit gain equals -0.833 (-1.59dB) and
is inverted with respect to the 2-wire input (VTR).
ZO


G 24 = – 2  ------------------------------------------
Z
+
2R
+
Z
 O
P
L
For example, a source current limit setting of 50mA is
programmed with a 35.6kΩ resistor connected from pin 16 of
the device to ground. This setting determines the maximum
amount of current which flows from Tip to Ring during an off
hook event until the DC loop current limit responds. In addition
this setting also determines the amount of current which will
flow from Tip or Ring when external battery faults occur.
SINK CURRENT PROGRAMMING
The sink current limit is internally offset 20% higher than the
externally programmed source current limit setting.
(EQ. 14)
I SNK = 1.20 × I SRC
If the source current limit is set to 50mA, the sink current limit
will be 60mA. This setting will determine the amount of current
which flows into Tip or Ring when external ground faults occur.
FUNCTIONAL DESCRIPTION
Each amplifier is designed to limit source current and sink
current. The diagram below shows the functionality of the
circuit for the case of limiting the source current. A similar
diagram applies to the sink current limit with current polarity
changed accordingly.
IO/K
IREF = 1.21/TL
IERR
200K
(EQ. 11)
+
TRANSHYBRID GAIN
The transhybrid gain is defined as the 4-wire to 4-wire gain
(G44) and is given by Equation 12 (Reference Figure 14)).
ISIG VB/2
TIP or RING
20
IO
FIGURE 2. CURRENT LIMIT FUNCTIONAL DIAGRAM
ZO


G 44 = – 2.8  ---------------------------------------
Z
+
2R
+
Z
 O
P
L
(EQ. 12)
Transient Current Limit
The drive current capability of the output amplifiers is
determined by an externally programmable output current
limit circuit which is separate from the DC loop current limit
function. The transient current limit is programmed with a
resistor to ground at the TL pin. The current limit circuit
works in both the source and sink direction, with an internally
fixed offset to prevent the current limit functions from turning
on simultaneously. The current limit function is provided by
sensing line current and reducing the voltage drive to the
load when the externally set threshold is exceeded, hence
forcing a constant source or sink current.
SOURCE CURRENT PROGRAMMING
The source current is externally programmed as shown in
Equation 13.
(EQ. 13)
1780
R TL = ------------I SRC
7
During normal operation, the error current (IERR) is zero and
the output voltage is determined by the signal current (ISIG)
multiplied by the 200K feedback resistor. With the current
polarity as shown for ISIG, the output voltage moves positive
with respect to half battery. Assuming the amplifier output is
driving a load at a more negative potential, the amplifier
output will source current.
During excessive output source current flow, the scaled
output current (IO/K) exceeds the reference current (IREF)
forcing an error current (IERR). With the polarity as shown
the error current subtracts from the signal current, which
reduces the amplifier output voltage. By reducing the output
voltage the source current to the load is decreased and the
output current is limited.
DETERMINING THE PROPER SETTING
Since this feature programs the maximum output current of
the device, the setting must be high enough to allow for
detection of ring trip or programmed off hook loop current,
whichever is greater.
FN4924.2
November 3, 2004
ISL5586
To allow for proper ring trip operation, the transient current
limit setting should be set at least 25% higher than the peak
ring trip current setting. Setting the transient current 25%
higher should account for programming tolerances of both
the ring trip threshold and the transient current limit.
GND
600Ω
TIP AMP
TIP
If loop current is larger than ring trip current (low REN
applications) then the transient current limit should be set at
least 35% higher than the loop current setting. The slightly
higher offset accounts for the slope of the loop current limit
function.
Attention to detail should be exercised when programming
the transient current limit setting. If ring trip detect does not
occur while ringing, then re-examine the transient current
limit and ring trip threshold settings.
Low Power Standby Mode
Overview
The low power standby mode (LPS, 000) should be used in
conjunction with the high battery during idle line conditions.
The SLIC is designed to operate from the high battery during
this mode so MTU compliance can be met. Most of the
internal circuitry is powered down, resulting in low power
dissipation. If MTU compliance is not required during idle line
conditions, the device may be operated from the low battery
which will decrease the standby power dissipation.
TABLE 1. DEVICE INTERFACES DURING LPS
INTERFACE
ON
OFF
NOTES
AC transmission, impedance
matching and ringing are
disabled during this mode.
Receive
-
x
Ringing
-
x
Transmit
-
x
2-Wire
x
-
Amplifiers disabled.
Loop Detect
x
-
Switch hook.
2-Wire Interface
In the LPS mode, the 2-wire interface is maintained with
internal switches, resistors, and voltage references. The Tip
and Ring amplifiers are turned off to conserve power. The
device will provide MTU compliance, loop current, and loop
supervision. Figure 2 represents the internal circuitry
providing the 2-wire interface when in this mode of operation.
RING
RING AMP
600Ω
MTU REF
FIGURE 3. LPS 2-WIRE INTERFACE CIRCUIT DIAGRAM
MTU Compliance
Maintenance Termination Unit or MTU compliance places
DC voltage requirements on the 2-wire terminals during idle
line conditions. The minimum idle voltage for compliance is
42.75V. The high side of the MTU range is 56V. The voltage
is expressed as the difference between Tip and Ring.
The Tip voltage is held near ground through a 600Ω resistor
and switch. The Ring voltage is nominally limited to -49V by
the MTU reference. A switch and 600Ω resistor connect the
MTU reference to the Ring terminal. When the high battery
voltage exceeds the MTU reference of -49V, the Ring
terminal will be clamped by the internal reference. The same
Ring relationships apply when operating from the low
battery. For operating battery voltages (VBH) less than or
equal to the internal MTU reference, the Ring voltage will be
approximately 4.5 volts more positive than VBH.
Loop Current
In the LPS mode, the device is capable of providing DC
current to a load through a path of resistors and switches.
The current available for switch hook detect is a function of
the off hook loop resistance (RLOOP). This includes the off
hook phone resistance and copper loop resistance. The
current available during LPS is given by Equation 15.
I LOOP = ( – 1 – ( – 49 ) ) ⁄ ( 600 + 600 + R LOOP )
(EQ. 15)
Internal current limiting of the standby switches will limit the
maximum current to approximately 23mA. The longitudinal
current capability is guaranteed to be greater than or equal to
10mARMS per pin. When longitudinal currents exceed this
level, false off hook detection may occur. The reduction in
longitudinal current capability with respect to the Forward Active
mode is a result of turning off the Tip and Ring amplifiers.
On Hook Power Dissipation
The on hook power dissipation of the SLIC in the LPS mode
is determined by the operating voltages and quiescent
currents and is calculated below.
P LPS = V BH × I BHQ + V BL × I BLQ + V CC × I CCQ
8
(EQ. 16)
FN4924.2
November 3, 2004
ISL5586
The quiescent current terms are specified in the electrical
tables for each operating mode. Load power dissipation is
not a factor since this is an on hook mode. Some
applications may specify a standby current. The standby
current may be a charging current required for modern
telephone electronics.
RB
VIN
RCS
+
RL
(EQ. 18)
Most applications do not specify charging current
requirements during standby. When specified, the typical
charging current may be as high as 5mA.
Forward Active Mode
Overview
The Forward Active mode (FA, 001) is the primary AC
transmission mode of the SLIC. On hook transmission, DC loop
feed and voice transmission are supported during this mode.
The device may be operated from either high or low battery for
on-hook transmission and from low battery for loop feed.
Loop supervision is provided by the switch hook detector at
the DET output. When DET goes low, the low battery should
be selected for DC loop feed and voice transmission.
On-Hook Transmission
The primary purpose of on hook transmission will be to
support caller ID and other advanced signalling features.
The transmission over load level while on hook is 3.1VPEAK .
When operating from the high battery, the DC voltages at Tip
and Ring are MTU compliant. The typical Tip voltage is -4V
and the Ring voltage is a function of the battery voltage for
battery voltages less than -60V as shown in Equation 19.
(EQ. 19)
Feed Architecture
The SLIC design implements a voltage feed current sense
architecture. The voltage across Tip and Ring is controlled
by sensing the load current. Resistors are placed in series
with the Tip and Ring outputs to provide the current sensing
function. The diagram below illustrates the concept.
9
+
KS
FIGURE 4. VOLTAGE FEED CURRENT SENSE DIAGRAM
By monitoring the current at the amplifier outputs, a negative
feedback mechanism sets the output voltage for a defined
load. The amplifier closed loop gains are set by internal
resistor ratios (RA , RB , RC) providing all the performance
benefits of matched resistors. The internal sense resistor
RCS , is much smaller than the gain resistors and are
typically 20Ω. The feedback mechanism, KS , represents the
gain configuration providing negative feedback to the loop.
DC Loop Feed
The feedback mechanism for monitoring the DC portion of
the loop current is contained within the loop detector block. A
low pass filter is used in the feedback loop to block voice and
other signals from interfering with the loop current limit
function. The pole of the low pass filter is set by the external
4.7µF capacitor (CDC) and an internal 8KΩ resistor. The DC
feed characteristic of the SLIC will drive Tip and Ring
towards half battery to regulate the DC loop current. For light
loads, Tip will be near -4V and Ring will be near
VVBL + 4.5V. Most applications will operate the device from
low battery while off hook. The following diagram depicts the
DC feed characteristic.
VTR(OC)
m = (∆VTR/∆IL) = 11.1kΩ
VTR , DC (V)
(EQ. 17)
If the battery voltage is less than -49V (the MTU clamp is
off), the standby line current power contribution reduces to
Equation 18.
V RING = V BH + 4.5V
RC
-
Any standby line current, ISLC , introduces an additional power
dissipation term PSLC . Equation 17 illustrates the power
contribution is zero when the standby line current is zero.
P SLC = I SLC × ( V BH + 1 + I SLC x1200 )
-
VOUT
Standby Current Power Dissipation
P SLC = I SLC × ( V BH – 49 + 1 + I SLC x1200 )
RA
ILOOP (mA)
ILIM
FIGURE 5. DC FEED CHARACTERISTIC
The point on the y-axis labeled VTR(OC) is the open circuit
Tip to Ring voltage and is defined by the feed battery
voltage.
V TR ( OC ) = V BL – 9
(EQ. 20)
The curve of Figure 5 shows the loop current for a given set
of loop conditions. The loop conditions are determined by
the low battery voltage and the DC loop resistance. The DC
loop resistance is the sum of the protection resistance,
copper resistance (ohms/foot) and the telephone off hook
DC resistance.
FN4924.2
November 3, 2004
ISL5586
Since the current relationships are different for constant
current versus constant voltage, the region of device
operation is critical to valid power dissipation calculations.
IA
ISC
IB
ILOOP (mA)
ILIM
Reverse Active Mode
Overview
2RP
RLOOP (Ω)
RKNEE
FIGURE 6. ILOOP VERSUS RLOOP LOAD CHARACTERISTIC
The slope of the feed characteristic and the battery voltage
define the maximum loop current on the shortest possible
loop as the short circuit current ISC .
V TR ( OC ) – 2R P I LIM
I SC = I LIM + ----------------------------------------------------1.1e4
(EQ. 21)
The term ILIM is the programmed current limit, 1760/RIL. The
line segment IA represents the constant current region of the
loop current limit function.
V TR ( OC ) – R LOOP I LIM
I A = I LIM + -------------------------------------------------------------1.1e4
(EQ. 22)
The maximum loop resistance for a programmed loop
current is defined as RKNEE .
V TR ( OC )
R KNEE = ----------------------I LIM
(EQ. 23)
When RKNEE is exceeded, the device will transition from
constant current feed to constant voltage, resistive feed. The
line segment IB represents the resistive feed portion of the
load characteristic.
V TR ( OC )
I B = ----------------------R LOOP
(EQ. 24)
Power Dissipation
The power dissipated by the SLIC in the Forward Active
mode while on hook is strictly a function of the quiescent
currents for each supply.
P FAQ = V BH × I
+ V BL × I BLQ + V CC × I CCQ
BHQ
(EQ. 25)
Off hook power dissipation is increased above the quiescent
power dissipation by the DC load. If the loop length is less
than or equal to RKNEE , the device is providing constant
current (IA) , and the power dissipation is calculated using
Equation 26.
P FA ( IA ) = P FA ( Q ) + ( V BL xI A ) – ( R LOOP xI 2 A )
The reverse active mode (RA, 011) provides the same
functionality as the forward active mode. On hook transmission,
DC loop feed, and voice transmission are supported. Loop
supervision is provided by the switch hook detector. The device
may be operated from either high or low battery.
When in the Reverse Active mode the Tip and Ring DC
voltage characteristics exchange roles. That is, Ring is
typically 4V below ground and Tip is typically 4.5V more
positive than battery.
Silent Polarity Reversal
Changing from forward active to reverse active or vice versa
is referred to as polarity reversal. Many applications require
control of the polarity reversal transition time. Requirements
range from minimizing cross talk to protocol signalling.
The SLIC uses an external low voltage capacitor, CPOL , to
set the reversal time. The capacitor is isolated from the AC
loop so that loop stability is not influenced by its selection.
Once CPOL is set, the reversal time will remain nearly
constant over various load conditions.
The internal circuitry used to set the polarity reversal time is
shown in Figure 7. During Forward Active the switch is open
and the current from source I1 charges the external timing
capacitor CPOL. The internal resistor provides a clamping
function for the voltage at the POL node. When the Reverse
Active mode is initiated the switch closes and the difference
current (I2-I1) discharges the timing capacitor. The voltage at
the POL node drives one side of a transistor differential pair
which forces the Forward or Reverse condition on the Tip and
Ring amplifiers. The forward/reverse transition time is given by
Equation 28, where ∆time is the required reversal time.
∆time
C POL = ---------------75000
(EQ. 28)
Polarized capacitors may be used for CPOL. The low voltage
at the POL pin and minimal voltage excursion in the order of
±0.75V, are well suited for polarized capacitors.
(EQ. 26)
If the loop length is greater than RKNEE , the device is
operating in the constant voltage, resistive feed region. The
power dissipated in this region is calculated using Equation 27.
P FA ( IB ) = P FA ( Q ) + ( V BL xI B ) – ( R LOOP xI 2 B )
10
(EQ. 27)
FN4924.2
November 3, 2004
ISL5586
I1
V BH
V R = ----------- – ( 50 × V DIF )
2
POL
75kΩ
When the differential input signal is zero, the Tip and Ring
amplifier outputs are centered at half battery. The device
provides auto centering for easy implementation of
sinusoidal ringing waveforms. Both AC and DC control of the
Tip and Ring outputs is available during ringing. This feature
allows for DC offsets as part of the ringing waveform.
CPOL
I2
FIGURE 7. REVERSAL TIMING CONTROL
Ringing Input Terminals
Power Dissipation
The power dissipation equations for forward active operation
also apply to the reverse active mode.
Ringing
Overview
The Ringing mode (RNG, 100) provides linear amplification
to support a variety of ringing waveforms. A programmable
ring trip function provides loop supervision and auto
disconnect upon ring trip. The device is designed to operate
from the high battery during this mode.
Architecture
The SLIC provides linear amplification to the differential
signal applied to the ringing inputs (VRSP, VRSM). The
differential ringing gain of the device is 100V/V. The circuit
model for the ringing path is shown in Figure 8.
R
20
R/8
-
+
TIP
RING
20
+
-
1.25R
-
+
5:1
1.25R
+ VBH
2
R
R
+
VRSP
VRSM
-
-
+
R
FIGURE 8. LINEAR RINGING MODEL
The voltage gain from the differential ringing input to the Tip
output is 50V/V. The resistor ratios provide a gain of 10 and
the current mirror provides a gain of 5. The voltage gain from
the differential input to the Ring output is -50V/V. The
equations for the Tip and Ring outputs during ringing are
provided below.
V BH
V T = ----------+ ( 50 × V DIF )
2
(EQ. 30)
(EQ. 29)
The differential terminals feature high input impedance
which allows the use of low value capacitors for AC coupling
the ring signal if necessary. The Ringing input is enabled
only during the ringing mode, therefore a free running
oscillator may be connected at all times.
When operating from a battery of -100V, each amplifier, Tip
and Ring, will swing a maximum of 95VP-P . Hence, the
maximum differential signal swing between VRSP and VRSM
to achieve full scale ringing is approximately 1.9VP-P .
Logic Control
Ringing patterns consist of silent and ringing intervals. The
ringing to silent pattern is called the ringing cadence. During
the silent portion of ringing, the device can be programmed
to any other operating mode. The most likely candidates are
low power standby or forward active. Depending on system
requirements, the low or high battery may be selected.
Loop supervision is provided with the ring trip detector. The ring
trip detector senses the change in loop current when the phone
is taken off hook. The loop detector full-wave rectifies the
ringing current, which is then filtered with external components
RRT and CRT. The resistor RRT sets the trip threshold and the
capacitor CRT sets the trip response time. Most applications will
require a trip response time less than 150ms.
Three very distinct actions occur when the device detects a
ring trip. First, the DET output is latched low. The latching
mechanism eliminates the need for software filtering of the
detector output. The latch is cleared when the operating
mode is changed externally. Second, the Ringing inputs are
disabled, removing the ring signal from the line. Third, the
device is internally forced to the forward active mode.
Power Dissipation
The power dissipation during ringing is dictated mostly by the
load driving requirements and the ringing waveform. The key to
valid power calculations is the correct definition of average and
RMS currents. The average current defines the high battery
supply current. The RMS current defines the load current.
The cadence provides a time averaging reduction in the
peak power. The total power dissipation consists of ringing
power, Pr, and the silent interval power, Ps .
tr
ts
P RNG = P r × -------------- + P s × -------------t +t
t +t
r
11
s
r
(EQ. 31)
s
FN4924.2
November 3, 2004
ISL5586
The terms tR and tS represent the cadence. The ringing
interval is tR and the silent interval is tS . A typical cadence
ratio tR :tS is 1:2.
The quiescent power of the device in the Ringing mode is
defined in Equation 32.
P r ( Q ) = V BH × I BHQ + V BL × I BLQ + V CC × I CCQ
(EQ. 32)
The total power during the ringing interval is the sum of the
quiescent power and loading power:
2
V RMS
P r = P r ( Q ) + V BH × I AVG – ----------------------------------------Z
+R
REN
(EQ. 33)
LOOP
For sinusoidal waveforms, the average current, IAVG, is
defined in Equation 34.
V RMS × 2
2
I AVG =  --- ----------------------------------------- π Z
+R
REN
(EQ. 34)
LOOP
The silent interval power dissipation will be determined by
the quiescent power of the selected operating mode.
Forward Loop Back Mode
Overview
The Forward Loop Back mode (FLB, 101) provides test
capability for the SLIC. An internal signal path is enabled
allowing for both DC and AC verification by the connection of
an internal 600 ohm resistor across Tip and Ring. This
internal terminating resistor has a tolerance of ±10% at room
temperature. The device is intended to operate from only the
low battery during this mode.
Architecture
When the forward loop back mode is initiated internal
switches connect a 600Ω load across the outputs of the Tip
and Ring amplifiers as shown below.
TIP
TIP AMP
600Ω
RING AMP
RING
AC Verification
The entire AC loop of the device is active during the forward
loop back mode. Therefore a 4-wire to 4-wire level test
capability is provided. Depending on the transhybrid balance
implementation, test coverage is provided by a one or two
step process.
System architectures which cannot disable the transhybrid
function would require a two step process. The first step
would be to send a test tone to the device while on hook and
not in forward loop back mode. The return signal amplitude
would be the test signal amplitude times the gain of the
transhybrid amplifier. Since the device would not be
terminated in the on hook mode, cancellation would not
occur. The second step would be to program the device to
FLB mode and resend the test tone. The return signal would
be much lower in amplitude than the first step, indicating the
device was active and the internal termination attenuated the
return signal.
System architectures which can disable the transhybrid
function would achieve test coverage with a signal step.
Once the transhybrid function is disabled the SLIC can be
programmed to the FLB mode and the test tone can be sent.
The return signal level is determined by the 4-wire to 4-wire
gain of the SLIC times the amplitude of the signal sent.
Tip Open/Ground Start Mode
Overview
The Tip Open mode (TO, 110) is intended for compatibility
with PBX type interfaces. The device does not provide
transmission capability in this mode which is intended for idle
line conditions. Loop supervision is provided by the switch
hook detector and either high or low battery operation is
supported.
Functionality
During Tip Open operation, the Tip switch is disabled and
the Ring switch is enabled. The minimum Tip impedance is
30kΩ. The only active path through the device will be
through the Ring switch.
In keeping with the MTU characteristics of the device, Ring
will not exceed -56V when operating from the high battery.
Though MTU does not apply to Tip Open, safety
requirements are satisfied.
FIGURE 9. FORWARD LOOP BACK INTERNAL TERMINATION
DC Verification
When the internal signal path is provided, DC current will
flow from Tip to Ring. The DC current will force DET low,
indicating the presence of loop current. In addition to
verifying device functionality, toggling the logic output
verifies the interface to the system controller.
12
FN4924.2
November 3, 2004
ISL5586
Power Denial
from the low battery if MTU compliance is not required,
further reducing standby power dissipation.
Overview
The power denial mode (111) will shutdown the entire device
except for the logic interface. Loop supervision is not
provided. This mode may be used as a sleep mode or to
shut down the SLIC in the presence of fault conditions.
Switching between high and low battery will have no effect
during power denial.
Functionality
During power denial, both the Tip and Ring amplifiers are
disabled, presenting high impedances to the line. The
voltages at both outputs are near ground.
Thermal Shutdown
In the event the safe die temperature is exceeded due to a fault
condition the device will automatically shut down. The thermal
shutdown threshold is approximately 170ºC.When the device
cools to a temperature below the thermal threshold it will power
back up automatically. If the fault persists the part will continue
to go in and out of thermal shutdown which can be observed as
an oscillation on Tip or Ring. Programming power denial will
shut down the device and stop the self cooling cycle.
High Battery Operation
Other than ringing, the high battery should be used for
standby conditions which must provide MTU compliance.
During standby operation the power consumption is typically
85mW with -100V battery. If ringing requirements do not
require full 100V operation, then a lower battery will result in
lower standby power.
High Voltage Decoupling
The 100V rating of the SLIC dictates a capacitor of higher
voltage rating be used for decoupling. Suggested decoupling
values for all device pins are 0.1µF. If the protection scheme
shown in Figure 15 is implemented the VBH decoupling
capacitor should be increased to 0.47uF. This is done to
minimize the turn-on time of the battrax device during
negative surge transients. Standard surface mount ceramic
capacitors are rated at 100V. For applications driven by low
cost and small size, the decoupling scheme shown in Figure
10 could be implemented.
0.22µ
0.22µ
Battery Switching
Overview
The integrated battery switch selects between high battery
and low battery operation. The battery switch is controlled with
the logic input BSEL. When BSEL is a logic high, the high
battery (VBH) is selected. A logic low will enable the low
battery (VBL). All operating modes of the SLIC will function
from high or low battery, but it is strongly recommended
Forward Loop Back be enabled only with the low battery.
Functionality
The logic control is independent of the operating mode
decode. Independent logic control provides the most
flexibility and will support all application configurations.
When changing device operating states, battery switching
should occur simultaneously with or prior to changing the
operating mode. In most cases, this will minimize overall
power dissipation and prevent glitches on the DET output.
All off hook operating conditions should use the low battery
to minimize power dissipation. A typical low battery
operating voltage for the SLIC is -24V, however this may be
increased to support longer loop lengths or high loop
current requirements. Standby conditions may also operate
13
FIGURE 10. ALTERNATE DECOUPLING SCHEME
It is important to place an external diode between the VBH pin
and the decoupling capacitor. Connecting the decoupling
capacitor directly to the VBH pin will degrade the reliability of the
device. Refer to Figure 15 for the proper arrangement. This
applies to both single and stacked and decoupling schemes.
If VBL and VBH are tied together the battery switch function
is overridden. In this case the external diode is not needed
and the decoupling capacitor may be attached directly to
VBH pin.
R
TIP
V2W
+
-
IL
VTR
RING
20
-
RF
+
20
1:1
+
-
VZO
TA
-
Low Battery Operation
VBH
ISL5586
+
The only external component required to support the battery
switch is a diode in series with the VBH supply lead. In the
event that high battery is removed, the diode allows the
device to transition to low battery operation.
VBL
R
4R
3R
-IN
4R
4R
4R
8K
-
+
RS
VSA
CFB
VFB
3R
FIGURE 11. IMPEDANCE SYNTHESIS
FN4924.2
November 3, 2004
ISL5586
Impedance and Gain Derivations
The feedback mechanism for monitoring the AC portion of
the loop current consists of two amplifiers, the sense
amplifier (SA) and the transmit amplifier (TA). The AC
feedback signal is used for impedance synthesis. A detailed
model of the AC feed back loop is provided below
Impedance Programming Resistor Derivation
The gain of the transmit amplifier, set by RS , determines the
programmed resistance of the SLIC. For complex line
terminations RS is replaced with a complex network ZS
(Figure 1). The capacitor CFB blocks the DC component of
the loop current. Figure 11 illustrates the impedance
synthesis loop. Note that the ground symbols shown in
Figures 11 through 14 represent AC grounds, not
necessarily actual DC potentials.
The receiver block provides a single-ended to differential
conversion with a voltage gain of 2. The voltage at Tip and
Ring due to the feedback from VZO is shown in Equation 35.
(EQ. 35)
VTR = – 2 × V ZO
The Feedback amplifier (TA) provides the programmable
gain required for impedance synthesis to the Receiver block.
The output voltage (VZO) is a function of the Sense Amplifier
output voltage and the gain of the feedback amplifier, which
can be substituted for VZO .
RS
VTR = – 2 × V SA ×  ------------
 8KΩ
(EQ. 36)
The sense amplifier shown in Figure 11 is configured as a 4
input differential amplifier with a gain of 3/4. The output
voltage, VSA , is a function of the voltage across the Tip and
Ring sense resistors (20Ω each) which can also be
expressed in terms of loop current.
V SA = – 2 × 20 × IL × ( 3 ⁄ 4 )
(EQ. 37)
Substituting Equation 37 into Equation 35 and rearranging
terms yields Z0 , the SLIC’s synthesized 2-wire impedance.
Rearranging and solving for RS , Equation 39 shows the
relationship between the impedance programming resistor
and the programmed impedance.
Rs
Rs
V TR
3
- = 4 × 20 × IL × --- × ------------ = 60 × -----------Z 0 = ---------8KΩ
4 8KΩ
IL
(EQ. 38)
R S = 133.3 × Z0
(EQ. 39)
4-WIRE TO 2-WIRE GAIN
The 4-wire to 2-wire gain is defined as the gain from the
differential receive input to the 2-wire load ZL. The gain is a
function of the terminating impedance, synthesized
impedance and protection resistors and is illustrated in
Figure 12. The input current to the receiver block Irx4w
comes from the difference of the VRX input current and the
14
VZO feedback current. This current is fed to the Tip and Ring
amplifiers and yields the relationship shown in Equation 40.
V TR = – 2 × ( V rx – V ZO )
(EQ. 40)
The voltage VZO, is a function of the sense amplifier output
voltage VSA.
RS
V Z0 = – V SA × -----------8KΩ
(EQ. 41)
VSA can be expressed in terms of loop current as shown in
Equation 42.
3
V SA = – IL × 2 × 20 × --4
(EQ. 42)
Substituting Equation 42 into Equation 41 gives Equation 43.
3 RS
V Z0 = – IL × 2 × 20 × --- × -----------4 8KΩ
(EQ. 43)
The VZ0 term in Equation 40 can now be replaced by
Equation 43 yielding Equation 44.
RS
3
V TR = – 2 × V rx – 2  IL × 2 × 20 × --- ×  ------------



8KΩ
4
(EQ. 44)
A loop equation can be derived for the 2-wire side that
replaces VTR as shown in the equation below.
RS
3
V 2W + IL × 2R p = – 2V rx – IL  4 × 20 × --- ×  ------------

4  8KΩ
(EQ. 45)
Expressing IL in terms of V2W/ZL, rearranging, and solving
for V2W yields the relationship between the 2-wire voltage
and the output of the Receive amplifier.
ZL


V 2W = – 2V rx ×  --------------------------------------
 Z L + Z 0 + 2R P
(EQ. 46)
The differential voice input is configured for a gain of 1.4.
The relationship between VRX and the voice input is shown
in Equation 47. Substituting for VRX , the 4-2-Wire gain is
shown in Equation 48. Note that the differential voice input is
outside the impedance synthesis loop, so the gain of the
receive amplifier has no effect on the SLIC’s impedance.
V rx = 1.4 × ( V RXP – V RXM ) = 1.4 × V RX4W
ZL
V 2W


------------------- = – 2.8  ------------------------------------------
V RX4W
 Z O + 2R P + Z L
(EQ. 47)
(EQ. 48)
When the combination of the device source impedance and
the protection resistors equal the terminating impedance, the
receive gain equals 2.92dB and is inverted with respect to
the 4-wire input.
2-WIRE TO 4-WIRE GAIN
The 2-wire to 4-wire gain (G24) is defined as the gain from the
Tip and Ring terminals (VTR) to the VTX differential output.
FN4924.2
November 3, 2004
ISL5586
Irx4w
200K
ZL
RP
TIP
IL
Vtr
20
200K
+
1.4R
Iz0
1:1
1.4R
-
V2W
RP
+
+
VRX
200K
VZO
20
+
-
RING
R
TA
-
+
3R
4R
-IN
+
-
200K
R
VRXM
VRXP
RS
4R
8K
-
4R
+
4R
3R
VSA
CFB
VRX4W
VFB
FIGURE 12. SCHEMATIC FOR 4-WIRE TO 2-WIRE GAIN DERIVATION
Note that in Figure 13, VTR is referenced on the line side of the
protection resistors.
On the 2-wire side, solving for IL in terms of VIN gives
Equation 49. Equations 50 and 51 show the relationship of
VIN to the outputs of the Sense Amplifier (VSA) and the
Feedback Amplifier (VZ0) respectively.
V IN


IL =  --------------------------------------
Z
+
Z
+
2R
 L
P
0
(EQ. 49)
V IN


3
V SA = –  -------------------------------------- × 2 × 20 ×  ---
 4
 Z L + Z 0 + 2R P
V IN
RS


3
V Z0 = –  -------------------------------------- × 2 × 20 ×  --- × -----------

Z
+
Z
+
2R
8KΩ
4
 L
P
0
(EQ. 50)
(EQ. 51)
Simplifying Equation 51 in terms of Z0 gives the following
equation.
V IN

 Z0
V Z0 = –  -------------------------------------- × ----- Z L + Z 0 + 2R P 2
(EQ. 52)
The resulting differential output voltage VTX4W, is shown in
Equation 53.
V TX4W = V TXP – V TXM = V Z0 – ( – V ) = 2V Z0
Z0
(EQ. 53)
Note that the gain from VZ0 to the differential output is outside
the impedance synthesis loop and will have no effect on the
SLIC’s programmed impedance.
Substituting Equation 53 into Equation 52 and rearranging
terms gives the gain from the 2-wire source (VIN) to the
differential output of the Transmit Amplifier.
Z0
V TX4W


-------------------- = –  -------------------------------------
V IN
 Z L + Z 0 + 2R P
(EQ. 54)
15
If the combination of the protection resistors and the
programmed impedance of the SLIC are equal to ZL the
voltage VTR will be 1/2 VIN. The 2-wire to 4-wire gain is
defined by Equation 55.
2Z 0
V TX4W


------------------- = –  -------------------------------------
V TR
 Z L + Z 0 + 2R P
(EQ. 55)
4-WIRE TO 4-WIRE GAIN
The 4-Wire to 4-Wire gain is defined in Equation 56 and is
illustrated in Figure 14.The first term is identical to
Equation 48.
V TX4W
V 2W
V TX4W
------------------- = -------------------- × -------------------V RX4W
V 2W
V RX4W
(EQ. 56)
The second term is derived in a similar manner as the 2-wire
to 4-wire gain starting with Equation 57.
V 2W = IL × ZL
(EQ. 57)
Moving around the loop from the 2-wire side to the 4-wire
output we solve for VSA and VZO .
3 V 2W
3
V SA = – I L × 2 × 20 × --- = ------------ × 40 × --ZL
4
4
(EQ. 58)
RS
V 2W
V 2W Z 0
3
V Z0 = ------------ ×  ------------ × 40 × --- = ------------ × ----- 8KΩ
ZL
ZL
2
4
(EQ. 59)
The relationship between VZ0 and the 4-wire output is
shown in Equation 53. Substituting Equation 59 into
Equation 53 yields Equation 60, the second term in Equation
56.
Z
V TX4W
------------------- = ------0
V 2W
ZL
(EQ. 60)
FN4924.2
November 3, 2004
ISL5586
Equations 48 and 60 can be combined to re-write the 4-wire
to 4-wire gain equation.
ZL
V TX4W

 Z0
------------------- = – 2.8  ------------------------------------------ × -----Z
+
2R
+
Z
V RX4W
 O
P
L Z L
Simplifying the above yields the 4-wire to 4-wire gain.
Z0
V TX4W


------------------- = – 2.8  ------------------------------------------
Z
+
2R
+
Z
V RX4W
 O
P
L
(EQ. 61)
(EQ. 62)
1.4R
IL
VIN
+
-
ZL
RP1
V
TR
20
20
-
200K
VRXP
VRXM
R
1.4R
1:1
VZO
+
-
TA
-
+
RP2
-
+
VRX
+
TIP
RING
R
200K
200K
200K 4R
3R
-IN
4R
4R
4R
3R
VTX4W
R
-
-
VFB
VSA
+
R
CFB
8K
-
+
VTXP
RS
+
VTXM
FIGURE 13. SCHEMATIC FOR 2-WIRE TO 4-WIRE GAIN DERIVATION
1.4R
200K
RP1
+
V2W ZL
20
IL
20
R
-
+
-
+
3R
4R
8K
-
+
R
VRXM
+ VRX4W
-
VTXP
RS
-IN
4R
4R
VRXP
VZO
TA
200K 4R
R
+
1.4R
200K
1:1
-
RP2
-
VRX
+
T
-
200K
VSA
CFB
VFB
R
R
-
VTX4W
+
+
3R
VTXM
FIGURE 14. SCHEMATIC FOR 4-WIRE TO 4-WIRE GAIN DERIVATION
16
FN4924.2
November 3, 2004
ISL5586
Pin Descriptions
PLCC
SYMBOL
DESCRIPTION
1
TIP
2
BGND
3
VBL
Low Battery Supply Connection.
4
VBH
High Battery Supply Connection.
5
BSEL
6
F2
TTL Mode Control Input - MSB.
7
F1
TTL Mode Control Input.
8
F0
TTL Mode Control Input - LSB.
9
DET
Detector Output - This TTL output provides on-hook/off-hook status of the loop based upon the selected operating mode.
The detected output will either be switch hook or ring trip.
10
VRSP
Non-Inverting Ringing Signal Input - Analog input for driving 2-wire interface while in Ring Mode.
11
VRSM
Inverting Ringing Signal Input - Analog input for driving 2-wire interface while in Ring Mode.
12
VTXP
Transmit Output Voltage - AC couples to CODEC.
13
VTXM
Transmit Output Voltage - AC couples to CODEC.
14
AGND
Analog Ground Reference. This pin should be externally connected to BGND.
15
POL
An External Capacitor on this pin sets the polarity reversal time.
16
VRXP
Non-Inverting Analog Receive Voltage - 4-wire analog audio input voltage.
17
VRXM
Inverting Analog Receive Voltage - 4-wire analog audio input voltage.
18
VZO
Connection Terminal for impedance matching programming resistor
19
-IN
Connection Terminal for high pass filter capacitor and impedance matching components.
20
VFB
Connection Terminal for high pass filter capacitor and impedance matching components.
21
TL
22
VCC
23
CDCP
DC Biasing Filter Capacitor - Positive Terminal.
24
CDCM
DC Biasing Filter Capacitor - Negative Terminal.
25
RTD
Ring Trip Filter Network Connection Terminal.
26
ILIM
Loop Current Limit programming resistor connection terminal.
27
RD
Switch Hook Detection threshold programming resistor connection terminal.
28
RING
TIP Power Amplifier Output.
Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground.
Internally separate from AGND and SGND but should be connected to the same potential as AGND & SGND.
Selects between high and low battery, with a logic “1” selecting the high battery and logic “0” the low battery.
Transient Current Limit Programming Resistor Connection Terminal.
Positive Voltage Power Supply, +5V +/-5%.
RING Power Amplifier Output.
17
FN4924.2
November 3, 2004
Basic Application Circuit
CPS1
CPS2
D1
F1250T
BCM3352
VRXP
2
RP2
CRT
2
RRT
B1100CC
3
VRX0(-)
VTX0(+)
VRSM
VTXP
RTD
VZO
ISL5586
RIL
ILIM
CDCM
CDC
CDCP
POL
CP
20K
RS
-IN
CFB
CX1
CT1
100K
TL
RINGING_OUT(-)
100K
RP
20K
VFB
CT2
BSEL
CX3
F0
F1
AGND
DET
RINGING_OUT(+)
CX2
F2
RTL
CMLEVEL
0.068µF
0.068µF
BGND
FN4924.2
November 3, 2004
NOTE: CPS1 should be located as close as possible to the
B1100CC to minimize turn-on time. Less than 2 inches is
recommended.
FIGURE 15. SINGLE CHANNEL INTERFACE BETWEEN ISL5586 AND BCM3352
ISL5586
CSH
VTX0(-)
CR3
VTXM
RD
CPOL
CR2
VRSP
RING
RSH
1
VRX0(+)
VRXM
SLIC_CTRL4
B1100CC
F1250T
CR1
VCC
SLIC_CTRL3
VBL
SLIC_CTRL2
3
VBH
TIP
SLIC_CTRL1
RP1
SLIC_CTRL0
18
CPS3
1
ISL5586
TABLE 2. BASIC APPLICATION CIRCUIT COMPONENT LIST
VALUE
TOLERANCE
RATING
U1 - Ringing SLIC
COMPONENT
ISL5586
N/A
N/A
RTL
17.8kΩ
1%
0.1W
RRT
22.1kΩ
1%
0.1W
RSH
40kΩ
1%
0.1W
RIL
71.5kΩ
1%
0.1W
RS
66.5kΩ
1%
0.1W
0Ω
1%
0.1W
Not Populated
20%
10V
0.47µF
20%
10V
RP1,RP2
CP
CRT, CPOL , CSH
CFB
1.0µF
20%
10V
CDC
4.7µF
20%
10V
CPS1
0.47µF
20%
>100V
CPS2 , CPS3
0.1µF
20%
100V
CT1, CT2
4.7µF
CR1, CR2, CR3
3300pF
CX1, CX2, CX3
150pF
1N400X Type with Breakdown > 100V.
D1
D2,D3
1N4935 Type
RP1 , RP2
Protection resistor values are application dependent and will be determined by protection
requirements. Standard applications will use ≥ 49Ω per side.
Design Parameters: Ring Trip Threshold = 81mAPEAK , Switch Hook Threshold = 15mA, Loop Current Limit = 24.6mA, Synthesize Device
Impedance = (3*66.5kΩ)/400 = 498.8Ω, protection resistors = 50Ω, impedance across Tip and Ring terminals = 599Ω. Transient current
limit = 100mA.
Interface Diagram
The figure 15 above shows the electrical interface between
the ISL5586 and the BCM3352. Only a single channel is
shown to simplify the diagram. This diagram only shows
electrical interfaces and pertinent external components
Receive Interface
The receive interface of the BCM3352 is directly coupled to
the ISL5586 differential receive input. External filter
capacitors are provided to minimize noise from the
BCM3352. The ISL5586 is designed with a 4-wire to 2-wire
gain of +2.98dB.
single ringing generator as supplied by the BCM3352 drives
all four sets of ringing inputs in the Broadcom reference
design. The ISL5586 is designed with a differential ringing
gain of 100V/V.
Passive Component Values
The passive component values in the Broadcom reference
design may not be reflected by this document. Please refer
to the Broadcom reference design documentation for the
most recent schematic and COM information.
Transmit Interface
The differential transmit output of the ISL5586 is AC coupled
to an external passive network. The external passive
network accomplishes many tasks. First, it filters the noise
which may exist on the CMLEVEL output of the BCM3352.
Second, it biases the ground referenced output signals of
the ISL5586 to the CMLEVEL of the BCM3352. Lastly, the
external network attenuates the signal levels coming from
the ISL5586. The ISL5586 is designed with a 2-wire to 4wire gain of 0dB and a 4-wire to 4-wire gain of +2.98dB.
Ringing Interface
The ISL5586 only passes the ringing signal on VRSP, VRSM
to Tip and ring only during the ringing mode. Therefore, a
19
FN4924.2
November 3, 2004
ISL5586
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
0.048 (1.22)
PIN (1) IDENTIFIER
0.042 (1.07)
0.056 (1.42)
0.004 (0.10)
C
0.025 (0.64)
R
0.045 (1.14)
0.050 (1.27) TP
C
L
N28.45 (JEDEC MS-018AB ISSUE A)
28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
INCHES
SYMBOL
D2/E2
E1 E
C
L
D2/E2
VIEW “A”
0.020 (0.51)
MIN
A1
A
D1
D
MIN
MAX
MILLIMETERS
MIN
MAX
NOTES
A
0.165
0.180
4.20
4.57
-
A1
0.090
0.120
2.29
3.04
-
D
0.485
0.495
12.32
12.57
-
D1
0.450
0.456
11.43
11.58
3
D2
0.191
0.219
4.86
5.56
4, 5
E
0.485
0.495
12.32
12.57
-
E1
0.450
0.456
11.43
11.58
3
E2
0.191
0.219
4.86
5.56
4, 5
N
28
28
SEATING
-C- PLANE
0.020 (0.51) MAX
3 PLCS
0.026 (0.66)
0.032 (0.81)
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
0.045 (1.14)
MIN
6
Rev. 2 11/97
VIEW “A” TYP.
NOTES:
1. Controlling dimension: INCH. Converted millimeter dimensions are
not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.
4. To be measured at seating plane -C- contact point.
5. Centerline to be determined where center leads exit plastic body.
6. “N” is the number of terminal positions.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
20
FN4924.2
November 3, 2004
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