an9918

ISL5586EVAL Evaluation Board User’s Guide
TM
Data Sheet
March 2001
AN9918
Introduction
Getting Started
The ISL5586 evaluation
board provides a complete
evaluation system for the
ISL5586 family of ringing
SLICs. The receive and
transmit ports of the ISL5586 are designed with differential
interfaces. This implementation provides noise immunity and
signal level compatibility with 3.3V CODECs. The ringing
interface of the ISL5586 is DC coupled and has been
implemented differentially. The interface allows both AC and
DC control of the balanced waveform.
Your evaluation kit should contain this user’s guide and the
following hardware.
The evaluation board comes complete with a differential input
driver. The differential input driver can be used to drive both
the receive inputs of the ISL5586 or provide a differential
ringing signal to ring the phone using a single ended input
source. Also included on the evaluation board is a differential
receive circuit to monitor the SLIC’s differential transmit signal.
Applying Power to the Evaluation Board
1. One ISL5586 evaluation board.
2. At least one ISL5586 device sample, already in board.
3. One PLCC extraction tool.
4. One power cable assembly with multi colored conductors.
5. Four jumpers.
The evaluation board should have the same appearance as
the silk screen shown in Figure 1.
Here are a few safeguards with power sequencing until you
are accustomed to using the high voltages required by the
devices.
1. Limit the current on all power supplies to 100mA.
2. Turn on the power supplies after the power cables are
attached to the evaluation boards.
Voltage ratings for external components have been selected
based on 100V device operation, therefore compatibility to
lower voltage versions is guaranteed.
1
6
TM
DUT
POWER
5
10
R5
GND V
CC
C3
VBH
C2
R2 C8
R13 R14 R15
D3
TP6
J1 FUSE1
2 WIRE
PROTECTION
D1
B1
ILIM
RD_
TIP
RING
VEL
VEH
BSEL
B2
RING
J2
FUSE2
TP7
RPR
D4
GND2
MODE
+
F2
F1
F0
LPS
1
0
0
0
PA
0
0
0
1
RA
0
0
1
1
RING
1
0
0
0
LP BCK
0
1
0
1
TIP OPEN
0
1
1
0
PWR DOWN
1
1
1
1
1
S1
GND
C14
VZO
VRXM
VRXF
POL
VTXP
VTXM
CRXM
CRXP
CPOL
S4
C7
L
F2
F1
NON-INV J6
TP9
JP4 VRSP
VRSM
JP2
J4
DIFF. RECEIVE
H
BSEL
R3
F0
R12
INPUT LOGIC
VRSP
VRSM
CVTXM
R7
S3
GND3
VRXM
CVTXP
U2
DET
ON
S2
U5 C5
VRXP
VRXP
VRXM
JP1
TP6 J3
INV.
R1
TRUTH TABLE
BS
EL
C9
CP
CPE
RLIM
RPT
C13
J5
JP3
U4
CRD
RTL
CDC
RTD_
CDCM
CDCP
VCC
TL
VRB
IN
TIP
RD
C4
U3
C10
GND 1
DIFF
DRV
-15V
C2
TL, ILIM, RD, RTD
IMPED
PROGRAMMING CKTS MATCH
RTD CRTD
RS RP
3V LOGIC
RJ11
VVLE
F2
F1
F0
DET_
VRSP
VRSM
ISL5586 EVAL REV B
S/N
CALL 1-800-INTERSIL
DIFF. DRIVER
R6
J6
TP11
JP6
R6
VTXP
VTXM
R10
JP5
R9
TP10
R11
J7
VTXM
C16
C15 GND5
GND
EXT. CONTROL
VTXP
SPARE JUMPERS
DIFF
REC
FIGURE 1. EVALUATION BOARD SILK SCREEN
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, All Rights Reserved
Application Note 9918
Evaluation Board Functional Description
DUT
POWER
TM
DIFF DRIVER
DIFF
DRV
3V LOGIC
TL, ILIM,
RD, RTD,
PROG CKTS
RJ11
IMPED
MATCH
JP3
VRXP
JP1
VRXM
JP4
VRSP
JP2
VRSM
DIFF RCV JP6
VTXP
JP5
VTXM
TIP
ISL5586
2W
PROTECTION
RING
INPUT LOGIC
TRUTH TABLE
S1 S2 S3 S4
BSEL F2 F1 F0
DIFF
RCV
FIGURE 2. EVALUATION BOARD FUNCTIONAL DIAGRAM
Evaluation Board Jumper Definitions
JUMPER
DESCRIPTION
JP1
Connects the output of the differential driver to the VRXM pin of the ISL5586 for 4 wire to 2 wire communication.
JP2
Connects the output of the differential driver to the VRSM pin of the ISL5586 to ring the phone.
JP3
Connects the output of the differential driver to the VRXP pin of the ISL5586 for 4 wire to 2 wire communication.
JP4
Connects the output of the differential driver to the VRSP pin of the ISL5586 to ring the phone.
JP5
Connects the input of the differential receiver to the VTXM pin of the ISL5586 for 2 wire to 4 wire communication.
JP6
Connects the output of the differential driver to the VTXP pin of the ISL5586 for 2 wire to 4 wire communication.
Test Points
TABLE 1. ISL5586 OPERATING MODES
Each connector interface to the evaluation board has a test
point (reference Table 5 for test point descriptions). All test
points are DC coupled and should be guarded against
ground shorts. High impedance test inputs, such as
oscilloscopes or DVMs, should be used to monitor these
points. Unused BNC connections also provide convenient
test point access.
Toggle Switches
OPERATING MODE
F2
F1
F0
Low Power Standby
0
0
0
Forward Active
0
0
1
Unused
0
1
0
Reverse Active
0
1
1
Ringing
1
0
0
Forward Loop Back (Note)
1
0
1
Tip Open
1
1
0
Power Denial
1
1
1
The four toggle switches, S1 thru S4, interface directly to the
ISL5586 device. Positioning any switch towards the top of
the board is a logic “1”. Positioning any switch towards the
bottom of the board is a logic “0”. All switches are labeled
with the control signal name of the ISL5586 device.
NOTE: The ISL5586 device should always operate from low battery
voltage when using the Forward Loop Back mode.
The battery select signal BSEL, selects the high battery
when set to logic high. The operating modes for the ISL5586
device are provided in Table 1.
Refer to the device electrical data sheet for detailed
descriptions regarding each operating mode according to
the device under evaluation.
2
Application Note 9918
Basic Operation Configuration
DUT
POWER
TM
DIFF DRIVER
DIFF
DRV
3V LOGIC
TL, ILIM,
RD, RTD,
PROG CKTS
RJ11
IMPED
MATCH
Jumper
Jumper
TIP
ISL5586
2W
PROTECTION
RING
DIFF RCV
Jumper
INPUT LOGIC
TRUTH TABLE
S1 S2 S3 S4
Jumper
JP3
VRXP
JP1
VRXM
JP4
VRSP
JP2
VRSM
JP6
VTXP
JP5
VTXM
BSEL F2 F1 F0
DIFF
RCV
FIGURE 3. BASIC OPERATION CONNECTION AND JUMPERS
Description
Measurement Capability
The ISL5586 Evaluation Board is equipped to handle
differential input signals from a CODEC in both the receive
and transmit directions. The board is also equipped to
enable a differential ringing signal to drive the phones
through the ISL5586. This is accomplished by removing all
jumpers from the board and applying the input signals using
the banana jacks located on the right side of the board. The
following section will discuss setting up the evaluation board
for the basic operation. Setting up the evaluation board to
ring the phone will be the topic of the next section.
Nearly all AC and DC parameters of the device can be
measured using this configuration. The device has been
socketed to allow easy measurements of more than a single
device. An extraction tool has been included with the
evaluation kit and should be used to remove the device from
the socket. The typical device measurements are listed below.
The ISL5586 Evaluation Board is equipped with a differential
driver to enable the user to drive the ISL5586 with standard
lab equipment. Figure 3 shows the connection of the
jumpers to enable basic operation of the ISL5586 using
standard single ended lab equipment.
Power Supply Connections
Power should be applied to the evaluation board using the
primary power cable located at the top of the board. Prior to
applying power, the voltage setting of each supply should be
verified. The power supplies should be turned off while
mating the primary power cable to the evaluation board.
Jumper Settings
Reference Figure 3 for the placement of the jumpers to
enable basic operation of the ISL5586.
3
1. Power supply current per operation mode.
2. Tip and Ring DC voltages per operation mod.
3. On hook AC gains G42 , G24 and G44 .
4. Off hook AC gains G42 , G24 and G44 .
5. Other AC parameters such as longitudinal balance.
DET LED
DET should light when: A DC current path exists from Tip to
Ring (switch hook); Ring Trip has occurred during ringing or,
during forward loop back testing.
Socket Removal
The surface mount socket for the ISL5586 device has the
same solder foot print as the PLCC package. Therefore, the
socket may be removed for more extensive characterization.
Application Note 9918
Basic Operation Configuration Typical Measurements
TABLE 2. SUPPLY CURRENTS (MILLI AMPS) - ON HOOK (VBL = -24V, VBH =-100V)
OPERATING MODE
F2, F1, F0
BSEL
ICC (Note)
IBH
IBL
Low Power Standby
0, 0, 0
1
23.2
0.65
0
Forward Active
0, 0, 1
0
25
0
2.5
Unused
0, 1, 0
N/A
N/A
N/A
N/A
Reverse Active
0, 1, 1
0
25
0
2.5
Ringing
1, 0, 0
1
27.4
2.2
1.5
Forward Loop Back
1, 0, 1
0
30.3
0
23
Tip Open
1, 1, 0
1
23.4
0.6
0.1
Power Denial
1, 1, 1
x
23.4
0
0.22
NOTE: The current ICC includes the current flowing through the DET LED biasing network (20ma).
TABLE 3. TIP AND RING VOLTAGES (VOLTS) - ON HOOK
OPERATING MODE
F2, F1, F0
BSEL
TIP
RING
Low Power Standby
0, 0, 0
1
-0.75
-52
Forward Active
0, 0, 1
0
-4.0
-19
Unused
0, 1, 0
N/A
N/A
N/A
Reverse Active
0, 1, 1
0
-19
-4
Ringing
1, 0, 0
1
VBH /2
VBH/2
Forward Loop Back
1, 0, 1
0
-4
-19
Tip Open
1, 1, 0
1
Float
-52
Power Denial
1, 1, 1
x
Float
Float
TABLE 4. AC GAINS (dB), OFF HOOK, 600Ω TERMINATION - FORWARD AND REVERSE ACTIVE ONLY
OPERATING MODE
F2, F1, F0
BSEL
G42
G24
G44
Forward Active
0, 0, 1
0
2.92
-1.58
1.33
Reverse Active
0, 1, 1
0
2.92
-1.58
1.33
G42
G24
AC Gain Equations
ZL


G 42 = – 2.82  ---------------------------------------
 Z O + 2R P + Z L
4
ZO


G 24 = – 2  ---------------------------------------
 Z O + 2R P + Z L
G44
ZO


G 44 = – 2.82  ---------------------------------------
 Z O + 2R P + Z L
Application Note 9918
Ringing Configuration
DUT
POWER
TM
DIFF DRIVER
DIFF
DRV
3V LOGIC
TL, ILIM,
RD, RTD,
PROG CKTS
RJ11
TIP
IMPED
MATCH
JUMPER
ISL5586
2W
PROTECTION
RING
JP3
VRXP
JP1
VRXM
JP4
VRSP
JP2
VRSM
JP6
VTXP
JP5
VTXM
JUMPER
DIFF RCV
INPUT LOGIC
TRUTH TABLE
S1 S2 S3 S4
BSEL F2 F1 F0
DIFF
RCV
FIGURE 4. RINGING CONNECTION AND JUMPERS
Description
The evaluation board is equipped to enable a differential
ringing signal using the VRSP and VRSM inputs located on
the right side of the board. If a differential ringing source is
not available, ringing the phone with standard lab equipment
is achieved by using the differential drive circuit. Figure 4
shows the connection of the jumpers to ring the phone with a
standard signal generator. The input impedance of the Driver
circuit is 50Ω and the gain is set to 0.5V/V such that a
1VRMS single ended input will produce a 1VRMS differential
output.
The ISL5586 provides linear amplification to the differential
signal applied to the ringing inputs VRSP and VRSM. The
differential ringing gain of the device is 100V/V.
The voltage gain from the differential ringing input to the Tip
output is 50V/V. The voltage gain from the differential ringing
input to the Ring output is also 50V/V. The equations for the
Tip and Ring outputs during ringing are given in EQ. 1 and
EQ. 2.
V BH
V T = ----------- + ( 50 × V DIF )
2
(EQ. 1)
V BH
V R = ----------- – ( 50 × V DIF )
2
(EQ. 2)
Power Supply Connections
Power should be applied to the evaluation board using the
primary power cable located at the top of the board. Prior to
applying power, the voltage setting of each supply should be
verified. The power supplies should be turned off while
mating the primary power cable to the evaluation board.
Jumper Settings
Reference Figure 4 for the placement of the jumpers to
enable ringing of the phone.
When the differential input signal is zero, the Tip and Ring
amplifier outputs are centered at half battery. The device
provides auto centering for easy implementation of
sinusoidal ringing. Both AC and DC control of the Tip and
Ring outputs are available during ringing. This feature allows
for DC offsets as part of the ringing waveform.
Ringing Input Terminals
Overview of Ringing
The Ringing mode (F2 = 1, F1 = 0, F0 = 0) provides linear
amplification to support a variety of ringing waveforms. A
programmable ring trip function provides loop supervision
and auto disconnect upon ring trip. The device is designed to
operate from the high battery during this mode.
5
The Ringing input is enabled only during the ringing mode,
therefore, a free running oscillator may be connected at all
times.
When operating from a battery of -100V, each amplifier, Tip
and Ring, will swing a maximum of 95Vp-p. Hence the
maximum differential signal swing between VRSP and
VRSM to achieve full scale ringing is approximately 1.9Vp-p
Application Note 9918
The following VRS input voltages are recommended for
maximum ringing capability at the given battery voltage.
TIP
VBH = -100V, VRS = 0.672VRMS .
TIP AMP
VBH = -85V, VRS = 0.565VRMS.
600Ω
VBH = -75V, VRS = 0.495VRMS .
Forward Loop Back Configuration
RING
Description
RING AMP
The Forward Loop Back mode (F2 = 1, F1 = 0, F0 = 1)
provides test capability for the SLIC. An internal signal path
is enabled allowing for both DC and AC verification by the
connection of an internal 600Ω resistor across Tip and Ring.
This internal terminating resistor has a tolerance of ±10% at
room temperature. The device is intended to operate from
only the low battery during this mode. When the Forward
Loop Back mode is initiated, an internal switch connects a
600Ω load across the outputs of the Tip and Ring amplifiers
as shown in Figure 6.
DC Verification
When the internal signal path is provided, DC current will
flow from Tip to Ring. The DC current will force DET low,
indicating the presence of loop current. In addition to
verifying device functionality, toggling the logic output
verifies the interface to the system controller
FIGURE 5. FORWARD LOOP BACK SIGNAL FLOW
Power Supply Connections
Power should be applied to the evaluation board using the
primary power cable located at the top of the board. Prior to
applying power, the voltage setting of each supply should be
verified. The power supplies should be turned off while
mating the primary power cable to the evaluation board.
Jumper Setting
Reference Figure 5 for the placement of the jumpers to
enable Forward Loopback operation of the ISL5586.
DUT
POWER
TM
DIFF DRIVER
DIFF
DRV
3V LOGIC
TL, ILIM,
RD, RTD,
PROG CKTS
RJ11
IMPED
MATCH
JUMPER
JUMPER
TIP
RING
2W
PROTECTION
ISL5586
INPUT LOGIC
DIFF RCV
JUMPER
TRUTH TABLE
S1 S2 S3 S4
JUMPER
JP3
VRXP
JP1
VRXM
JP4
VRSP
JP2
VRSM
JP6
VTXP
JP5
VTXM
BSEL F2 F1 F0
FIGURE 6. FORWARD LOOP BACK CONNECTION AND JUMPERS
6
DIFF
RCV
Application Note 9918
TABLE 5. EVALUATION BOARD TEST POINTS DESCRIPTIONS
CONNECTOR
T1
T3, TP2
T4
TP1
DESCRIPTION
Connects to the Tip pin of the ISL5586. (The Tip pin is the Tip Power Amplifier Output).
Connects to the VBL pin of the ISL5586 and the external VBL supply connection.
Connects to the VBH pin of the ISL5586 and the anode of D1.
External VBH supply connection and the cathode of D1.
T5
Connects to the Battery Select pin of the ISL5586. (The BSEL pin Selects between high and low battery).
T6
Connects to the F2 pin of the ISL5586. (The F2 pin is a TTL Mode Control Input - MSB).
T7
Connects to the F1 pin of the ISL5586. (The F1 pin is a TTL Mode Control Input).
T8
Connects to the F0 pin of the ISL5586. (The F0 pin is a TTL Mode Control Input - LSB).
T9
Connects to the DET of the ISL5586. (The DET pin will either detect switch hook or ring trip based upon operating state).
T10
Connects to the VRSP pin of the ISL5586. (The VRSP pin is the Non-inverting Ringing Signal Input).
T11
Connects to the VRSM pin of the ISL5586. (The VRSM pin is the Inverting Ringing Signal Input).
T12
Connects to the VTXP pin of the ISL5586. (The VTXP pin is the positive Transmit Output Voltage).
T13
Connects to the VTXM pin of the ISL5586. (The VTXP pin is the negative Transmit Output Voltage).
T15
Connects to the POL pin of the ISL5586. (An external capacitor on this pin sets the polarity reversal time).
T16
Connects to the VRXP pin of the ISL5586. (The VRXP pin is the Non-inverting Analog Receive Voltage).
T17
Connects to the VRXM pin of the ISL5586. (The VRXM pin is the Inverting Analog Receive Voltage).
T18
Connects to the VZO pin of the ISL5586. (The VZO pin is the connection terminal for the impedance matching resistor).
T19
Connects to the -IN pin of the ISL5586. (The -IN pin is the connection terminal for high pass filter and impedance matching).
T20
Connects to the VFB pin of the ISL5586. (The VFB pin is the connection terminal for high pass filter and impedance matching).
T21
Connects to the TL pin of the ISL5586. (The TL pin is the Transient Current Limit Programming Resistor connection terminal).
T22,TP3
Connects to the VCC pin of the ISL5586 and the external VCC supply connection.
T23
Connects to the CDCP pin of the ISL5586. (The VCDCP pin is the DC Biasing Filter Capacitor - Positive terminal)..
T24
Connects to the CDCM pin of the ISL5586. (The VCDCM pin is the DC Biasing Filter Capacitor - Negative terminal).
T25
Connects to the RTD pin of the ISL5586. (The RTD pin is the Ring Trip Filter Network connection terminal).
T26
Connects to the ILIM pin of the ISL5586. (The ILIM pin is the Loop Current Limit programming resistor connection terminal).
T27
Connects to the RD pin of the ISL5586. (The RD pin is the Switch Hook Detection threshold programming connection terminal).
T28
Connects to the Ring pin of the ISL5586. (The Ring pin is the Ring Power Amplifier Output).
TP4
Connects to the -15V supply connection.
TP5
Connects to the +15V supply connection.
TP6
Connects to the Tip output of the eval board downstream from the protection resistor and fuse.
TP7
Connects to the Ring output of the eval board downstream from the protection resistor and fuse.
TP8
Connects to the inverting output of the differential driver circuit.
TP9
Connects to the non-inverting output of the differential driver circuit.
TP10, TP11
Connects to the inputs of the differential receive circuit.
7
Application Note 9918
CPS1
CPS2
D1
F1250T
CPS3
VCC
3
1
VBL
VBH
ISL5586 VRXP
D2
RP1
U1
TIP
VRXM
VRSP
B1100CC
RP2
RING
2
2
3
B1100CC
CRT
D3
RRT
VRSM
VTXP
CTXP
CTXM
VTXM
RTD
VZO
F1250T
CP
RSH
1
RD
RS
-IN
RIL
ILIM
CFB
RP
VFB
CDCM
BSEL
CDC
F0
CDCP
F1
CPOL
F2
POL
DET
TL
RTL
AGND
BGND
NOTE: CPS1 should be located as close as possible to the B1100CC to minimize turn on time. Less than 2 inches is recommended.
FIGURE 7. ISL5586 BASIC APPLICATION CIRCUIT
Basic Application Circuit Component List
COMPONENT
VALUE
TOLERANCE
RATING
COMPONENT
VALUE
TOLERANCE
RATING
U1 - Ringing SLIC
ISL5586
N/A
N/A
CDC
4.7µF
20%
10V
RRT
22.1kΩ
1%
0.1W
CFB
1.0µF
20%
10V
RSH
40kΩ
1%
0.1W
CPS1
0.47µF
20%
>100V
RIL
71.5kΩ
1%
0.1W
CPS2 , CPS3
0.1µF
20%
100V
RS
66.5kΩ
1%
0.1W
D1
1N400X type with breakdown > 100V.
RTL
17.8kΩ
1%
0.1W
D2, D3
1N4935 type.
RP
0Ω
N/A
N/A
RP1, RP2 = 50Ω,
0.5W,
matched to 0.1Ω.
Protection resistor values are application
dependent and will be determined by
protection requirements. Standard
applications will use ≥ 50Ω per side.
CP
Open
N/A
N/A
CRT , CRS , CSH ,
CTXP , CTXM, CPOL
0.47µF
20%
10V
Design Parameters: Ring Trip Threshold = 90mAPEAK. Switch Hook Threshold = 12mA, Loop Current Limit = 24.6mA, Transient current limit:
ISOURCE = 100mA, ISINK = 120mA, Synthesize Device Impedance = 66.5KΩ/133.3 = 500Ω, with 51Ω protection resistors, impedance across Tip
and Ring terminals = 603Ω.
8
Evaluation Board Schematic
U2
U3
U4
U5
C10
0.1µF
C11
0.1µF
TIP
J1
+15V
U3
U2
C8
0.1µF
U4
VCC
U5
C6
0.1µF
C9
0.1µF
VBH
CRXM
VBH
C3
C1
0.1µF 0.1µF
VCC
C5
0.1µF
1
TP6
VBL
CRXP
9
D3
2
2
RJ11
B1100CC
D4
1
TP7
RING
J2
RPR
F1250T
50
50
U1
25
RD
VTXP 12
RTD
ILIM
POL
CRTD
22.6k
0.47µF
CDCP
VFB 20
24 CDCM
CDCM
RTD
23
-IN 19
ILIM
18
RP
0.0
-IN
VFB
F0 8
CVTXP
F1 7
0.47µF
1 U5
3
+
2 --
2
R6
40k
1 4 +V
8
-V
10µF
5
U3
RD
CRD
51k
0.47µF
AGND
14
-15V
JP5
2
CFB
TP11
1
JP6
V
T
X J9
P
C15
1µF
3
R7
1M
+
2 --
U2
1
R8
R9
20k
20k
2
5
+
6 --
C16
1µF
U2
7 R10
20k
R12
1M
DIFF. RCV.
U2
9
8
10 +
R11
20k
TL
RTL
17.8k
DET
DET
BGND
R15
F0
2
BSEL
499
3.0V
66.5k
F1
R13
VCC
F2
100
S2
F2
U4 = U5= HA3-5033-5
R4
500k
R5
0.47µF
RS
INV
C14
4.7µF
CP
NP
CPOL
U1 = ISL5586
U2 = U3 = HA-4741
+15V
DET 9
RILIM
71.5k
R3
500k
10µF
5
TP9
V
T
X J8
M
BSEL 5
VZO
-V
NON - INV
-15V
JP4
0.47µF TP10
1
TL 21
VZO
C12
8
20k
VTXP
F2 6
15 POL
4 +V
CVTXM
VRSP 10
26
1 U4
U3
V
R
S J7
P
VRSM 11
27 RD
CDCP
CDC
4.7µF
VRSP 1
4
7
-5 +
DIFF. DRV.
VRXM
VBH
VRXM 17
VRXP
VRXP 16
VTXM
VTXM 13
VBL
28 RING
RING
RTD
VBH
3
22
TIP V
CC
1 TIP
20k
6
S3
F1
S4
FO
S1
BSEL
R14
150
Application Note 9918
RPT
+15V
R1
V
R
X J6
P
D1
VBL
VCC
3
20k
1 JP3 2
0.47µF
B1100CC
TP8
V
R
S J5
M
CVTXM
C2
0.1µF
C13
0.47µF
R2
V
R
X J4
M
VRSM 1 JP2 2
0.47µF
F1250T
3
JP1 2
1
C4
0.1µF
C7
0.1µF
VBL
-15V
Application Note 9918
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
2401 Palm Bay Rd., Mail Stop 53-204
Palm Bay, FL 32905
TEL: (321) 724-7000
FAX: (321) 724-7240
10
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil Ltd.
8F-2, 96, Sec. 1, Chien-kuo North,
Taipei, Taiwan 104
Republic of China
TEL: 886-2-2515-8508
FAX: 886-2-2515-8369
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