DATASHEET

CT
O D U EM E N T
R
P
TE
AC
O LE
EPL
OBS NDE D R 0
E
512
O MM
HC5
RECData Sheet
®
HC-5509B
August 2003
FN2799.8
ITU CO/Loop Carrier SLIC
Features
The HC-5509B telephone Subscriber Line Interface Circuit
integrates most of the BORSCHT functions on a monolithic
IC. The device is manufactured in a Dielectric Isolation (DI)
process and is designed for use as a high voltage interface
between the traditional telephone subscriber pair (Tip and
Ring) and the low voltage filtering and coding/decoding
functions of the line card. Together with a secondary
protection diode bridge and “feed” resistors, the device will
withstand 1000V lightning induced surges, in plastic
packages. The SLIC also maintains specified transmission
performance in the presence of externally induced
longitudinal currents. The BORSCHT functions that the SLIC
provides are:
• DI Monolithic High Voltage Process
Battery Feed with Subscriber Loop Current Limiting
• Switch Hook, Ground Key, and Ring Trip Detection
• Overvoltage Protection
• Selective Power Denial to Subscriber
• Ring Relay Driver
• Voice Path Active During Power Denial
• Supervisory Signaling Functions
• On-Chip Op Amp for 2-Wire Impedance Matching
• Hybrid Functions (with External Op Amp)
Applications
• Test (or Battery Reversal) Relay Driver
• Solid State Line Interface Circuit for PBX or Central Office
Systems, Digital Loop Carrier Systems
In addition, the SLIC provides selective denial of power to
subscriber loops, a programmable subscriber loop current
limit from 20mA to 60mA, a thermal shutdown with an alarm
output and line fault protection. Switch hook detection, ring
trip detection and ground key detection functions are also
incorporated in the SLIC device.
The HC-5509B SLIC is ideally suited for line card designs in
PBX and CO systems, replacing traditional transformer
solutions.
Part Number Information
PART
NUMBER
HC9P5509B-5
TEMP.
RANGE (oC)
0 to 75
PACKAGE
28 Ld SOIC
1
PKG. DWG.
#
• Compatible with Worldwide PBX and CO Performance
Requirements
• Controlled Supply of Battery Feed Current with
Programmable Current Limit
• Operates with 5V Positive Supply (VB+)
• Internal Ring Relay Driver and a Utility Relay Driver
• High Impedance Mode for Subscriber Loop
• High Temperature Alarm Output
• Low Power Consumption During Standby Functions
• Hotel/Motel Switching Systems
• Direct Inward Dialing (DID) Trunks
• Voice Messaging PBXs
• High Voltage 2-Wire/4-Wire, 4-Wire/2-Wire Hybrid
• Related Literature
- AN9607, Impedance Matching Design Equations
- AN9628, AC Voltage Gain
- AN9608, Implementing Pulse Metering
- AN549, The HC-5502S/4X Telephone Subscriber Line
Interface Circuits (SLIC)
M28.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HC-5509B
Absolute Maximum Ratings (Note 1)
Thermal Information
Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 15V
Maximum Supply Voltages
(VB+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
(VB+)-(VB-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75V
Thermal Resistance (Typical, Note 3)
θJA (oC/W)
θJC (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . .
72
N/A
Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . .150oC
Storage Temperature Range . . . . . . . . . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(For SMD; SOIC - Lead Tips Only)
Operating Conditions
Operating Temperature Range
HC-5509B-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC
Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V to 12V
Positive Power Supply (VB+) . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5%
Negative Power Supply (VB-) . . . . . . . . . . . . . . . . . . . . -42V to -58V
Loop Resistance (RL) . . . . . . . . . . . . . . . . .200Ω to 1750Ω (Note 2)
Die Characteristics
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Diode Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 x 120
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connected
Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied.
2. May Be Extended to 1900Ω With Application Circuit.
3. θJA is measured with the component mounted on an evaluation PC board in free air.
Unless Otherwise Specified, Typical Parameters are at TA = 25oC, Min-Max Parameters are Over Operating
Temperature Range, VB- = -48V, VB+ = 5V, AG = DG = BG = 0V. All AC Parameters are specified at 600Ω
2-Wire Terminating Impedance
Electrical Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
AC TRANSMISSION PARAMETERS
RX Input Impedance
300Hz to 3.4kHz (Note 4)
-
100
-
kΩ
TX Output Impedance
300Hz to 3.4kHz (Note 4)
-
-
20
Ω
4-Wire Input Overload Level
300Hz to 3.4kHz RL = 1200Ω ,
600Ω Reference
1.5
-
-
VPEAK
2-Wire Return Loss
SRL LO
Matched for 600Ω (Note 4)
26
35
-
dB
30
40
-
dB
ERL
30
40
-
dB
2-Wire Longitudinal to Metallic Balance
Off Hook
SRL HI
Per ANSI/IEEE STD 455-1976 (Note 4) 300Hz to
3400Hz
58
63
-
dB
4-Wire Longitudinal Balance
Off Hook
300Hz to 3400Hz (Note 4)
50
55
-
dB
Low Frequency Longitudinal Balance
R.E.A. Test Circuit
-
-
-67
dBmp
-
-
23
dBrnC
Longitudinal Current Capability
ILINE = 40mA, TA = 25oC (Note 4)
ILINE = 40mA, TA = 25oC (Note 4)
-
-
30
mARMS
-
±0.05
±0.2
dB
-
±0.05
±0.2
dB
Insertion Loss
2-Wire/4-Wire
0dBm at 1kHz, Referenced 600Ω
4-Wire/2-Wire
-
-
±0.2
dB
-
±0.02
±0.05
dB
Referenced to -10dBm (Note 4)
+3 to -40dBm
-
-
±0.05
dB
-40 to -50dBm
-
-
±0.1
dB
-50 to -55dBm
-
-
±0.3
dB
4-Wire/4-Wire
Frequency Response
300Hz to 3400Hz (Note 4) Referenced to
Absolute Level at 1kHz, 0dBm Referenced 600Ω
Level Linearity
2-Wire to 4-Wire and 4-Wire to 2-Wire
2
HC-5509B
Unless Otherwise Specified, Typical Parameters are at TA = 25oC, Min-Max Parameters are Over Operating
Temperature Range, VB- = -48V, VB+ = 5V, AG = DG = BG = 0V. All AC Parameters are specified at 600Ω
2-Wire Terminating Impedance (Continued)
Electrical Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
1
µs
Absolute Delay
2-Wire/4-Wire
(Note 4)
300Hz to 3400Hz
-
-
4-Wire/2-Wire
300Hz to 3400Hz
-
-
1
µs
4-Wire/4-Wire
300Hz to 3400Hz
-
-
1.5
µs
Transhybrid Loss, THL
(Note 4) See Figure 1
-
40
-
dB
Total Harmonic Distortion
2-Wire/4-Wire, 4-Wire/2-Wire, 4-Wire/4-Wire
Reference Level 0dBm at 600Ω
300Hz to 3400Hz (Note 4)
-
-
-52
dB
Idle Channel Noise
2-Wire and 4-Wire
(Note 4)
C-Message
-
-
5
dBrnC
Psophometric
-
-
-85
dBmp
3kHz Flat
-
-
15
dBrn
Power Supply Rejection Ratio
VB+ to 2-Wire
(Note 4)
30Hz to 200Hz, RL = 600Ω
20
29
-
dB
VB+ to 4-Wire
20
29
-
dB
VB- to 2-Wire
20
29
-
dB
VB- to 4-Wire
20
29
-
dB
30
-
-
dB
30
-
-
dB
VB- to 4-Wire
20
25
-
dB
VB- to 4-Wire
20
25
-
dB
50
-
500
µs
20
-
60
mA
10
-
-
%
-
±3
±5
mA
-
30
-
mA
RING to Ground
-
60
-
mA
TIP and RING to Ground
-
90
-
mA
Switch Hook Detection Threshold
-
12
15
mA
Ground Key Detection Threshold
-
10
-
mA
140
-
160
oC
-
10
-
mA
Ring Trip Detection Period
-
100
150
ms
Dial Pulse Distortion
-
0.1
0.5
ms
VB+ to 4-Wire
(Note 4)
200Hz to 16kHz, RL = 600Ω
VB- to 2-Wire
Ring Sync Pulse Width
DC PARAMETERS
Loop Current Programming
Limit Range
Accuracy
Loop Current During Power Denial
RL = 200Ω
Fault Currents
TIP to Ground
Thermal ALARM Output
Safe Operating Die Temperature Exceeded
Ring Trip Detection Threshold
VRING = 105VRMS, fRING = 20Hz
Relay Driver Outputs
On Voltage VOL
Off Leakage Current
IOL (PR) = 60mA, IOL (RD) = 30mA
-
0.2
0.5
V
VOH = 13.2V
-
±10
±100
µA
TTL/CMOS Logic Inputs (F0, F1, RS, TEST, PRI)
Logic ‘0’ VIL
Logic ‘1’ VIH
Input Current (F0, F1, RS, TEST, PRI)
3
0V ≤ VIN ≤ 5V
-
-
0.8
V
2.0
-
5.5
V
-
-
±100
µA
HC-5509B
Unless Otherwise Specified, Typical Parameters are at TA = 25oC, Min-Max Parameters are Over Operating
Temperature Range, VB- = -48V, VB+ = 5V, AG = DG = BG = 0V. All AC Parameters are specified at 600Ω
2-Wire Terminating Impedance (Continued)
Electrical Specifications
PARAMETER
Logic Outputs
Logic ‘0’ VOL
Logic ‘1’ VOH
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ILOAD = 800µA
-
0.1
0.5
V
ILOAD = 40µA
2.7
-
-
V
-
200
-
mW
Power Dissipation On Hook
Relay Drivers Off
IB+
VB+ = 5.25V, VB- = -58V, RLOOP =
IB-
VB+ = 5.25V, VB- = -58V, RLOOP =
∞
∞
-
-
6
mA
-6
-
-
mA
-
±5
-
mV
UNCOMMITTED OP AMP PARAMETERS
Input Offset Voltage
-
±10
-
nA
Differential Input Resistance
(Note 4)
-
1
-
MΩ
Output Voltage Swing
RL = 10kΩ
-
±3
-
VP-P
Small Signal GBW
(Note 4)
-
1
-
MHz
Input Offset Current
NOTE:
4. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial
design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification
compliance.
Pin Descriptions
SOIC
SYMBOL
DESCRIPTION
1
AG
(Note 5)
2
VB+
3
C1
Capacitor #C1 - An external capacitor to be connected between this terminal and analog ground. Required for proper
operation of the loop current limiting function.
4
F1
Function Address #1 - A TTL and CMOS compatible input used with F0 function address line to externally select logic
functions. The three selectable functions are mutually exclusive. See Truth Table. F1 should be toggled high after power
is applied.
5
F0
Function Address #0 - A TTL and CMOS compatible input used with F1 function address line to externally select logic
functions. The three selectable functions are mutually exclusive. See Truth Table.
6
RS
Ring Synchronization Input - A TTL - compatible clock input. The clock is arranged such that a positive pulse (50µs 500µs) occurs on the zero crossing of the ring voltage source, as it appears at the RFS terminal. For Tip side injected
systems, the RS pulse should occur on the negative going zero crossing and for Ring injected systems, on the positive
going zero crossing. This ensures that the ring delay activates and deactivates when the instantaneous ring voltage is
near zero. If synchronization is not required, the pin should be tied to 5.
7
SHD
Switch Hook Detection - An active low LS, TTL-compatible logic output. A line supervisory output.
8
GKD
Ground Key Detection - An active low LS, TTL-compatible logic output. A line supervisory output.
9
TST
A TTL logic input. A low on this pin will set a latch and keep the SLIC in a power down mode until the proper F1, F0
state is set and will keep ALM low. See Truth Table.
10
ALM
An LS TTL-compatible active low output which responds to the thermal detector circuit when a safe operating die
temperature has been exceeded. When TST is forced low by an external control signal, ALM is latched low until the
proper F1, F0 state and TST input is brought high. The ALM can be tied directly to the TST pin to power down the part
when a thermal fault is detected and then reset with F0, F1. See Truth Table. It is possible to ignore transient thermal
overload conditions in the SLIC by delaying the response to the TST pin from the ALM. Care must be exercised in
attempting this as continued thermal overstress may reduced component life.
11
ILMT
Loop Current Limit - Voltage on this pin sets the short loop current limiting conditions using a resistive voltage divider.
12
OUT1
The analog output of the spare operational amplifier.
13
-IN1
Analog Ground - To be connected to zero potential. Serves as a reference for the transmit output and receive input
terminals.
Positive Voltage Source - most positive supply.
The inverting analog input of the spare operational amplifier.
4
HC-5509B
Pin Descriptions
(Continued)
SOIC
SYMBOL
DESCRIPTION
14
TIP
An analog input connected to the TIP (more positive) side of the subscriber loop through a feed resistor and ring relay
contact. Functions with the RING terminal to receive voice signals from the telephone and for loop monitoring purpose.
15
RING
An analog input connected to the RING (more negative) side of the subscriber loop through a feed resistor. Functions
with the TIP terminal to receive voice signals from the telephone and for loop monitoring purposes.
16
RFS
Ring Feed Sense - Senses RING side of the loop for Ground Key Detection. During Ring injected ringing the ring signal
at this node is isolated from RF via the ring relay. For Tip injected ringing, the RF and RFS pins must be shorted.
17
VRX
Receive Input, 4-Wire Side - A high impedance analog input. AC signals appearing at this input drive the Tip Feed and
Ring Feed amplifiers differentially.
18
C2
19
VTX
Transmit Output, 4-Wire Side - A low impedance analog output which represents the differential voltage across TIP and
RING. Transhybrid balancing must be performed beyond this output to completely implement 2-Wire to 4-Wire conversion.
This output is referenced to analog ground. Since the DC level of this output varies with loop current, capacitive coupling
to the next stage is necessary.
20
PRI
A TTL compatible input used to control PR. PRI active High = PR active low.
21
PR
An active low open collector output. Can be used to drive a Polarity Reversal Relay.
22
DG
(Note 5)
Digital Ground - To be connected to zero potential. Serves as a reference for all digital inputs and outputs on the SLIC.
23
RD
Ring Relay Driver - An active low open collector output. Used to drive a relay that switches ringing signals onto the 2Wire line.
24
VFB
Feedback input to the tip feed amplifier; may be used in conjunction with transmit output signal and the spare op amp
to accommodate 2-Wire line impedance matching.
25
TF
Tip Feed - A low impedance analog output connected to the TIP terminal through a feed resistor.
26
RF
Ring Feed - A low impedance analog output connected to the RING terminal through a feed resistor.
27
VB-
The battery voltage source. The most negative supply.
28
BG
(Note 5)
Capacitor #C2 - An external capacitor to be connected between this terminal and ground. It prevents false ring trip
detection from occurring when longitudinal currents are induced onto the subscriber loop from power lines and other
noise sources. This capacitor should be nonpolarized.
Battery Ground - To be connected to zero potential. All loop current and some quiescent current flows into this ground
terminal.
NOTE:
5. All grounds (AG, BG, and DG) must be applied before VB+ or VB-. Failure to do so may result in premature failure of the part. If a user wishes
to run separate grounds off a line card, the AG must be applied first.
5
HC-5509B
Pinout
HC-5509B (SOIC)
TOP VIEW
TRUTH TABLE
F1
F0
AG 1
28 BG
0
0
Normal Loop Feed
VB+
2
27 VB-
0
1
RD Active (Ringing)
C1
3
26 RF
1
0
Power Down Latch RESET
F1
4
25 TF
1
0
Power On RESET
F0
5
24 VFB
6
23 RD
1
1
Loop Power Denial Active
RS
SHD
7
22 DG
GKD
8
21 PR
TST
9
20 PRI
ALM 10
19 VTX
ILMT 11
18 C2
OUT 1 12
17 VRX
-IN 1 13
16 RFS
ACTION
15 RING
TIP 14
Functional Diagram
SOIC
R
TF
25
VRX
R
-
TF
+
-IN 1
OUT 1
17
24
VTX
DG
VB+
19
2
AG
1
22
28
-
2R
OP AMP
+
R/2
BIAS
NETWORK
27
RF1
2R
R
VFB
13
12
4
2R
R
SHD
TA
+
2R
R
SH
THERM
LTD
4.5K
25K
100K
RING
15
100K
-
RFS
100K
RTD
GKD
90K
LA
+
100K
16
TSD
GK
25K
FAULT
DET
4.5K
6
IIL LOGIC INTERFACE
TIP
14
5
-
R
20
26
RF
90K
+
R = 108kΩ
-
VB/2
REF
18
3
C1
6
C2
GM
+
RF2
11
ILMT
RS
PRI
PR
23
RD
10
-
F0
21
RFC
RF
F1
TST
8
90K
VB-
9
7
90K
BG
SHD
GKD
ALM
HC-5509B
Overvoltage Protection and Longitudinal
Current Protection
The SLIC device, in conjunction with an external protection
bridge, will withstand high voltage lightning surges and
power line crosses.
High voltage surge conditions are as specified in Table 1.
The SLIC will withstand longitudinal currents up to a
maximum or 30mARMS , 15mARMS per leg, without any
performance degradation.
TABLE 1.
PARAMETER
TEST CONDITION
PERFORMANCE
(MAX)
UNITS
Longitudinal
Surge
10µs Rise/
1000µs Fall
±1000 (Plastic)
VPEAK
Metallic Surge
10µs Rise/
1000µs Fall
±1000 (Plastic)
VPEAK
T/GND, R/GND
10µs Rise/
1000µs Fall
±1000 (Plastic)
VPEAK
50/60Hz Current
T/GND,
R/GND
11 Cycles,
700 (Plastic)
Limited to 10ARMS
VRMS
Logic Diagram
RS
TTL TO I2L
RELAY
DRIVER
RD
TTL TO I2L
F0
I2L TO TTL
GKD
GK
I2L TO TTL
SHD
THERMAL
SHUT DOWN
TTL TO I2L
I2L TO TTL
ALM
F1
PD
SH
TTL TO I2L
THERMAL
SHUT
DOWN
LATCH
TO BIAS
NETWORK
TEST
INJ
A
B
C
KEY
7
A
B
C
HC-5509B
Typical Applications
5V
SYSTEM CONTROLLER
5V
K1
RS1
CS1
K2
PR
K1A
TIP
SHD GKD PRI RS TEST F1 ALARM F0
RD
RB2
RB1
RL2
TIP
ILIMIT
VRX+
SECONDARY
PROTECTION
(NOTE 8)
RL1
VFB
VBC5
FROM PCM
FILTER/CODER
CAC
SLIC
HC-5509B
VTX
PRIMARY
PROTECTION
KRF
RS2
KIB
-IN1
RF
KZ0
CS2
RFS
OUT1
TO HYBRID
BALANCE
NETWORK
VRING
RB4
150VPEAK (MAX)
RB3
RING
Z1
RING
VB-
BG
C2
DG
AG
V B+ C 1
PTC
C3
C4
5V
FIGURE 1. TYPICAL LINE CIRCUIT APPLICATION WITH THE MONOLITHIC SLIC
Typical Component Values
C1 = 0.5µF, 30V.
RL1 , RL2 ; Current Limit Setting Resistors:
C2 = 1.0µF ±10%, 20V (for other values of C2 , refer to
AN9667).
RL1 + RL2 > 90kΩ → offset.
C3 = 0.01µF, 100V, ±20%.
ILIMIT = (0.6) (RL1 + RL2)/(200 x RL2), RL1 typically 100kΩ.
KRF = 20kΩ, RF = 2(RB2 + RB4), K = Scaling Factor = 100).
C4 = 0.01µF, 100V, ±20%.
C5 = 0.01µF, 100V, ±20%.
RB1 = RB2 = RB3 = RB4 = 50Ω (1% absolute, matching
requirements covered in a Tech Brief).
CAC = 0.5µF, 20V.
RS1 = RS2 = 1kΩ , typically.
KZ0 = 60kΩ, (Z0 = 600Ω, K = Scaling Factor = 100).
CS1 = CS2 = 0.1µF, 200V typically, depending on VRing and
line length.
Z1 = 150V to 200V transient protector. PTC used as ring
generator ballast.
8
HC-5509B
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
C
0.10(0.004)
0.25(0.010) M
C A M
B S
MILLIMETERS
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.6969
0.7125
17.70
18.10
3
E
0.2914
0.2992
7.40
7.60
4
0.05 BSC
10.00
h
0.01
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
8o
0o
28
0o
10.65
-
0.394
N
0.419
1.27 BSC
H
α
NOTES:
MAX
A1
e
α
MIN
28
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
-
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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