Si8483DB www.vishay.com Vishay Siliconix P-Channel 12 V (D-S) MOSFET FEATURES PRODUCT SUMMARY VDS (V) -12 RDS(on) () (MAX.) ID (A) e 0.026 at VGS = -4.5 V -16 0.035 at VGS = -2.5 V -16 0.055 at VGS = -1.8 V -13 0.092 at VGS = -1.5 V -2.5 MICRO FOOT® 1.5 x 1 x xxx xx x 1 m m S 3 D 4 mm 1.5 1 Backside View Qg (TYP.) • TrenchFET® power MOSFET • Ultra-small 1.5 mm x 1 mm maximum outline • Ultra-thin 0.59 mm maximum height 21 nC S 2 • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 APPLICATIONS 1 G 6 S 5 D Bump Side View S • Load switch for smart phones, tablet PCs, and mobile computing - Low voltage drop - Low power consumption - Increased battery life G Marking Code: xxxx = 8483 xxx = Date / lot traceability code D P-Channel MOSFET Ordering Information: Si8483DB-T2-E1 (Lead (Pb)-free and halogen-free) ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS -12 Gate-Source Voltage VGS ± 10 TC = 25 °C Continuous Drain Current (TJ = 150 °C) TC = 70 °C TA = 25 °C Continuous Source-Drain Diode Current -15 ID -8.7 a, b -7 a, b Maximum Power Dissipation IDM TC = 25 °C TA = 25 °C -10.8 IS -2.3 a, b 13 TC = 70 °C 8.4 PD Package Reflow Conditions c W 2.77 a, b 1.77 a, b TA = 70 °C Operating Junction and Storage Temperature Range A -25 TC = 25 °C TA = 25 °C V -16 TA = 70 °C Pulsed Drain Current UNIT TJ, Tstg -55 to +150 IR/Convection °C 260 THERMAL RESISTANCE RATINGS PARAMETER Maximum Junction-to-Ambient a, f Maximum Junction-to-Case (Drain) Steady State SYMBOL TYPICAL MAXIMUM RthJA 37 45 RthJC 7 9.5 UNIT °C/W Notes a. Surface mounted on 1" x 1" FR4 board. b. t = 10 s. c. Refer to IPC/JEDEC® (J-STD-020), no manual or hand soldering. d. Case is defined as the top surface of the package. e. Based on TC = 25 °C. f. Maximum under steady state conditions is 85 °C/W. S15-0932-Rev. C, 20-Apr-15 Document Number: 63553 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si8483DB www.vishay.com Vishay Siliconix SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0, ID = -250 μA -12 - - V - -7 - - 2.8 - Static Drain-Source Breakdown Voltage VDS Temperature Coefficient VDS/TJ VGS(th) Temperature Coefficient VGS(th)/TJ Gate-Source Threshold Voltage ID = -250 μA mV/°C VGS(th) VDS = VGS, ID = -250 μA -0.4 - -0.8 V Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 10 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS On-State Drain Current a ID(on) Drain-Source On-State Resistance a VDS = -12 V, VGS = 0 V - - -1 VDS = -12 V, VGS = 0 V, TJ = 70 °C - - -10 VDS -5 V, VGS = -4.5 V -5 - 0.026 RDS(on) Forward Transconductance a gfs VGS = -4.5 V, ID = -1.5 A - 0.022 VGS = -2.5 V, ID = -1.5 A - 0.028 0.035 VGS = -1.8 V, ID = -1 A - 0.040 0.055 VGS = -1.5 V, ID = -0.5 A - 0.056 0.092 VDS = -6 V, ID = -1.5 A - 10 - μA A S Dynamic b Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Gate Resistance Rg Turn-On Delay Time tr td(off) - - 380 - VDS = -6 V, VGS = -10 V, ID = -1.5 A - 43 65 - 21 32 VDS = -6 V, VGS = -4.5 V, ID = -1.5 A - 2.1 - - 4.8 - VGS = -0.1 V, f = 1 MHz - 2.2 - - 20 40 - 25 50 VDD = -6 V, RL = 4 ID -1.5 A, VGEN = -4.5 V, Rg = 1 - 40 80 - 10 20 td(on) - 10 20 Rise Time Turn-Off Delay Time - 410 tf Fall Time Turn-On Delay Time 1840 - td(on) Rise Time Turn-Off Delay Time VDS = -6 V, VGS = 0 V, f = 1 MHz tr td(off) Fall Time VDD = -6 V, RL = 4 ID -1.5 A, VGEN = -10V, Rg = 1 tf pF nC ns - 10 20 - 40 80 - 10 20 - - -10.8 - - -25 - -0.8 -1.2 V - 30 60 ns - 12 25 nC - 11.5 - - 18.5 - Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulse Diode Forward Current ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Reverse Recovery Fall Time ta Reverse Recovery Rise Time tb TC = 25 °C IS = -1.5 A, VGS = 0 IF = -1.5 A, dI/dt = 100 A/μs, TJ = 25 °C A ns Notes a. Pulse test; pulse width 300 μs, duty cycle 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. S15-0932-Rev. C, 20-Apr-15 Document Number: 63553 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si8483DB www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 10 25 VGS = 5 V thru 2.5 V 8 VGS = 2 V ID - Drain Current (A) ID - Drain Current (A) 20 15 10 TC = 25 °C 6 4 TC = 125 °C 2 5 TC = - 55 °C VGS = 1.5 V 0 0 0.0 0.5 1.0 1.5 2.0 2.5 VDS - Drain-to-Source Voltage (V) 0 3.0 0.5 1 1.5 2 VGS - Gate-to-Source Voltage (V) Output Characteristics Transfer Characteristics 0.16 3000 VGS = 1.5 V C - Capacitance (pF) RDS(on) - On-Resistance (Ω) 2500 0.12 VGS = 1.8 V 0.08 VGS = 2.5 V 0.04 Ciss 2000 1500 1000 Coss 500 Crss VGS = 4.5 V 0 0 0 5 10 15 ID - Drain Current (A) 20 25 0 3 On-Resistance vs. Drain Current and Gate Voltage 9 12 Capacitance 10 1.4 RDS(on) - On-Resistance (Normalized) ID = 1.5 A VDS = 6 V VGS - Gate-to-Source Voltage (V) 6 VDS - Drain-to-Source Voltage (V) 8 VDS = 3 V 6 VDS = 9.6 V 4 2 0 0 10 20 30 40 50 1.3 VGS = 4.5 V, 2.5 V; ID = 1.5 A 1.2 VGS = 1.8 V; ID = 1.5 A 1.1 1.0 VGS = 1.5 V; ID = 0.5 A 0.9 0.8 - 50 - 25 0 25 50 75 100 125 Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C) Gate Charge On-Resistance vs. Junction Temperature S15-0932-Rev. C, 20-Apr-15 150 Document Number: 63553 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si8483DB www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 0.14 100 0.12 RDS(on) - On-Resistance (Ω) IS - Source Current (A) ID = 1.5 A TJ = 150 °C 10 TJ = 25 °C 1 0.10 0.08 0.06 TJ = 125 °C 0.04 0.02 0.1 TJ = 25 °C 0 0.0 0.2 0.4 0.6 0.8 1.0 VSD - Source-to-Drain Voltage (V) 1.2 0 Source-Drain Diode Forward Voltage 1 2 3 4 VGS - Gate-to-Source Voltage (V) 5 On-Resistance vs. Gate-to-Source Voltage 0.9 30 0.8 25 0.7 0.6 0.5 Power (W) VGS(th) (V) 20 ID = 250 μA 10 0.4 5 0.3 0.2 - 50 15 - 25 0 25 50 75 100 125 0 0.001 150 TJ - Temperature (°C) 0.01 0.1 1 Pulse (s) 10 100 Threshold Voltage Single Pulse Power, Junction-to-Ambient 1000 100 Limited by RDS(on)* ID - Drain Current (A) 10 100 μs 1 ms 1 10 ms 100 ms 1 s, 10 s DC 0.1 TA = 25 °C BVDSS Limited 0.01 0.1 1 10 100 VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Safe Operating Area, Junction-to-Ambient S15-0932-Rev. C, 20-Apr-15 Document Number: 63553 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si8483DB www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 15 24 12 Power Dissipation (W) ID - Drain Current (A) 20 16 Package Limited 12 8 9 6 3 4 0 0 0 25 50 75 100 125 TC - Ambient Temperature (°C) Current Derating* 150 25 50 75 100 125 150 T C - Case Temperature (°C) Power Derating * The power dissipation PD is based on TJ (max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. S15-0932-Rev. C, 20-Apr-15 Document Number: 63553 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si8483DB www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 Notes: 0.1 P DM 0.05 t1 t2 1. Duty Cycle, D = t1 t2 2. Per Unit Base = R thJA = 85 °C/W 0.02 Single Pulse 3. T JM - TA = PDMZthJA(t) 4. Surface Mounted 0.01 10-4 10-3 10-2 10-1 1 10 100 1000 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 0.05 0.02 Single Pulse 0.1 10-4 10-3 10-2 10-1 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Case Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?63553. S15-0932-Rev. C, 20-Apr-15 Document Number: 63553 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix MICRO FOOT®: 6-Bump (1.5 mm x 1 mm, 0.5 mm Pitch, 0.250 mm Bump Height) S S S G e XXXX D s XXX D D s 6x Ø b1 s Mark on Backside of Die e e s E 6x Ø 0.24 to 0.26 (Note 3) Solder mask ~ Ø 0.25 C NOTE 5 b A2 B A1 A e A e K e Bump (Note 2) Recommended Land Pattern Notes (unless otherwise specified) 1. Six (6) solder bumps are 95.5/3.8/0.7 Sn/Ag/Cu. 2. Backside surface is coated with a Ti/Ni/Ag layer. 3. Non-solder mask defined copper landing pad. 4. Laser marks on the silicon die back. 5. “b1” is the diameter of the solderable substrate surface, defined by an opening in the solder resist layer solder mask defined. 6. • is the location of pin 1 DIM. MILLIMETERS INCHES MIN. NOM. MAX. MIN. NOM. MAX. A 0.510 0.575 0.590 0.0201 0.0226 0.0232 A1 0.220 0.250 0.280 0.0087 0.0098 0.0110 A2 0.290 0.300 0.310 0.0114 0.0118 0.0122 b 0.297 0.330 0.363 0.0116 0.0129 0.0143 b1 0.250 0.0098 e 0.500 0.0197 s 0.210 0.230 0.250 0.0082 0.0090 0.0098 D 0.920 0.960 1.000 0.0362 0.0378 0.0394 E 1.420 1.460 1.500 0.0559 0.0575 0.0591 K 0.028 0.065 0.102 0.0011 0.0025 0.0040 Note • Use millimeters as the primary measurement. ECN: T15-0140-Rev. A, 20-Apr-15 DWG: 6035 Revison: 20-Apr-15 Document Number: 69426 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. 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