Si5933CDC Datasheet

Si5933CDC
Vishay Siliconix
Dual P-Channel 20 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
RDS(on) (Ω)
ID (A)a
0.144 at VGS = - 4.5 V
- 3.7
0.180 at VGS = - 2.5 V
- 3.0
0.222 at VGS = - 1.8 V
- 3.0
VDS (V)
- 20
Qg (Typ.)
4.1 nC
• Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFET
• 100 % Rg Tested
• Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
1206-8 ChipFET®
• Load Switch for Portable Devices
1
S1
S1
D1
S2
G1
D1
S2
G1
Marking Code
D2
G2
DI
XXX
D2
Bottom View
G2
Lot Traceability
and Date Code
Part #
Code
Ordering Information: Si5933CDC-T1-E3 (Lead (Pb)-free)
Si5933CDC-T1-GE3 (Lead (Pb)-free and Halogen-free)
D1
D2
P-Channel MOSFET
P-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (TJ = 150 °C)
Symbol
VDS
VGS
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
IDM
Pulsed Drain Current
Continuous Source-Drain Diode Current
Maximum Power Dissipation
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)d, e
ID
TC = 25 °C
TA = 25 °C
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
IS
PD
TJ, Tstg
Limit
- 20
±8
- 3.7
- 3.0
- 2.5b, c
- 2.0b, c
- 10
- 2.3
- 1.1b, c
2.8
1.8
1.3b, c
0.8b, c
- 55 to 150
260
Unit
V
A
W
°C
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
Maximum
Unit
RthJA
t≤5s
82
99
Maximum Junction-to-Ambientb, f
°C/W
35
45
Maximum Junction-to-Foot (Drain)
Steady State
RthJF
Notes:
a. Based on TC = 25 °C.
b. Surface mounted on 1" x 1" FR4 board.
c. t = 5 s.
d. See Solder Profile (www.vishay.com/ppg?73257). The ChipFET is a leadless package. The end of the lead terminal is exposed copper (not
plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required
to ensure adequate bottom side solder interconnection.
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under steady state conditions is 130 °C/W.
Document Number: 68822
S10-0548-Rev. B, 08-Mar-10
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1
Si5933CDC
Vishay Siliconix
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter
Symbol
Test Conditions
Min.
VDS
VGS = 0 V, ID = - 250 µA
- 20
Typ.
Max.
Unit
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
ΔVDS/TJ
V
- 19
ID = - 250 µA
mV/°C
VGS(th) Temperature Coefficient
ΔVGS(th)/TJ
Gate-Source Threshold Voltage
VGS(th)
VDS = VGS, ID = - 250 µA
-1
V
IGSS
VDS = 0 V, VGS = ± 8 V
± 100
nA
VDS = - 20 V, VGS = 0 V
-1
VDS = - 20 V, VGS = 0 V, TJ = 70 °C
-5
Gate-Source Leakage
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currenta
ID(on)
Drain-Source On-State Resistancea
Forward Transconductancea
RDS(on)
gfs
VDS ≤ - 5 V, VGS = - 4.5 V
2
- 0.45
- 10
µA
A
VGS = - 4.5 V, ID = - 2.5 A
0.120
0.144
VGS = - 2.5 V, ID = - 2.2 A
0.150
0.180
VGS = - 1.8 V, ID = - 2.0 A
0.185
0.222
VDS = - 10 V, ID = - 2.5 A
18
Ω
S
Dynamicb
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Gate Resistance
Rg
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
276
VDS = - 10 V, VGS = 0 V, f = 1 MHz
VDS = - 10 V, VGS = - 5 V, ID = - 2.5 A
VDS = - 10 V, VGS = - 4.5 V, ID = - 2.5 A
td(off)
4.5
6.8
4.1
6.2
0.6
f = 1 MHz
VDD = - 10 V, RL = 5.0 Ω
ID ≅ - 2.0 A, VGEN = - 4.5 V, Rg = 1 Ω
1.1
5.5
11
11
17
34
51
22
33
tf
8
16
td(on)
5
10
14
21
17
26
8
16
tr
td(off)
nC
1.0
td(on)
tr
pF
60
43
VDD = - 10 V, RL = 5.0 Ω
ID ≅ - 2.0 A, VGEN = - 5 V, Rg = 1 Ω
tf
Ω
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulse Diode Forward Current
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Reverse Recovery Fall Time
ta
Reverse Recovery Rise Time
tb
TC = 25 °C
- 2.3
- 10
IS = - 2.0 A, VGS = 0 V
IF = - 2.0 A, dI/dt = - 100 A/µs, TJ = 25 °C
A
- 0.8
- 1.2
V
23
35
ns
13
20
nC
10
13
ns
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 68822
S10-0548-Rev. B, 08-Mar-10
Si5933CDC
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
2.0
10
VGS = 5 V thru 2.5 V
VGS = 2 V
I D - Drain Current (A)
I D - Drain Current (A)
8
6
4
VGS = 1.5 V
1.5
1.0
TC = 25 °C
0.5
2
TC = 125 °C
VGS = 1 V
0
1
2
3
4
TC = - 55 °C
0.0
0.0
0
5
0.3
VDS - Drain-to-Source Voltage (V)
0.9
1.2
1.5
VGS - Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
0.30
540
0.25
450
VGS = - 1.8 V
C - Capacitance (pF)
R DS(on) - On-Resistance (Ω)
0.6
0.20
VGS = - 2.5 V
0.15
0.10
VGS = - 4.5 V
360
Ciss
270
180
0.05
90
0.00
0
Coss
Crss
0
2
4
6
8
10
0
4
8
12
16
ID - Drain Current (A)
VDS - Drain-to-Source Voltage (V)
On Resistance vs. Drain Current
Capacitance
5
20
1.5
VDS = 10 V
3
VDS = 16 V
2
1.3
(Normalized)
R DS(on) - On-Resistance
VGS - Gate-to-Source Voltage (V)
ID = 2.5 A
4
1.1
VGS = 4.5 V; I D = 2.5 A
0.9
1
VGS = 2.5 V; I D = 2.2 A
0
0
1
2
3
4
5
0.7
- 50
- 25
0
25
50
75
100
125
Qg - Total Gate Charge (nC)
TJ - Junction Temperature (°C)
Gate Charge
On-Resistance vs. Junction Temperature
Document Number: 68822
S10-0548-Rev. B, 08-Mar-10
150
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Si5933CDC
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.25
100
R DS(on) - On-Resistance (Ω)
I S - Source Current (A)
ID = 2.5 A
10
TJ = 150 °C
TJ = 25 °C
1
0.1
0.0
0.20
TJ = 125 °C
0.15
0.10
TJ = 25 °C
0.05
0.00
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
1.6
2
VSD - Source-to-Drain Voltage (V)
4
6
8
VGS - Gate-to-Source Voltage (V)
Forward Diode Voltage vs. Temperature
On-Resistance vs. Gate-to-Source Voltage
0.7
5
0.6
4
0.5
Power (W)
VGS(th) (V)
ID = 250 µA
0.4
0.3
0.2
- 50
3
2
1
- 25
0
25
50
75
100
125
0
0.001
150
0.01
0.1
1
TJ - Temperature (°C)
Time (s)
Threshold Voltage
Single Pulse Power
10
100
100
I D - Drain Current (A)
10
Limited by RDS(on)*
100 µs
1
1 ms
10 ms
100 ms
1 s, 10 s
DC
0.1
TA = 25 °C
Single Pulse
BVDSS Limited
0.01
0.1
1
10
100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area, Junction-to-Ambient
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Document Number: 68822
S10-0548-Rev. B, 08-Mar-10
Si5933CDC
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
5
I D - Drain Current (A)
4
3
2
1
0
0
25
50
75
100
125
150
TC - Case Temperature (°C)
4
1.2
3
0.9
Power (W)
Power (W)
Current Derating*
2
1
0.6
0.3
0
0.0
0
25
50
75
100
125
150
0
25
50
75
100
125
TC - Case Temperature (°C)
TA - Ambient Temperature (°C)
Power, Junction-to-Foot
Power, Junction-to-Ambient
150
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 68822
S10-0548-Rev. B, 08-Mar-10
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Si5933CDC
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
0.1
Notes:
0.05
PDM
0.02
t1
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = RthJA = 110 °C/W
Single Pulse
3. TJM - TA = PDMZthJA(t)
4. Surface Mounted
0.01
10 -4
10 -3
10 -2
10 -1
1
100
10
1000
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10 -4
10 -3
10 -2
10 -1
1
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?68822.
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Document Number: 68822
S10-0548-Rev. B, 08-Mar-10
Package Information
Vishay Siliconix
1206-8 ChipFETR
4
L
D
8
7
6
5
4
1
S
2
e
3
E1
5
6
7
8
4
3
2
1
E
4
b
x
c
Backside View
2X 0.10/0.13 R
C1
A
DETAIL X
NOTES:
1.
All dimensions are in millimeaters.
2.
Mold gate burrs shall not exceed 0.13 mm per side.
3.
Leadframe to molded body offset is horizontal and vertical shall not exceed
0.08 mm.
4.
Dimensions exclusive of mold gate burrs.
5.
No mold flash allowed on the top and bottom lead surface.
MILLIMETERS
Dim
A
b
c
c1
D
E
E1
e
L
S
INCHES
Min
Nom
Max
Min
Nom
Max
1.00
−
1.10
0.039
−
0.043
0.25
0.30
0.35
0.010
0.012
0.014
0.1
0.15
0.20
0.004
0.006
0.008
0
−
0.038
0
−
0.0015
2.95
3.05
3.10
0.116
0.120
0.122
1.825
1.90
1.975
0.072
0.075
0.078
1.55
1.65
1.70
0.061
0.065
0.067
0.65 BSC
0.28
−
0.0256 BSC
0.42
0.011
−
0.55 BSC
0.022 BSC
5_Nom
5_Nom
0.017
ECN: C-03528—Rev. F, 19-Jan-04
DWG: 5547
Document Number: 71151
15-Jan-04
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1
AN812
Vishay Siliconix
Dual-Channel 1206-8 ChipFETr Power MOSFET Recommended
Pad Pattern and Thermal Performance
INTRODUCTION
New Vishay Siliconix ChipFETs in the leadless 1206-8
package feature the same outline as popular 1206-8 resistors
and capacitors but provide all the performance of true power
semiconductor devices. The 1206-8 ChipFET has the same
footprint as the body of the LITTLE FOOTR TSOP-6, and can
be thought of as a leadless TSOP-6 for purposes of visualizing
board area, but its thermal performance bears comparison
with the much larger SO-8.
This technical note discusses the dual ChipFET 1206-8
pin-out, package outline, pad patterns, evaluation board
layout, and thermal performance.
80 mil
25 mil
43 mil
18 mil
10 mil
26 mil
PIN-OUT
FIGURE 2.
Figure 1 shows the pin-out description and Pin 1 identification
for the dual-channel 1206-8 ChipFET device. The pin-out is
similar to the TSOP-6 configuration, with two additional drain
pins to enhance power dissipation and thus thermal
performance. The legs of the device are very short, again
helping to reduce the thermal path to the external heatsink/pcb
and allowing a larger die to be fitted in the device if necessary.
Dual 1206-8 ChipFET
S1
G1
S2
Footprint With Copper Spreading
The pad pattern with copper spreading shown in Figure 2
improves the thermal area of the drain connections (pins 5 and
6, pins 7 and 8) while remaining within the confines of the basic
footprint. The drain copper area is 0.0019 sq. in. or
1.22 sq. mm. This will assist the power dissipation path away
from the device (through the copper leadframe) and into the
board and exterior chassis (if applicable) for the dual device.
The addition of a further copper area and/or the addition of vias
to other board layers will enhance the performance still further.
An example of this method is implemented on the Vishay
Siliconix Evaluation Board described in the next section
(Figure 3).
G2
D1
THE VISHAY SILICONIX EVALUATION
BOARD FOR THE DUAL 1206-8
D1
D2
D2
FIGURE 1.
For package dimensions see the 1206-8 ChipFET package
outline drawing (http://www.vishay.com/doc?71151).
BASIC PAD PATTERNS
The basic pad layout with dimensions is shown in Application
Note 826, Recommended Minimum Pad Patterns With Outline
Drawing
Access
for
Vishay Siliconix
MOSFETs,
(http://www.vishay.com/doc?72286). This is sufficient for low
power dissipation MOSFET applications, but power
semiconductor performance requires a greater copper pad
area, particularly for the drain leads.
Document Number: 71127
12-Dec-03
The dual ChipFET 1206-08 evaluation board measures 0.6 in
by 0.5 in. Its copper pad pattern consists of an increased pad
area around each of the two drain leads on the top-side—
approximately 0.0246 sq. in. or 15.87 sq. mm—and vias
added through to the underside of the board, again with a
maximized copper pad area of approximately the board-size
dimensions, split into two for each of the drains. The outer
package outline is for the 8-pin DIP, which will allow test
sockets to be used to assist in testing.
The thermal performance of the 1206-8 on this board has been
measured with the results following on the next page. The
testing included comparison with the minimum recommended
footprint on the evaluation board-size pcb and the industry
standard one-inch square FR4 pcb with copper on both sides
of the board.
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AN812
Vishay Siliconix
Front of Board
Back of Board
ChipFETr
vishay.com
FIGURE 3.
Junction-to-Foot Thermal Resistance (the Package
Performance)
Thermal performance for the 1206-8 ChipFET measured as
junction-to-foot thermal resistance is 30_C/W typical, 40_C/W
maximum for the dual device. The “foot” is the drain lead of the
device as it connects with the body. This is identical to the dual
SO-8 package RQjf performance, a feat made possible by
shortening the leads to the point where they become only a
small part of the total footprint area.
Junction-to-Ambient Thermal Resistance
(dependent on pcb size)
The typical RQja for the dual-channel 1206-8 ChipFET is
90_C/W steady state, identical to the SO-8. Maximum ratings
are 110_C/W for both the 1206-8 and the SO-8. Both packages
have comparable thermal performance on the 1” square pcb
footprint with the 1206-8 dual package having a quarter of the
body area, a significant factor when considering board area.
The results show that a major reduction can be made in the
thermal resistance by increasing the copper drain area. In this
example, a 57_C/W reduction was achieved without having to
increase the size of the board. If increasing board size is an
option, a further 38_C/W reduction was obtained by
maximizing the copper from the drain on the larger 1” square
PCB.
200
Min. Footprint
160
Thermal Resistance (C/W)
THERMAL PERFORMANCE
Dual EVB
120
80
40
1” Square PCB
Testing
To aid comparison further, Figure 4 illustrates ChipFET 1206-8
dual thermal performance on two different board sizes and
three different pad patterns.The results display the thermal
performance out to steady state and produce a graphic
account on how an increased copper pad area for the drain
connections can enhance thermal performance. The
measured steady state values of RQja for the Dual 1206-8
ChipFET are :
1) Minimum recommended pad pattern (see
Figure 2) on the evaluation board size of
0.5 in x 0.6 in.
185_C/W
2) The evaluation board with the pad pattern
described on Figure 3.
128_C/W
3) Industry standard 1” square pcb with
maximum copper both sides.
90_C/W
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2
0
10-5 10-4
10-3
10-2
10-1
1
10
100
1000
Time (Secs)
FIGURE 4.
Dual 1206-8 ChipFET
SUMMARY
The thermal results for the dual-channel 1206-8 ChipFET
package display identical power dissipation performance to
the SO-8 with a footprint reduction of 80%. Careful design of
the package has allowed for this performance to be achieved.
The short leads allow the die size to be maximized and thermal
resistance to be reduced within the confines of the TSOP-6
body size.
ASSOCIATED DOCUMENT
1206-8 ChipFET Single Thermal performance, AN811,
(http://www.vishay.com/doc?71126).
Document Number: 71127
12-Dec-03
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR 1206-8 ChipFET®
0.093
0.026
0.016
0.010
(0.650)
(0.406)
(0.244)
0.036
(0.914)
0.022
(0.559)
(2.032)
0.080
(2.357)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
Return to Index
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Document Number: 72593
Revision: 21-Jan-08
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requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
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Revision: 02-Oct-12
1
Document Number: 91000