Si5432DC Datasheet

New Product
Si5432DC
Vishay Siliconix
N-Channel 20-V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
RDS(on) (Ω)
ID (A)a
0.020 at VGS = 4.5 V
6
VDS (V)
20
0.025 at VGS = 2.5 V
• Halogen-free
Qg (Typ.)
• TrenchFET® Power MOSFET
RoHS
10 nC
6
COMPLIANT
APPLICATIONS
• Load Switches for Portable Devices
1206-8 ChipFET
TM
1
D
D
D
D
D
D
D
G
G
S
S
Bottom View
N-Channel MOSFET
Ordering Information: Si5432DC-T1-GE3 (Lead (Pb)-free and Halogen-free)
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (TJ = 150 °C)
Symbol
VDS
VGS
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
Pulsed Drain Current
TC = 25 °C
TA = 25 °C
TC = 25 °C
TC = 70 °C
Maximum Power Dissipation
TA = 25 °C
TA = 70 °C
Operating Junction and Storage Temperature Range
Continuous Source-Drain Diode Current
Soldering Recommendations (Peak Temperature)e, f
ID
IDM
IS
PD
TJ, Tstg
Limit
20
± 12
Unit
V
6a
6a
6a, b, c
6a, b, c
30
5.2
2.1b, c
6.3
4
2.5b, c
1.6b, c
- 55 to 150
260
A
W
°C
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
Maximum
Unit
t≤5s
RthJA
40
50
Maximum Junction-to-Ambienta, c, d
°C/W
RthJF
15
20
Maximum Junction-to-Foot (Drain)
Steady State
Notes:
a. Package limited, TC = 25 °C.
b. Surface Mounted on 1" x 1" FR4 board.
c. t = 10 s.
d. Maximum under Steady State conditions is 95 °C/W.
e. See Reliability Manual for profile. The ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result
of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure
adequate bottom side solder interconnection.
f. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
Document Number: 68925
S-82293-Rev. A, 22-Sep-08
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1
New Product
Si5432DC
Vishay Siliconix
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter
Symbol
Test Conditions
Min.
VDS
VGS = 0 V, ID = 250 µA
20
Typ.
Max.
Unit
Static
Drain-Source Breakdown Voltage
ΔVDS /TJ
VDS Temperature Coefficient
VGS(th) Temperature Coefficient
ΔVGS(th)/TJ
Gate-Source Threshold Voltage
ID = 250 µA
VGS(th)
VDS = VGS , ID = 250 µA
Gate-Source Leakage
IGSS
VDS = 0 V, VGS = ± 12 V
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currenta
ID(on)
Drain-Source On-State Resistancea
Forward Transconductancea
RDS(on)
gfs
V
25
mV/°C
- 4.0
0.6
1.5
V
± 100
nA
VDS = 20 V, VGS = 0 V
1
VDS = 20 V, VGS = 0 V, TJ = 55 °C
10
VDS ≥ 5 V, VGS = 4.5 V
30
µA
A
VGS = 4.5 V, ID = 8.3 A
0.016
0.020
VGS = 2.5 V, ID = 4.5 A
0.020
0.025
VDS = 10 V, ID = 8.3 A
45
Ω
S
b
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Gate Resistance
Turn-on Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-on Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Rg
1200
VDS = 10 V, VGS = 0 V, f = 1 MHz
VDS = 10 V, VGS = 10 V, ID = 8.3 A
VDS = 10 V, VGS = 4.5 V, ID = 8.3 A
td(off)
pF
22
33
10
15
2.5
f = 1 MHz
VDD = 10 V, RL = 1.5 Ω
ID ≅ 6.7 A, VGEN = 4.5 V, Rg = 1 Ω
Ω
2.4
15
25
10
15
35
55
tf
12
20
td(on)
10
15
12
20
25
40
10
15
tr
td(off)
nC
1.7
td(on)
tr
220
100
VDD = 10 V, RL = 1.5 Ω
ID ≅ 6.7 A, VGEN = 10 V, Rg = 1 Ω
tf
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulse Diode Forward Current
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Reverse Recovery Fall Time
ta
Reverse Recovery Rise Time
tb
TC = 25 °C
5.2
30
IS = 6.7 A, VGS = 0 V
IF = 6.7 A, dI/dt = 100 A/µs, TJ = 25 °C
A
0.8
1.2
V
20
40
ns
10
20
nC
10
10
ns
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 68925
S-82293-Rev. A, 22-Sep-08
New Product
Si5432DC
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
10
30
VGS = 5 thru 2.5 V
TC = - 55 °C
8
I D - Drain Current (A)
I D - Drain Current (A)
24
18
VGS = 2 V
12
6
TC = 125 °C
4
2
6
TC = 25 °C
VGS = 1 V
0
0.0
0.5
1.0
1.5
VGS = 1.5 V
2.0
2.5
0
0.0
3.0
0.5
1.0
1.5
2.0
VGS - Gate-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
1500
0.026
0.024
Ciss
0.022
C - Capacitance (pF)
RDS(on) - On-Resistance (Ω)
1200
0.020
VGS = 2.5 V
0.018
0.016
VGS = 4.5 V
0.014
900
600
Coss
300
0.012
Crss
0
0.010
0
6
12
18
24
0
30
5
15
20
VDS - Drain-to-Source Voltage (V)
ID - Drain Current (A)
On-Resistance vs. Drain Current
Capacitance
10
1.6
ID = 8.3 A
ID = 8.3 A
8
VGS = 4.5 V, 2.5 V
VDS = 10 V
6
VDS = 16 V
4
2
(Normalized)
1.4
R DS(on) - On-Resistance
VGS - Gate-to-Source Voltage (V)
10
1.2
1.0
0.8
0
0
5
10
15
Qg - Total Gate Charge (nC)
Gate Charge
Document Number: 68925
S-82293-Rev. A, 22-Sep-08
20
25
0.6
- 50
- 25
0
25
50
75
100
125
150
TJ - Junction Temperature (°C)
On-Resistance vs. Junction Temperature
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New Product
Si5432DC
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.050
100
ID = 8.3 A
TJ = 150 °C
R DS(on) - On-Resistance (Ω)
I S - Source Current (A)
0.040
TJ = 25 °C
10
1
0.0
0.030
TJ = 125 °C
0.020
TJ = 25 °C
0.010
0.000
0.2
0.4
0.6
0.8
1.0
1.2
0
1
VSD - Source-to-Drain Voltage (V)
4
5
On-Resistance vs. Gate-to-Source Voltage
1.4
50
40
ID = 250 µA
Power (W)
1.2
V GS(th) (V)
3
VGS - Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
1.0
0.8
30
20
10
0.6
0.4
- 50
2
- 25
0
25
50
75
100
125
0
0.001
150
0.01
0.1
1
10
100
600
Time (s)
TJ - Temperature (°C)
Single Pulse Power
Threshold Voltage
100
Limited by RDS(on)*
100 µs
ID - Drain Current (A)
10
1 ms
1
10 ms
0.1
TA = 25 °C
Single Pulse
0.01
0.1
BVDSS
Limited
100 ms
1s
10 s
DC
1
10
100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area, Junction-to-Ambient
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Document Number: 68925
S-82293-Rev. A, 22-Sep-08
New Product
Si5432DC
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
18
8
15
Power (W)
ID - Drain Current (A)
6
12
9
Package Limited
4
6
2
3
0
0
0
25
50
75
100
TC - Case Temperature (°C)
Current Derating*
125
150
25
50
75
100
125
150
TC - Case Temperature (°C)
Power Derating
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 68925
S-82293-Rev. A, 22-Sep-08
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New Product
Si5432DC
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Normalized Effective Transient
Thermal Impedance
2
1
Duty Cycle = 0.5
0.2
Notes:
0.1
PDM
0.1
0.05
t1
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = RthJA = 80 °C/W
0.02
3. TJM - TA = PDMZthJA(t)
Single Pulse
4. Surface Mounted
0.01
10-4
10-3
10-2
10-1
1
Square Wave Pulse Duration (s)
10
100
600
Normalized Thermal Transient Impedance, Junction-to-Ambient
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10-4
10-3
10-2
10-1
Square Wave Pulse Duration (s)
1
10
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?68925.
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Document Number: 68925
S-82293-Rev. A, 22-Sep-08
Package Information
Vishay Siliconix
1206-8 ChipFETR
4
L
D
8
7
6
5
4
1
S
2
e
3
E1
5
6
7
8
4
3
2
1
E
4
b
x
c
Backside View
2X 0.10/0.13 R
C1
A
DETAIL X
NOTES:
1.
All dimensions are in millimeaters.
2.
Mold gate burrs shall not exceed 0.13 mm per side.
3.
Leadframe to molded body offset is horizontal and vertical shall not exceed
0.08 mm.
4.
Dimensions exclusive of mold gate burrs.
5.
No mold flash allowed on the top and bottom lead surface.
MILLIMETERS
Dim
A
b
c
c1
D
E
E1
e
L
S
INCHES
Min
Nom
Max
Min
Nom
Max
1.00
−
1.10
0.039
−
0.043
0.25
0.30
0.35
0.010
0.012
0.014
0.1
0.15
0.20
0.004
0.006
0.008
0
−
0.038
0
−
0.0015
2.95
3.05
3.10
0.116
0.120
0.122
1.825
1.90
1.975
0.072
0.075
0.078
1.55
1.65
1.70
0.061
0.065
0.067
0.65 BSC
0.28
−
0.0256 BSC
0.42
0.011
−
0.55 BSC
0.022 BSC
5_Nom
5_Nom
0.017
ECN: C-03528—Rev. F, 19-Jan-04
DWG: 5547
Document Number: 71151
15-Jan-04
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1
AN811
Vishay Siliconix
Single-Channel 1206-8 ChipFETr Power MOSFET Recommended
Pad Pattern and Thermal Performance
INTRODUCTION
New Vishay Siliconix ChipFETs in the leadless 1206-8
package feature the same outline as popular 1206-8 resistors
and capacitors but provide all the performance of true power
semiconductor devices. The 1206-8 ChipFET has the same
footprint as the body of the LITTLE FOOTR TSOP-6, and can
be thought of as a leadless TSOP-6 for purposes of visualizing
board area, but its thermal performance bears comparison
with the much larger SO-8.
80 mil
68 mil
This technical note discusses the single-channel ChipFET
1206-8 pin-out, package outline, pad patterns, evaluation
board layout, and thermal performance.
28 mil
26 mil
PIN-OUT
Figure 1 shows the pin-out description and Pin 1 identification
for the single-channel 1206-8 ChipFET device. The pin-out is
similar to the TSOP-6 configuration, with two additional drain
pins to enhance power dissipation and thermal performance.
The legs of the device are very short, again helping to reduce
the thermal path to the external heatsink/pcb and allowing a
larger die to be fitted in the device if necessary.
Single 1206-8 ChipFET
1
D
D
D
D
The pad pattern with copper spreading shown in Figure 2
improves the thermal area of the drain connections (pins
1,2,3,6.7,8) while remaining within the confines of the basic
footprint. The drain copper area is 0.0054 sq. in. or
3.51 sq. mm). This will assist the power dissipation path away
from the device (through the copper leadframe) and into the
board and exterior chassis (if applicable) for the single device.
The addition of a further copper area and/or the addition of vias
to other board layers will enhance the performance still further.
An example of this method is implemented on the
Vishay Siliconix Evaluation Board described in the next
section (Figure 3).
D
D
G
S
Bottom View
FIGURE 1.
For package dimensions see the 1206-8 ChipFET package
outline drawing (http://www.vishay.com/doc?71151).
BASIC PAD PATTERNS
The basic pad layout with dimensions is shown in Application
Note 826, Recommended Minimum Pad Patterns With Outline
Drawing
Access
for
Vishay Siliconix
MOSFETs,
(http://www.vishay.com/doc?72286). This is sufficient for low
power dissipation MOSFET applications, but power
semiconductor performance requires a greater copper pad
area, particularly for the drain leads.
Document Number: 71126
12-Dec-03
FIGURE 2. Footprint With Copper Spreading
THE VISHAY SILICONIX EVALUATION
BOARD FOR THE SINGLE 1206-8
The ChipFET 1206-08 evaluation board measures 0.6 in by
0.5 in. Its copper pad pattern consists of an increased pad area
around the six drain leads on the top-side—approximately
0.0482 sq. in. 31.1 sq. mm—and vias added through to the
underside of the board, again with a maximized copper pad
area of approximately the board-size dimensions. The outer
package outline is for the 8-pin DIP, which will allow test
sockets to be used to assist in testing.
The thermal performance of the 1206-8 on this board has been
measured with the results following on the next page. The
testing included comparison with the minimum recommended
footprint on the evaluation board-size pcb and the industry
standard one-inch square FR4 pcb with copper on both sides
of the board.
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1
AN811
Vishay Siliconix
Front of Board
Back of Board
ChipFETr
vishay.com
FIGURE 3.
Junction-to-Foot Thermal Resistance
(the Package Performance)
Thermal performance for the 1206-8 ChipFET measured as
junction-to-foot thermal resistance is 15_C/W typical, 20_C/W
maximum for the single device. The “foot” is the drain lead of
the device as it connects with the body. This is identical to the
SO-8 package RQjf performance, a feat made possible by
shortening the leads to the point where they become only a
small part of the total footprint area.
Junction-to-Ambient Thermal Resistance
(dependent on pcb size)
The typical RQja for the single-channel 1206-8 ChipFET is
80_C/W steady state, compared with 68_C/W for the SO-8.
Maximum ratings are 95_C/W for the 1206-8 versus 80_C/W
for the SO-8.
The results show that a major reduction can be made in the
thermal resistance by increasing the copper drain area. In this
example, a 45_C/W reduction was achieved without having to
increase the size of the board. If increasing board size is an
option, a further 33_C/W reduction was obtained by
maximizing the copper from the drain on the larger 1” square
pcb.
160
Thermal Resistance (C/W)
THERMAL PERFORMANCE
120
Single EVB
Min. Footprint
80
1” Square PCB
40
Testing
To aid comparison further, Figure 4 illustrates ChipFET 1206-8
thermal performance on two different board sizes and three
different pad patterns. The results display the thermal
performance out to steady state and produce a graphic
account of how an increased copper pad area for the drain
connections can enhance thermal performance. The
measured steady state values of RQja for the single 1206-8
ChipFET are :
1) Minimum recommended pad pattern (see
Figure 2) on the evaluation board size of
0.5 in x 0.6 in.
156_C/W
2) The evaluation board with the pad pattern
described on Figure 3.
111_C/W
3) Industry standard 1” square pcb with
maximum copper both sides.
78_C/W
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2
0
10-5 10-4
10-3
10-2
10-1
1
10
100
1000
Time (Secs)
FIGURE 4. Single 1206−8 ChipFET
SUMMARY
The thermal results for the single-channel 1206-8 ChipFET
package display similar power dissipation performance to the
SO-8 with a footprint reduction of 80%. Careful design of the
package has allowed for this performance to be achieved. The
short leads allow the die size to be maximized and thermal
resistance to be reduced within the confines of the TSOP-6
body size.
ASSOCIATED DOCUMENT
1206-8 ChipFET Dual Thermal performance, AN812
(http://www.vishay.com/doc?71127).
Document Number: 71126
12-Dec-03
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR 1206-8 ChipFET®
0.093
0.026
0.016
0.010
(0.650)
(0.406)
(0.244)
0.036
(0.914)
0.022
(0.559)
(2.032)
0.080
(2.357)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
Return to Index
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Document Number: 72593
Revision: 21-Jan-08
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Revision: 02-Oct-12
1
Document Number: 91000