DATASHEET

ISL8487E, ISL81487L, ISL81487E
®
Data Sheet
February 27, 2006
±15kV ESD Protected, 1/8 Unit Load, 5V,
Low Power, High Speed or Slew Rate
Limited, RS-485/RS-422 Transceivers
FN6051.7
Features
• RS-485 I/O Pin ESD Protection . . . . . . . . . . ±15kV HBM
- Class 3 ESD Level on all Other Pins . . . . . . >7kV HBM
These Intersil RS-485/RS-422 devices are ESD protected,
fractional unit load (UL), BiCMOS, 5V powered, single
transceivers that meet both the RS-485 and RS-422
standards for balanced communication. Each driver output/
receiver input is protected against ±15kV ESD strikes,
without latch-up. Unlike competitive devices, this Intersil
family is specified for 10% tolerance supplies (4.5V to 5.5V).
• Fractional Unit Load Allows up to 256 Devices on the Bus
• Specified for 10% Tolerance Supplies
• High Data Rate Version (ISL81487E) . . . . . up to 5Mbps
• Slew Rate Limited Versions for Error Free Data
Transmission (ISL8487E, ISL81487L) . . . . .up to 250kbps
• Low Current Shutdown Mode (Except ISL81487E). . . 0.5µA
All devices present a 1/8 “unit load” to the RS-485 bus,
which allows up to 256 transceivers on the network for large
node count systems (e.g., process automation, remote
meter reading systems). In a remote utility meter reading
system, individual (apartments for example) utility meter
readings are routed to a concentrator via an RS-485
network, so the high allowed node count minimizes the
number of repeaters required to network all the meters. Data
for all meters is then read out from the concentrator via a
single access port, or a wireless link.
• Low Quiescent Supply Current:
- ISL8487E, ISL81487L . . . . . . . . . . . . . . . 145µA (Max.)
- ISL81487E . . . . . . . . . . . . . . . . . . . . . . . . 420µA (Max.)
• -7V to +12V Common Mode Input Voltage Range
• Three State Rx and Tx Outputs
• 30ns Propagation Delays, 5ns Skew (ISL81487E)
• Half Duplex Pinouts
• Operate from a Single +5V Supply (10% Tolerance)
Slew rate limited drivers on the ISL8487E and ISL81487L
reduce EMI, and minimize reflections from improperly
terminated transmission lines, or unterminated stubs in
multidrop and multipoint applications. Data rates up to
250kbps are achievable with these devices.
• Current Limiting and Thermal Shutdown for Driver
Overload Protection
• Pin Compatible Replacements for: MAX487E, (ISL8487E);
LTC1487, ADM1487 (ISL81487L); MAX1487E, ST485ER
(ISL81487E)
Data rates up to 5Mbps are achievable by using the
ISL81487E, which features higher slew rates.
• Pb-Free Plus Anneal Available (RoHS Compliant)
Receiver (Rx) inputs feature a “fail-safe if open” design,
which ensures a logic high Rx output if Rx inputs are floating.
Applications
• High Node Count Networks
Driver (Tx) outputs are short circuit protected, even for
voltages exceeding the power supply voltage. Additionally,
on-chip thermal shutdown circuitry disables the Tx outputs to
prevent damage if power dissipation becomes excessive.
• Automated Utility Meter Reading Systems
• Factory Automation
• Security Networks
These half duplex devices multiplex the Rx inputs and Tx
outputs to allow transceivers with Rx and Tx disable
functions in 8 lead packages.
• Building Environmental Control Systems
• Industrial/Process Control Networks
TABLE 1. SUMMARY OF FEATURES
PART
NUMBER
HALF/FULL
DUPLEX
NO. OF DEVICES
DATA RATE
ALLOWED ON BUS
(Mbps)
ISL8487E
Half
256
0.25
Yes
Yes
120
Yes
8
ISL81487L
Half
256
0.25
Yes
Yes
120
Yes
8
ISL81487E
Half
256
5
No
Yes
350
No
8
1
SLEW-RATE
LIMITED?
RECEIVER/
QUIESCENT LOW POWER
PIN
DRIVER ENABLE?
ICC (µA)
SHUTDOWN? COUNT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL8487E, ISL81487L, ISL81487E
Pinout
Truth Tables
ISL8487E, ISL81487L, ISL81487E (PDIP, SOIC)
TOP VIEW
TRANSMITTING
INPUTS
RO 1
R
RE 2
DE 3
DI 4
D
8
VCC
RE
DE
DI
Z
Y
7
B/Z
X
1
1
0
1
6
A/Y
X
1
0
1
0
5
GND
0
0
X
High-Z
High-Z
1
0
X
High-Z *
High-Z *
Ordering Information
PART NO.
(BRAND)
PART
MARKING
*Shutdown Mode for ISL8487E, ISL81487L (See Note 7)
TEMP.
RANGE
(°C)
PKG.
PACKAGE DWG. #
ISL8487EIB*
8487EIB
-40 to 85
8 Ld SOIC
M8.15
ISL8487EIBZ*
(Note)
8487EIBZ
-40 to 85
8 Ld SOIC
(Pb-free)
M8.15
ISL8487EIP
ISL8487EIP
-40 to 85
8 Ld PDIP
E8.3
ISL8487EIPZ
(Note)
8487EIPZ
-40 to 85
8 Ld PDIP** E8.3
(Pb-free)
ISL81487LIB*
81487LIB
-40 to 85
8 Ld SOIC
M8.15
ISL81487LIBZ* 81487LIBZ
(Note)
-40 to 85
8 Ld SOIC
(Pb-free)
M8.15
ISL81487LIP
ISL81487LIP
-40 to 85
8 Ld PDIP
E8.3
ISL81487LIPZ
(Note)
81487LIPZ
-40 to 85
8 Ld PDIP** E8.3
(Pb-free)
ISL81487EIB*
81487EIB
-40 to 85
8 Ld SOIC
M8.15
ISL81487EIBZ* 81487EIBZ
(Note)
-40 to 85
8 Ld SOIC
(Pb-free)
M8.15
ISL81487EIP
-40 to 85
8 Ld PDIP
E8.3
-40 to 85
8 Ld PDIP** E8.3
(Pb-free)
ISL81487EIP
ISL81487EIPZ ISL81487EIPZ
(Note)
OUTPUTS
RECEIVING
INPUTS
OUTPUT
RE
DE
A-B
RO
0
0
≥ +0.2V
1
0
0
≤ -0.2V
0
0
0
Inputs Open
1
1
0
X
High-Z *
1
1
X
High-Z
*Shutdown Mode for ISL8487E, ISL81487L (See Note 7)
*Add “-T” suffix to part number for tape and reel packaging.
**Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
2
FN6051.7
February 27, 2006
ISL8487E, ISL81487L, ISL81487E
Pin Descriptions
PIN
FUNCTION
RO
Receiver output: If A > B by at least 0.2V, RO is high; If A < B by 0.2V or more, RO is low; RO = High if A and B are unconnected (floating).
RE
Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high.
DE
Driver output enable. The driver outputs, Y and Z, are enabled by bringing DE high. They are high impedance when DE is low.
DI
Driver input. A low on DI forces output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low.
GND
Ground connection.
A/Y
±15kV HBM ESD Protected, RS-485/422 level, noninverting receiver input and non-inverting driver output. Pin is an input (A) if
DE = 0; pin is an output (Y) if DE = 1.
B/Z
±15kV HBM ESD Protected, RS-485/422 level, inverting receiver input and inverting driver output. Pin is an input (B) if DE = 0; pin is
an output (Z) if DE = 1.
VCC
System power supply input (4.5V to 5.5V).
Typical Operating Circuits
ISL8487E, ISL81487L, ISL81487E
+5V
+5V
+
8
0.1µF
0.1µF
+
8
VCC
1 RO
VCC
R
D
2 RE
B/Z
7
3 DE
A/Y
6
4 DI
RT
RT
7
B/Z
DE 3
6
A/Y
RE 2
R
D
GND
GND
5
5
3
DI 4
RO 1
FN6051.7
February 27, 2006
ISL8487E, ISL81487L, ISL81487E
Absolute Maximum Ratings
Thermal Information
VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Input Voltages
DI, DE, RE . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC +0.5V)
Input/Output Voltages
A/Y, B/Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -8V to +12.5V
RO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC +0.5V)
Short Circuit Duration
Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table
Thermal Resistance (Typical, Note 1)
θJA (°C/W)
8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . .
170
8 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . .
140
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
Operating Conditions
Temperature Range
ISL8XXXIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
(
Electrical Specifications
Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified.
Typicals are at VCC = 5V, TA = 25°C, (Note 2)
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP
(°C)
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS
Driver Differential VOUT (no load)
VOD1
Driver Differential VOUT (with load)
VOD2
Change in Magnitude of Driver
Differential VOUT for
Complementary Output States
Driver Common-Mode VOUT
Change in Magnitude of Driver
Common-Mode VOUT for
Complementary Output States
Full
-
-
VCC
V
R = 50Ω (RS-422), (Figure 1)
Full
2
3
-
V
R = 27Ω (RS-485), (Figure 1)
Full
1.5
2.3
5
V
∆VOD
R = 27Ω or 50Ω, (Figure 1)
Full
-
0.01
0.2
V
VOC
R = 27Ω or 50Ω, (Figure 1)
Full
-
-
3
V
∆VOC
R = 27Ω or 50Ω, (Figure 1)
Full
-
0.01
0.2
V
Logic Input High Voltage
VIH
DE, DI, RE
Full
2
-
-
V
Logic Input Low Voltage
VIL
DE, DI, RE
Full
-
-
0.8
V
Logic Input Current
IIN1
DE, DI, RE
Full
-2
-
2
µA
Input Current (A/Y, B/Z), (Note 10)
IIN2
DE = 0V, VCC = 4.5 to
5.5V
IIN2
Receiver Differential Threshold
Voltage
VTH
DE = 0V, VCC = 0V
-7V ≤ VCM ≤ 12V
VIN = 12V
Full
-
-
140
µA
VIN = -7V
Full
-
-
-120
µA
VIN = 12V
Full
-
-
180
µA
VIN = -7V
Full
-
-
-100
µA
Full
-0.2
-
0.2
V
Receiver Input Hysteresis
∆VTH
VCM = 0V
25
-
70
-
mV
Receiver Output High Voltage
VOH
IO = -4mA, VID = 200mV
Full
3.5
-
-
V
Receiver Output Low Voltage
VOL
IO = -4mA, VID = 200mV
Full
-
-
0.4
V
Three-State (high impedance)
Receiver Output Current
IOZR
0.4V ≤ VO ≤ 2.4V
Full
-
-
±1
µA
Receiver Input Resistance
RIN
-7V ≤ VCM ≤ 12V
Full
96
-
-
kΩ
4
FN6051.7
February 27, 2006
ISL8487E, ISL81487L, ISL81487E
Electrical Specifications
Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified.
Typicals are at VCC = 5V, TA = 25°C, (Note 2) (Continued)
PARAMETER
SYMBOL
No-Load Supply Current, (Note 3)
ICC
TEST CONDITIONS
ISL81487E, DI, RE = 0V DE = VCC
or VCC
DE = 0V
ISL8487E, ISL81487L,
DI, RE = 0V or VCC
TEMP
(°C)
MIN
TYP
MAX
UNITS
Full
-
400
500
µA
Full
-
350
420
µA
DE = VCC
Full
-
160
200
µA
DE = 0V
Full
-
120
145
µA
Shutdown Supply Current
ISHDN
(Note 7), DE = 0V, RE = VCC, DI = 0V or VCC
Full
-
0.5
8
µA
Driver Short-Circuit Current,
VO = High or Low
IOSD1
DE = VCC, -7V ≤ VY or VZ ≤ 12V, (Note 4)
Full
35
-
250
mA
Receiver Short-Circuit Current
IOSR
0V ≤ VO ≤ VCC
Full
7
-
85
mA
tPLH, tPHL
RDIFF = 54Ω, CL = 100pF, (Figure 2)
Full
15
24
50
ns
tSKEW
RDIFF = 54Ω, CL = 100pF, (Figure 2)
Full
-
3
10
ns
tR, tF
RDIFF = 54Ω, CL = 100pF, (Figure 2)
Full
3
12
25
ns
tZH
CL = 100pF, SW = GND, (Figure 2)
Full
-
14
70
ns
SWITCHING CHARACTERISTICS (ISL81487E)
Driver Input to Output Delay
Driver Output Skew
Driver Differential Rise or Fall Time
Driver Enable to Output High
Driver Enable to Output Low
tZL
CL = 100pF, SW = VCC, (Figure 2)
Full
-
14
70
ns
Driver Disable from Output High
tHZ
CL = 15pF, SW = GND, (Figure 2)
Full
-
44
70
ns
Driver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, (Figure 2)
Full
-
21
70
ns
Receiver Input to Output Delay
tPLH, tPHL
(Figure 4)
Full
30
90
150
ns
tSKD
(Figure 4)
25
-
5
-
ns
tZH
CL = 15pF, SW = GND, (Figure 5)
Full
-
9
50
ns
Receiver Skew | tPLH - tPHL |
Receiver Enable to Output High
Receiver Enable to Output Low
tZL
CL = 15pF, SW = VCC, (Figure 5)
Full
-
9
50
ns
Receiver Disable from Output High
tHZ
CL = 15pF, SW = GND, (Figure 5)
Full
-
9
50
ns
Receiver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, (Figure 5)
Full
-
9
50
ns
Full
5
-
-
Mbps
Maximum Data Rate
fMAX
SWITCHING CHARACTERISTICS (ISL8487E)
Driver Input to Output Delay
Driver Output Skew
Driver Differential Rise or Fall Time
tPLH, tPHL
RDIFF = 54Ω, CL = 100pF, (Figure 2)
Full
250
650
2000
ns
tSKEW
RDIFF = 54Ω, CL = 100pF, (Figure 2)
Full
-
160
800
ns
tR, tF
RDIFF = 54Ω, CL = 100pF, (Figure 2)
Full
250
900
2000
ns
Driver Enable to Output High
tZH
CL = 100pF, SW = GND, (Figure 3, Note 5)
Full
250
1000
2000
ns
Driver Enable to Output Low
tZL
CL = 100pF, SW = VCC, (Figure 3, Note 5)
Full
250
860
2000
ns
Driver Disable from Output High
tHZ
CL = 15pF, SW = GND, (Figure 3)
Full
300
660
3000
ns
Driver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, (Figure 3)
Full
300
640
3000
ns
Receiver Input to Output Delay
tPLH, tPHL
(Figure 4)
Full
250
500
2000
ns
tSKD
Receiver Skew | tPLH - tPHL |
(Figure 4)
25
-
60
-
ns
Receiver Enable to Output High
tZH
CL = 15pF, SW = GND, (Figure 5, Note 6)
Full
-
10
50
ns
Receiver Enable to Output Low
tZL
CL = 15pF, SW = VCC, (Figure 5, Note 6)
Full
-
10
50
ns
Receiver Disable from Output High
tHZ
CL = 15pF, SW = GND, (Figure 5)
Full
-
10
50
ns
Receiver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, (Figure 5)
Full
-
10
50
ns
Full
250
-
-
kbps
(Note 7)
Full
50
120
600
ns
Maximum Data Rate
fMAX
Time to Shutdown
tSHDN
Driver Enable from Shutdown to
Output High
tZH(SHDN)
CL = 100pF, SW = GND, (Figure 3, Notes 7, 8)
Full
-
1000
2000
ns
Driver Enable from Shutdown to
Output Low
tZL(SHDN)
CL = 100pF, SW = VCC, (Figure 3, Notes 7, 8)
Full
-
1000
2000
ns
5
FN6051.7
February 27, 2006
ISL8487E, ISL81487L, ISL81487E
Electrical Specifications
Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified.
Typicals are at VCC = 5V, TA = 25°C, (Note 2) (Continued)
TEMP
(°C)
MIN
TYP
MAX
UNITS
CL = 15pF, SW = GND, (Figure 5, Notes 7, 9)
Full
-
800
2500
ns
CL = 15pF, SW = VCC, (Figure 5, Notes 7, 9)
Full
-
800
2500
ns
tPLH, tPHL
RDIFF = 54Ω, CL = 100pF, (Figure 2)
Full
150
650
1200
ns
tSKEW
RDIFF = 54Ω, CL = 100pF, (Figure 2)
Full
-
160
600
ns
tR, tF
RDIFF = 54Ω, CL = 100pF, (Figure 2)
Full
250
900
1200
ns
tZH
CL = 100pF, SW = GND, (Figure 3, Note 5)
Full
100
1000
1500
ns
PARAMETER
SYMBOL
Receiver Enable from Shutdown to
Output High
tZH(SHDN)
Receiver Enable from Shutdown to
Output Low
tZL(SHDN)
TEST CONDITIONS
SWITCHING CHARACTERISTICS (ISL81487L)
Driver Input to Output Delay
Driver Output Skew
Driver Differential Rise or Fall Time
Driver Enable to Output High
Driver Enable to Output Low
tZL
CL = 100pF, SW = VCC, (Figure 3, Note 5)
Full
100
1000
1500
ns
Driver Disable from Output High
tHZ
CL = 15pF, SW = GND, (Figure 3)
Full
150
750
1500
ns
Driver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, (Figure 3)
Full
150
750
1500
ns
Receiver Input to Output Delay
tPLH, tPHL
(Figure 4)
Full
30
175
250
ns
tSKD
(Figure 4)
25
-
13
-
ns
Receiver Skew | tPLH - tPHL |
Receiver Enable to Output High
tZH
CL = 15pF, SW = GND, (Figure 5, Note 6)
Full
-
10
50
ns
Receiver Enable to Output Low
tZL
CL = 15pF, SW = VCC, (Figure 5, Note 6)
Full
-
10
50
ns
Receiver Disable from Output High
tHZ
CL = 15pF, SW = GND, (Figure 5)
Full
-
10
50
ns
Receiver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, (Figure 5)
Full
-
10
50
ns
Full
250
-
-
kbps
Maximum Data Rate
fMAX
Time to Shutdown
tSHDN
(Note 7)
Full
50
140
600
ns
Driver Enable from Shutdown to
Output High
tZH(SHDN)
CL = 100pF, SW = GND, (Figure 3, Notes 7, 8)
Full
-
1100
2000
ns
Driver Enable from Shutdown to
Output Low
tZL(SHDN)
CL = 100pF, SW = VCC, (Figure 3, Notes 7, 8)
Full
-
1000
2000
ns
Receiver Enable from Shutdown to
Output High
tZH(SHDN)
CL = 15pF, SW = GND, (Figure 5, Notes 7, 9)
Full
-
900
2000
ns
Receiver Enable from Shutdown to
Output Low
tZL(SHDN)
CL = 15pF, SW = VCC, (Figure 5, Notes 7, 9)
Full
-
900
2000
ns
Human Body Model
25
-
±15
-
kV
25
-
>±7
-
kV
ESD PERFORMANCE
RS-485 Pins (A/Y, B/Z)
All Other Pins
NOTES:
2. Currents into device pins are positive; currents out of device pins are negative. Voltages are referenced to ground unless otherwise specified.
3. Supply current specification is valid for loaded drivers when DE = 0V.
4. Applies to peak current. See “Typical Performance Curves” for more information.
5. When testing the ISL8487E and ISL81487L, keep RE = 0 to prevent the device from entering SHDN.
6. When testing the ISL8487E and ISL81487L, the RE signal high time must be short enough (typically <200ns) to prevent the device from entering
SHDN.
7. The ISL8487E and ISL81487L are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 50ns, the parts
are guaranteed not to enter shutdown. If the inputs are in this state for at least 600ns, the parts are guaranteed to have entered shutdown. See
“Low-Power Shutdown Mode” section.
8. Keep RE = VCC, and set the DE signal low time >600ns to ensure that the device enters SHDN.
9. Set the RE signal high time >600ns to ensure that the device enters SHDN.
10. Devices meeting these limits are denoted as “1/8 unit load (1/8 UL)” transceivers. The RS-485 standard allows up to 32 Unit Loads on the bus,
so there can be 256 1/8 UL devices on a bus.
6
FN6051.7
February 27, 2006
ISL8487E, ISL81487L, ISL81487E
Test Circuits and Waveforms
R
DE
VCC
Z
DI
VOD
D
Y
VOC
R
FIGURE 1. DRIVER VOD AND VOC
3V
DI
1.5V
1.5V
0V
tPLH
tPHL
VOH
VCC
CL = 100pF
DE
50%
OUT (Y)
VOL
Z
DI
tPHL
RDIFF
D
Y
CL = 100pF
50%
tPLH
VOH
OUT (Z)
50%
50%
VOL
SIGNAL
GENERATOR
90%
DIFF OUT (Y - Z)
+VOD
90%
10%
10%
tR
-VOD
tF
SKEW = |tPLH (Y or Z) - tPHL (Z or Y)|
FIGURE 2A. TEST CIRCUIT
FIGURE 2B. MEASUREMENT POINTS
FIGURE 2. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES
DE
DI
SIGNAL
GENERATOR
Z
500Ω
VCC
D
SW
Y
GND
CL
3V
DE
NOTE 7
1.5V
1.5V
0V
tZH, tZH(SHDN)
PARAMETER OUTPUT
RE
DI
SW
CL (pF)
tHZ
Y/Z
X
1/0
GND
15
tLZ
Y/Z
X
0/1
VCC
15
tZH
Y/Z
0 (Note 5)
1/0
GND
100
tZL
Y/Z
0 (Note 5)
0/1
VCC
100
tZH(SHDN)
Y/Z
1 (Note 7)
1/0
GND
100
tZL(SHDN)
Y/Z
1 (Note 7)
OUTPUT HIGH
NOTE 7
(SHDN) for ISL8487E and ISL81487L only.
0/1
VCC
FIGURE 3A. TEST CIRCUIT
tHZ
VOH - 0.5V
OUT (Y, Z)
VOH
2.3V
0V
tZL, tZL(SHDN)
tLZ
NOTE 7
VCC
OUT (Y, Z)
2.3V
OUTPUT LOW
100
VOL + 0.5V V
OL
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. DRIVER ENABLE AND DISABLE TIMES
7
FN6051.7
February 27, 2006
ISL8487E, ISL81487L, ISL81487E
Test Circuits and Waveforms (Continued)
RE
+1.5V
3V
15pF
B
R
A
A
RO
1.5V
1.5V
0V
tPHL
tPLH
VCC
SIGNAL
GENERATOR
50%
RO
50%
0V
FIGURE 4A. TEST CIRCUIT
FIGURE 4B. MEASUREMENT POINTS
FIGURE 4. RECEIVER PROPAGATION DELAY
RE
B
SIGNAL
GENERATOR
1kΩ
RO
R
VCC
SW
A
GND
NOTE 7
3V
15pF
RE
1.5V
1.5V
0V
tZH, tZH(SHDN)
(SHDN) for ISL8487E and ISL81487L only.
OUTPUT HIGH
NOTE 7
PARAMETER
DE
A
SW
tHZ
0
+1.5V
GND
tLZ
0
-1.5V
VCC
tZH (Note 6)
0
+1.5V
GND
tZL, tZL(SHDN)
tZL (Note 6)
0
-1.5V
VCC
NOTE 7
tZH(SHDN) (Note 7)
0
+1.5V
GND
RO
tZL(SHDN) (Note 7)
0
-1.5V
VCC
FIGURE 5A. TEST CIRCUIT
tHZ
VOH - 0.5V
RO
VOH
1.5V
0V
tLZ
VCC
1.5V
OUTPUT LOW
VOL + 0.5V V
OL
FIGURE 5B. MEASUREMENT POINTS
FIGURE 5. RECEIVER ENABLE AND DISABLE TIMES
Application Information
RS-485 and RS-422 are differential (balanced) data
transmission standards for use in long haul or noisy
environments. RS-422 is a subset of RS-485, so RS-485
transceivers are also RS-422 compliant. RS-422 is a pointto-multipoint (multidrop) standard, which allows only one
driver and up to 10 (assuming one unit load devices)
receivers on each bus. RS-485 is a true multipoint standard,
which allows up to 32 one unit load devices (any
combination of drivers and receivers) on each bus. To allow
for multipoint operation, the RS-485 spec requires that
drivers must handle bus contention without sustaining any
damage.
Another important advantage of RS-485 is the extended
common mode range (CMR), which specifies that the driver
outputs and receiver inputs withstand signals that range from
+12V to -7V. RS-422 and RS-485 are intended for runs as
long as 4000’, so the wide CMR is necessary to handle
8
ground potential differences, as well as voltages induced in
the cable by external fields.
Receiver Features
These devices utilize a differential input receiver for maximum
noise immunity and common mode rejection. Input sensitivity
is ±200mV, as required by the RS-422 and RS-485
specifications.
Receiver input resistance of 96kΩ surpasses the RS-422
spec of 4kΩ, and is eight times the RS-485 “Unit Load (UL)”
requirement of 12kΩ minimum. Thus, these products are
known as “one-eighth UL” transceivers, and there can be up
to 256 of these devices on a network while still complying
with the RS-485 loading spec.
Receiver inputs function with common mode voltages as
great as ±7V outside the power supplies (i.e., +12V and
-7V), making them ideal for long networks where induced
voltages are a realistic concern.
FN6051.7
February 27, 2006
ISL8487E, ISL81487L, ISL81487E
All the receivers include a “fail-safe if open” function that
guarantees a high level receiver output if the receiver inputs
are unconnected (floating).
Receivers easily meet the data rates supported by the
corresponding driver, and receiver outputs are three-statable
via the active low RE input.
Driver Features
The RS-485/422 driver is a differential output device that
delivers at least 1.5V across a 54Ω load (RS-485), and at
least 2V across a 100Ω load (RS-422). The drivers feature
low propagation delay skew to maximize bit width, and to
minimize EMI.
Driver outputs are three-statable via the active high DE
input.
The ISL8487E and ISL81487L driver outputs are slew rate
limited to minimize EMI, and to minimize reflections in
unterminated or improperly terminated networks. Data rate
on these slew rate limited versions is a maximum of
250kbps. ISL81487E drivers are not limited, so faster output
transition times allow data rates of at least 5Mbps.
Data Rate, Cables, and Terminations
RS-485/422 are intended for network lengths up to 4000’,
but the maximum system data rate decreases as the
transmission length increases. Devices operating at 5Mbps
are limited to lengths less than a few hundred feet, while the
250kbps versions can operate at full data rates with lengths
in excess of 1000’.
Twisted pair is the cable of choice for RS-485/422 networks.
Twisted pair cables tend to pick up noise and other
electromagnetically induced voltages as common mode
signals, which are effectively rejected by the differential
receivers in these ICs.
To minimize reflections, proper termination is imperative
when using the 5Mbps device. Short networks using the
250kbps versions need not be terminated, but, terminations
are recommended unless power dissipation is an overriding
concern.
In point-to-point, or point-to-multipoint (single driver on bus)
networks, the main cable should be terminated in its
characteristic impedance (typically 120Ω) at the end farthest
from the driver. In multi-receiver applications, stubs
connecting receivers to the main cable should be kept as
short as possible. Multipoint (multi-driver) systems require
that the main cable be terminated in its characteristic
impedance at both ends. Stubs connecting a transceiver to
the main cable should be kept as short as possible.
The driver output stages incorporate short circuit current
limiting circuitry which ensures that the output current never
exceeds the RS-485 spec, even at the common mode
voltage range extremes. Additionally, these devices utilize a
foldback circuit which reduces the short circuit current, and
thus the power dissipation, whenever the contending voltage
exceeds either supply.
In the event of a major short circuit condition, these devices
also include a thermal shutdown feature that disables the
drivers whenever the die temperature becomes excessive.
This eliminates the power dissipation, allowing the die to
cool. The drivers automatically re-enable after the die
temperature drops about 15 degrees. If the contention
persists, the thermal shutdown/re-enable cycle repeats until
the fault is cleared. Receivers stay operational during
thermal shutdown.
Low Power Shutdown Mode (Excluding
ISL81487E)
These CMOS transceivers all use a fraction of the power
required by their bipolar counterparts, but the ISL8487E
and ISL81487L include a shutdown feature that reduces
the already low quiescent ICC to a 500nA trickle. They
enter shutdown whenever the receiver and driver are
simultaneously disabled (RE = VCC and DE = GND) for a
period of at least 600ns. Disabling both the driver and the
receiver for less than 50ns guarantees that shutdown is not
entered.
Note that receiver and driver enable times increase when
enabling from shutdown. Refer to Notes 5-9, at the end of
the Electrical Specification table, for more information.
ESD Protection
All pins on these interface devices include class 3 Human
Body Model (HBM) ESD protection structures, but the
RS-485 pins (driver outputs and receiver inputs)
incorporate advanced structures allowing them to survive
ESD events in excess of ±15kV HBM. The RS-485 pins are
particularly vulnerable to ESD damage because they
typically connect to an exposed port on the exterior of the
finished product. Simply touching the port pins, or
connecting a cable, can cause an ESD event that might
destroy unprotected ICs. These new ESD structures
protect the device whether or not it is powered up, protect
without allowing any latchup mechanism to activate, and
without degrading the RS-485 common mode range of -7V
to +12V. This built-in ESD protection eliminates the need
for board level protection structures (e.g., transient
suppression diodes), and the associated, undesirable
capacitive load they present.
Built-In Driver Overload Protection
As stated previously, the RS-485 spec requires that drivers
survive worst case bus contentions undamaged. These
devices meet this requirement via driver output short circuit
current limits, and on-chip thermal shutdown circuitry.
9
FN6051.7
February 27, 2006
ISL8487E, ISL81487L, ISL81487E
Human Body Model Testing
As the name implies, this test method emulates the ESD
event delivered to an IC during human handling. The tester
delivers the charge stored on a 100pF capacitor through a
1.5kΩ current limiting resistor into the pin under test. The
The RS-485 pin survivability on this high ESD family has
been characterized to be in excess of ±15kV, for discharges
to GND.
VCC = 5V, TA = 25°C, ISL8487E, ISL81487L and ISL81487E;
Unless Otherwise Specified
90
3.6
80
3.4
DIFFERENTIAL OUTPUT VOLTAGE (V)
DRIVER OUTPUT CURRENT (mA)
Typical Performance Curves
HBM method determines an IC’s ability to withstand the ESD
events typically present during handling and manufacturing.
70
60
50
40
30
20
10
0
0
1
2
3
4
3.2
RDIFF = 100Ω
3
2.8
2.6
2.4
RDIFF = 54Ω
2.2
2
-40
5
-25
DIFFERENTIAL OUTPUT VOLTAGE (V)
FIGURE 6. DRIVER OUTPUT CURRENT vs DIFFERENTIAL
OUTPUT VOLTAGE
25
50
75
85
FIGURE 7. DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs
TEMPERATURE
400
160
ISL81487E, DE = VCC, RE = X
140
ISL81487E
120
350
Y OR Z = LOW
100
80
ISL81487E, DE = GND, RE = X
ISL8487E, ISL81487L
300
60
40
ICC (µA)
OUTPUT CURRENT (mA)
0
TEMPERATURE (°C)
20
0
-20
200
Y OR Z = HIGH
-40
250
ISL8487E, ISL81487L, DE = VCC, RE = X
-60
ISL81487E
-80 ISL8487E, ISL81487L
-100
150
-120
100
-40
-7 -6
-4
-2
0
2
4
6
OUTPUT VOLTAGE (V)
ISL8487E, ISL81487L, DE = GND, RE = GND
8
10
12
FIGURE 8. DRIVER OUTPUT CURRENT vs SHORT CIRCUIT
VOLTAGE
10
-25
0
25
TEMPERATURE (°C)
50
75
85
FIGURE 9. SUPPLY CURRENT vs TEMPERATURE
FN6051.7
February 27, 2006
ISL8487E, ISL81487L, ISL81487E
Typical Performance Curves
VCC = 5V, TA = 25°C, ISL8487E, ISL81487L and ISL81487E;
Unless Otherwise Specified (Continued)
250
750
200
tPLHY
tPLHZ
650
|tPLHY - tPHLZ|
150
600
SKEW (ns)
PROPAGATION DELAY (ns)
700
tPHLY
550
tPHLZ
|tPHLY - tPLHZ|
100
50
500
|CROSS PT. OF Y↑ & Z↓ - CROSS PT. OF Y↓ & Z↑|
450
-40
-25
0
25
TEMPERATURE (°C)
50
0
-40
85
75
FIGURE 10. DRIVER PROPAGATION DELAY vs
TEMPERATURE (ISL8487E, ISL81487L)
-25
0
25
TEMPERATURE (°C)
50
85
75
FIGURE 11. DRIVER SKEW vs TEMPERATURE
(ISL8487E, ISL81487L)
30
5
4
|tPHLY - tPLHZ|
26
3
24
tPLHY
22
tPHLZ
tPLHZ
20
|tPLHY - tPHLZ|
SKEW (ns)
2
1
18
|CROSSING PT. OF Y↑ & Z↓ - CROSSING PT. OF Y↓ & Z↑|
tPHLY
16
-40
-25
0
25
50
0
-40
85
75
-25
TEMPERATURE (°C)
RO
0
5
RO
0
ISL81487L
ISL8487E
4
3
2
RECEIVER OUTPUT (V)
5
0
DRIVER INPUT (V)
5
RDIFF = 54Ω, CL = 100pF
B/Z
A/Y
1
0
TIME (400ns/DIV)
FIGURE 14. DRIVER AND RECEIVER WAVEFORMS,
LOW TO HIGH (ISL8487E, ISL81487L)
11
25
50
85
75
FIGURE 13. DRIVER SKEW vs TEMPERATURE
(ISL81487E)
DRIVER OUTPUT (V)
DRIVER OUTPUT (V)
RECEIVER OUTPUT (V)
FIGURE 12. DRIVER PROPAGATION DELAY vs
TEMPERATURE (ISL81487E)
DI
0
TEMPERATURE (°C)
RDIFF = 54Ω, CL = 100pF
DI
5
RO
0
5
RO
0
ISL81487L
5
0
DRIVER INPUT (V)
PROPAGATION DELAY (ns)
28
ISL8487E
4
3
2
A/Y
B/Z
1
0
TIME (400ns/DIV)
FIGURE 15. DRIVER AND RECEIVER WAVEFORMS,
HIGH TO LOW (ISL8487E, ISL81487L)
FN6051.7
February 27, 2006
ISL8487E, ISL81487L, ISL81487E
0
5
RO
0
4
3
2
B/Z
A/Y
1
0
TIME (20ns/DIV)
FIGURE 16. DRIVER AND RECEIVER WAVEFORMS,
LOW TO HIGH (ISL81487E)
RDIFF = 54Ω, CL = 100pF
DI
5
0
5
RO
0
DRIVER INPUT (V)
DI
5
RECEIVER OUTPUT (V)
RDIFF = 54Ω, CL = 100pF
DRIVER INPUT (V)
VCC = 5V, TA = 25°C, ISL8487E, ISL81487L and ISL81487E;
Unless Otherwise Specified (Continued)
DRIVER OUTPUT (V)
DRIVER OUTPUT (V)
RECEIVER OUTPUT (V)
Typical Performance Curves
4
3
2
A/Y
B/Z
1
0
TIME (20ns/DIV)
FIGURE 17. DRIVER AND RECEIVER WAVEFORMS,
HIGH TO LOW (ISL81487E)
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
518
PROCESS:
Si Gate CMOS
12
FN6051.7
February 27, 2006
ISL8487E, ISL81487L, ISL81487E
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
N
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AD
E
BASE
PLANE
-C-
SEATING
PLANE
A2
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8, 10
eA
C
0.008
0.014
0.204
C
D
0.355
0.400
9.01
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
e
0.100 BSC
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
eA
0.300 BSC
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
eB
-
L
0.115
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
N
8
0.355
10.16
5
2.54 BSC
-
7.62 BSC
6
0.430
-
0.150
2.93
10.92
3.81
8
7
4
9
Rev. 0 12/93
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
13
FN6051.7
February 27, 2006
ISL8487E, ISL81487L, ISL81487E
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
INDEX
AREA
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
B S
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
N
α
NOTES:
MILLIMETERS
8
0°
1.27
8
8°
0°
6
7
8°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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14
FN6051.7
February 27, 2006
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