High -P erf or manc e Dr BL AD E 5 mm x 5 mm x 0.6 mm IQFN TD A21 310 Dat a She et Revision 2.1, 2013-09-05 Po wer Ma nage m ent and M ulti M ark e t Edition 2013-09-05 Published by Infineon Technologies AG 81726 Munich, Germany © 2013 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). 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TDA21310 Revision History Page or Item Subjects (major changes since previous revision) Revision 2.1 2013-09-05 Temperature Rise diagram added Trademarks of Infineon Technologies AG AURIX™, BlueMoon™, C166™, CanPAK™, CIPOS™, CIPURSE™, COMNEON™, EconoPACK™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SMARTi™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™, X-GOLD™, X-PMU™, XMM™, XPOSYS™. Other Trademarks Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. 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TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2010-10-26 Data Sheet 3 Revision 2.1, 2013-09-05 TDA21310 Applications 1 Applications Desktop and Server buck-converter Single Phase and Multiphase POL CPU/GPU Regulation in Desktop Graphics Cards, DDR Memory, Graphic Memory High Power Density Voltage Regulator Modules (VRM). 2 Features ® Compatible to Intel VR12 Driver and Mosfets Module (DrMOS) functionality for Desktop/Server Applications For synchronous buck converter step down voltage applications Power MOSFETs rated 25 V for safe operation under all conditions Fast switching technology for improved performance at high switching frequencies (> 1 MHz) +5 V high side and low side MOSFETs driving voltage Compatible to standard +3.3 V PWM controller integrated circuits Small package: LG-UIQFN-32-2 (5 x 5 x 0.6 mm³) Optimized footprint for improved cooling by the PCB DC output current up to 40A 1 94% peak efficiency at 1.2V DC input voltage up to +16 V Remote driver disable function Includes bootstrap diode Undervoltage lockout Shoot through protection Tri-state PWM input functionality Top side cooling RoHS compliant Table 1 Product Identification Part Number Temp Range Package Marking TDA21310 -25 C to 125 C LG-UIQFN-32-2 (5 x 5 x 0.6 mm³) TDA21310 Figure 1 1 Picture of the Product Typical power stage efficiency, VIN=12V, VDRV=VCIN=5V, fSW=300kHz, L=210nH, 0.2mΩ, no air flow, no heat sink. Data Sheet 4 Revision 2.1, 2013-09-05 TDA21310 DR_EN PWM NC NC CGND Pin #4 Pin #3 Pin #2 Pin #1 Pin #8 VIN Pin #5 Pinout BOOT 3.1 Pin #6 Description VIN 3 Pin #7 PHASE Description Pin #9 Pin #32 VCIN VIN Pin #10 VIN Pin #11 Pin #30 PGND VSWH Pin #12 Pin #29 VSWH PGND Pin #13 Pin #28 VSWH PGND Pin #14 Figure 2 Table 2 Pin #31 VDRV VIN Pin #20 Pin #21 Pin #22 Pin #23 Pin #24 PGND PGND PGND PGND Pin #19 PGND PGND Pin #18 Pin #25 VSWH PGND PGND Pin #16 Pin #17 Pin #26 VSWH PGND PGND Pin #15 Pinout, numbering and name of pins (transparent top view) I/O Signals Pin No. Name Pin Type Buffer Type Function 4 PWM I +3.3 V logic 5 DR_EN I +3.3 V logic 6 BOOT I Analog 7 PHASE I Analog 12, 25 to 29, VSWH pad VSWH O Analog Data Sheet Pin #27 VSWH VSWH PWM drive logic input The tri-state PWM input is compatible with 3.3 V. Enable signal (active high) Connect to GND to disable the IC. Bootstrap voltage pin Connect to BOOT capacitor Switch node (reference for Boot voltage) internally connected to VSWH pin, connect to BOOT capacitor Switch node output High current output switching node 5 Revision 2.1, 2013-09-05 TDA21310 Description Table 3 Power Supply Pin No. Name Pin Type Buffer Type Function 8 to 11, VIN pad VIN POWER – 31 VDRV POWER – 32 VCIN POWER – Table 4 Input voltage Supply of the drain of the high side MOSFET FET gate supply voltage High and low side MOSFETs gate drive supply Logic supply voltage 5 V bias voltage for the internal logic Ground Pins Pin No. Name Pin Type Buffer Type Function 1 CGND GND – 13 to 24, 30 PGND GND – Table 5 Control signal ground Should be connected to PGND externally Power ground All these pins must be connected to the power GND plane through multiple low inductance vias. Not Connected Pin No. Name Pin Type Buffer Type Function 2, 3 NC – Data Sheet – No internal connection Leave pin floating or tie to GND. 6 Revision 2.1, 2013-09-05 TDA21310 Description 3.2 General Description The Infineon TDA21310 is a multichip module that incorporates Infineon’s premier MOSFET technology for a single high side and a single low side MOSFET coupled with a robust, high performance, high switching frequency gate driver in a single 32 pin LG-UIQFN-32-2 package. The optimized gate timing allows for significant light load efficiency improvements over discrete solutions. State of the art MOSFET technology provides exceptional full load performance. When combined with Infineon’s family of digital multi-phase controllers, the TDA21310 forms a complete corevoltage regulator solution for advanced micro and graphics processors as well as point-of-load applications. The TDA21310 is not pin compatible to the Intel 6x6 DrMOS specification, but compatible by functionality. The device package height is only 0.6 mm, and is an excellent choice for applications with critical height limitations. It has reduced thermal impedance from junction to top case compared to DrMOS, allowing for top side cooling. PHASE VCIN BOOT DRIVER IC HS Driver HS MOSFET GH Level Shifter UVLO VIN 10k VDRV DR_EN 500k HS Logic CGND Shoot Through Protection Unit + - VCIN 16k5 PWM 7k1 VSWH + Input Logic TriState - LS MOSFET VDRV CGND GL LS Logic LS Driver 10k PGND CGND Figure 3 VDRV Simplified Block Diagram Attention: GH and GL are not accessible. They are mentioned for clarity in this block diagram. Data Sheet 7 Revision 2.1, 2013-09-05 TDA21310 Electrical Specification 4 Electrical Specification 4.1 Absolute Maximum Ratings Note: TA = 25°C Stresses above those listed in Table 6 “Absolute Maximum Ratings” may cause permanent damage to the device. These are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational sections of this specification. Exposure over values of the recommended ratings (Table 8) for extended periods may adversely affect the operation and reliability of the device. Table 6 Absolute Maximum Ratings Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Frequency of the PWM input fSW – – 1.2 MHz – Maximum DC load current IOUT – – 40 A – Input Voltage VIN (DC) -0.30 – 16 V Logic supply voltage VCIN (DC) -0.30 – 6.5 – High and Low side driver voltage VDRV (DC) -0.30 – 6.5 – Switch node voltage VSWH (DC) -1 – 16 – -10 – 25 – VPHASE (DC) -1 – 16 – VPHASE (AC) -10 – 25 – VBOOT (DC) -0.3 2 VSWH (AC) PHASE node voltage BOOT voltage – 22.5 – VBOOT (AC) 2 -1 – 31.5 – VBOOT-PHASE (DC) -1 – 6.5 – DR_EN voltage VDR_EN -0.3 – 5.5 – PWM voltage VPWM -0.3 – 5.5 – Junction temperature TJmax -40 – 150 Storage temperature TSTG -55 – 150 C – – Note: All rated voltages are relative to voltages on the CGND and PGND pins unless otherwise specified. 2 AC is limited to 10 ns Data Sheet 8 Revision 2.1, 2013-09-05 TDA21310 Electrical Specification 4.2 Table 7 Thermal Characteristics Thermal Characteristics Parameter Symbol Values Unit Note / Test Condition K/W – Min. Typ. Thermal resistance between driver junction and soldering point3 Thermal resistance between driver junction and top of package Thermal resistance between high-side MOSFET junction and soldering point3 θJS-driver – 29 – θJtop-driver – 14 – – θJS-HS – 2 – – Thermal resistance between high-side MOSFET junction and top of package Thermal resistance between low-side MOSFET junction and soldering point3 Thermal resistance between low-side MOSFET junction and top of package Thermal resistance between driver junction and high-side MOSFET junction Thermal resistance between driver junction and low-side MOSFET junction θJtop-HS – 7 – – θJS-LS – 1 – – θJtop-LS – 2 – – θJJ-driver-HS – 40 – θJJ-driver-LS – 60 – – 36 – θJJ-LS-HS Thermal resistance between low-side MOSFET junction and high-side MOSFET junction 4.3 Max. Recommended Operating Conditions and Electrical Characteristics Note: VDRV = VCIN = 5 V, TA = 25°C Table 8 Recommended Operating Conditions Parameter 3 Symbol Values Min. Typ. Max. 5 – 16 Unit Note / Test Condition V – Input voltage VIN MOSFET driver voltage VDRV 4.5 5 6 – Logic supply voltage VCIN 4.5 5 6 VCIN rising,3.3V to 3.9V: dvCIN/dt > 300V/s Junction temperature TjOP -25 – 125 °C – The junction-soldering point is referred to the bottom exposed pad. Data Sheet 9 Revision 2.1, 2013-09-05 TDA21310 Electrical Specification Table 9 Voltage Supply And Biasing Current Parameter Symbol Values Min. Typ. Max. Note / Test Condition V VCIN rising,3.3V to 3.9V: dvCIN/dt > 300V/s VCIN falling mA DR_EN = 3.3V, fSW = 300 kHz UVLO rising VUVLO_R – 3.5 – UVLO falling VUVLO_F – 3.1 – Driver current IVDRV_300kHz – 12 – IVDRV_1MHz – 38 – IVDRV_PWML – 25 – IVDRV_PWMH – 12 – DR_EN = 0V, PWM = 3.3V IVCIN_PWML – 400 – IVCIN_O – 500 – DR_EN = 3.3 V, PWM = 0V DR_EN = 3.3 V, PWM = Open ICIN+IDRV – – 550 IC current (control) IC quiescent Table 10 Symbol PWM μA Values Min. DR_EN DR_EN = 3.3V, fSW = 1 MHz DR_EN = 3.3V, PWM = 0V DR_EN = 0 V Logic Inputs And Threshold Parameter 4 Unit Typ. Unit Note / Test Condition V VDR_EN falling Max. Input low VDR_EN_L 0.7 1.1 1.3 Input high VDR_EN_H 1.9 2.1 2.4 Sink current IDR_EN – 2 – μA VDR_EN = 1 V Input low VPWM_L – – 0.7 V VPWM falling Input high VPWM_H 2.4 – – Input resistance RIN-PWM 3 5 7 k VPWM = 1 V Open voltage VPWM_O – 1.5 – V VPWM_O Tri-state shutdown 4 window VPWM_S 1.2 – 1.9 VDR_EN rising VPWM rising – Maximum voltage range for tri-state Data Sheet 10 Revision 2.1, 2013-09-05 TDA21310 Theory of Operation Table 11 Timing Characteristics Parameter Symbol Values Min. Typ. Unit Max. PWM tri-state to VSWH rising delay or VSWH falling delay t_pts – 15 – VSWH Shutdown Hold-Off time t_tsshd – 150 – PWM to VSWH turn-off propagation delay t_pdlu – 20 – PWM to VSWH turn-on propagation delay DR_EN turn-off propagation delay falling DR_EN turn-on propagation delay rising PWM minimum pulse width t_pdll – 20 – t_pdl_DR_EN – 20 – t_pdh_DR_EN – 20 – ton_min_PWM – 25 – PWM minimum off time toff_min_PWM – 100 – 5 Note / Test Condition ns Theory of Operation The TDA21310 incorporates a high performance gate driver, one high-side power MOSFET and one low-side power MOSFET in a single 32 pin LG-UIQFN-32-2 package. The advantages of this arrangement are found in the areas of increased performance, increased efficiency and lower overall package and layout inductance. This module is ideal for use in Synchronous Buck Regulators. The power MOSFETs are optimized for 5 V gate drive enabling excellent high load and light load efficiency. The gate driver is a robust high-performance driver rated at the switching node for DC voltages ranging from -1 V to +16 V. The power density for transmitted power in a multiphase regulator of this approach can easily be higher 2 than 40 W per phase within a 25 mm area. 5.1 Driver Characteristics The gate driver of the TDA21310 has two input voltages, VCIN and VDRV. VCIN is the 5 V logic supply for the driver. VDRV sets the driving voltage for the high side and low side MOSFETs. The reference for the gate driver control circuit (VCIN) is CGND. To decouple the sensitive control circuitry (logic supply) from a noisy environment a ceramic capacitor must be placed between VCIN and CGND close to the pins. VDRV needs also to be decoupled using a ceramic capacitor (MLCC) between VDRV and PGND in close proximity to the pins. PGND serves as reference for the power circuitry including the driver output stage. Referring to the Block Diagram page 7, VCIN is internally connected to the UVLO circuit. It will force shut-down for insufficient VCIN voltage. VDRV supplies the floating high-side drive – consisting of an active boot circuit and the low-side drive circuit. A second UVLO circuitry, sensing the BOOT voltage level, is implemented to prevent false GH turn on during insufficient power supply level condition (BOOT cap charging/discharging sequence). During undervoltage both GH and GL are driven low actively; further passive pull-down (10 k) is placed across gate-source of both FETs. Data Sheet 11 Revision 2.1, 2013-09-05 TDA21310 Theory of Operation UVLO Output Logic Level “H” Enable Shutdown “L” VUVLO_F Figure 4 5.2 VUVLO_R VCIN Internal Output Signal from UVLO Unit Inputs to the Internal Control Circuits The PWM is the control input to the IC from an external PWM controller and is compatible with 3.3 V. The PWM input has tri-state functionality. When the voltage remains in the specified PWM-shutdown-window for at least the PWM-shutdown-holdoff time t_tsshd, the operation will be suspended by keeping both MOSFET gate outputs low. Once left open, the pin is held internally at a level of VPWM_O = 1.5 V level. Table 12 PWM Pin Functionality PWM logic level Driver output Low GL= High, GH = Low High GL = Low, GH = High Open (left floating, or high impedance) GL = Low, GH = Low Using a wide range VCIN power supply (from 4.5 V to 6 V) causes a shifting in the threshold voltages for the following parameters: VPMW_O, VPWM_H, VPWM_L. The typical behavior of these thresholds over VCIN voltage variation is shown in the following graph. Data Sheet 12 Revision 2.1, 2013-09-05 TDA21310 Theory of Operation Figure 5 Variation of PWM levels versus VCIN logic supply voltage Attention: The VPWM_S is also temperature dependent. VCIN requires a minimum dv/dt of 300V/s in the vicinity of the UVLO threshold to prevent the driver logic from emitting any gate drive glitches. The DR_EN is an active high signal. When DR_EN is pulled low, the power stage is disabled. Table 13 DR_EN Pin Functionality DR_EN logic level Driver output Low Shutdown : GL = GH = Low High Enable : GL = GH = Active Open (left floating, or high impedance) Shutdown : GL = GH = Low 5.3 Shoot Through Protection The TDA21310 driver includes gate drive functionality to protect against shoot through. In order to protect the power stage from overlap, both high-side and low-side MOSFETs being on at the same time, the adaptive control circuitry monitors specific voltages. When the PWM signal transitions to low, the high-side MOSFET will begin to turn off after the propagation delay time t_pdlu. When VGS of the high-side MOSFET is discharged below 1 V (a threshold below which the high-side MOSFET is off), a secondary delay t_pdhl is initiated. After that delay the low-side MOSFET turns on regardless of the state of the “VSWH” pin. It ensures that the converter can sink current efficiently and the bootstrap capacitor will be refreshed appropriately during each switching cycle. See Figure 8 for more detail. Data Sheet 13 Revision 2.1, 2013-09-05 TDA21310 Application CBOOT PWM 8 CIN 4x10 µF 7 6 PWM DR_EN VIN (4.5V - 16V) BOOT VIN PHASE 470 nF 5 4 3 2 1 µF 1 32 9 31 10 VIN 30 VIN 11 VSWH 12 29 13 28 PGND 14 26 16 25 19 20 21 +5V 1 µF PGND VSWH 15 18 VDRV 27 VSWH 17 VCIN 1Ω Implementation CGND 6.1 NC Application NC 6 22 23 L VOUT 24 COUT PGND Figure 6 Pin interconnection outline (transparent top view) Note: 1. Pin PHASE is internally connected to VSWH node 2. It is recommended to place a RC filter between VCIN and VDRV as shown. 3. During power-up and down sequences, the PWM signal must be either low or tri-state (open voltage), but never high, in order to avoid uncontrolled output voltage. Data Sheet 14 Revision 2.1, 2013-09-05 TDA21310 Application 6.2 Figure 7 Data Sheet Typical Application Four-phase voltage regulator - typical application (simplified schematic) 15 Revision 2.1, 2013-09-05 TDA21310 Gate Driver Timing Diagram 7 Gate Driver Timing Diagram VPWM_H VPWM_H VPWM_H Tri-State PWM VPWM_L t_pdll VPWM_L t_pdlu t_tsshd t_pts t_tssh d t_pts VSWH Note: VSWH during entering/exiting tri-state behaves dependend on inductor current. Figure 8 Adaptive gate driver timing diagram Active VDR_EN_H Active DR_EN Deactivated VDR_EN_L t_pdh(DR_EN) t_pdl(DR_EN) VSWH Figure 9 Data Sheet DR_EN timing diagram (PWM is assumed “high”) 16 Revision 2.1, 2013-09-05 TDA21310 Performance Curves – Typical Data 8 Performance Curves – Typical Data Operating conditions (unless otherwise specified): VIN = +12 V, VCIN = VDRV = +5 V, LOUT=150nH (Cooper, FPI0906R1-R15, DCR = 0.29 mΩ) inductor, TA = 25 °C, airflow = 300 LFM, no heatsink. Efficiency and power loss reported herein include only TDA21310 losses. 8.1 Figure 10 Data Sheet Temperature Rise Temperature Rise over Output Current 17 Revision 2.1, 2013-09-05 TDA21310 Performance Curves – Typical Data 8.2 Figure 11 Data Sheet Driver Current versus Switchig Frequency Driver Current over Switching Frequency in CCM Operation 18 Revision 2.1, 2013-09-05 TDA21310 Performance Curves – Typical Data 8.3 Efficiency and Power Loss versus Switching Frequency Figure 12 Efficiency at VIN = 12 V, VCIN = VDRV = 5 V, VOUT = 1.82 V, Parameter: fSW Figure 13 Power Loss at VIN = 12 V, VCIN = VDRV = 5 V, VOUT = 1.82 V, Parameter: fSW Data Sheet 19 Revision 2.1, 2013-09-05 TDA21310 Performance Curves – Typical Data Figure 14 Efficiency at VIN = 12 V, VCIN = VDRV = 5 V, VOUT = 1.218 V, Parameter: fSW Figure 15 Power Loss at VIN = 12 V, VCIN = VDRV = 5 V, VOUT = 1.218 V, Parameter: fSW Data Sheet 20 Revision 2.1, 2013-09-05 TDA21310 Mechanical Drawing LG-UIQFN-32-2 9 Figure 16 Data Sheet Mechanical Drawing LG-UIQFN-32-2 Mechanical dimensions 21 Revision 2.1, 2013-09-05 TDA21310 Mechanical Drawing LG-UIQFN-32-2 Figure 17 Data Sheet Stencil dimensions (in mm) 22 Revision 2.1, 2013-09-05 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG