5962-8754903VCA

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
A
Change AC limits in table I. Add vendor CAGE 18714 to device type 01CX.
Editorial changes throughout.
87-11-16
R. R. Evans
B
Changes in accordance with NOR 5962-R100-93.
93-03-23
Monica L. Poelking
C
Changes in accordance with NOR 5962-R181-93.
93-06-25
Monica L. Poelking
D
Add vendor CAGE F8859. Add device Class V criteria. Add delta limits, table III.
Add case outline X. Update boilerplate to MIL-PRF-38535 requirements. – lgt
01-03-23
Raymond Monnin
E
Add section 1.5, radiation features. Update the boilerplate to include radiation
hardness assured requirements. Editorial changes throughout. - TVN
03-10-01
Thomas M. Hess
F
Add appendix A, microcircuit die. Update the boilerplate to MIL-PRF-38535
requirements and to include radiation hardness assurance requirements.
Editorial changes throughout. - jak
07-02-16
Thomas M. Hess
G
Add new device type 03 with V class criteria. Update the boilerplate to current
MIL-PRF-38535 requirements. - MAA
08-11-24
Thomas M. Hess
H
Add RHA device type 03. Add radiations features for device type 03 in section
1.5. Update footnote 3/ to table IA. Update boilerplate paragraphs to current
MIL-PRF-38535 requirements - MAA
13-12-12
Thomas M. Hess
J
Add die for device type 03 and die layout figure A-2 to appendix A. - MAA
15-01-06
Thomas M. Hess
K
Add SEL and SEU radiation features for device type 03 in section 1.5 and
SEP table IB. – MAA
15-04-13
Thomas M. Hess
CURRENT CAGE CODE 67268
REV
SHEET
REV
K
K
K
K
K
K
K
K
K
K
K
SHEET
15
16
17
18
19
20
21
22
23
24
25
REV
K
K
K
K
K
K
K
K
K
K
K
K
K
K
SHEET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
REV STATUS
OF SHEETS
PMIC N/A
PREPARED BY
Greg A. Pitz
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS AVAILABLE
FOR USE BY ALL DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil/
CHECKED BY
N. A. Hauck
APPROVED BY
N. A. Hauck
DRAWING APPROVAL DATE
87-04-29
REVISION LEVEL
AMSC N/A
DSCC FORM 2233
APR 97
MICROCIRCUIT, DIGITAL, ADVANCED CMOS,
RADIATION HARDENED, QUAD 2-INPUT NAND
GATE, MONOLITHIC SILICON
K
SIZE
CAGE CODE
A
14933
SHEET
5962-87549
1 OF 25
5962-E219-15
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and
M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part
or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
For device classes M and Q:
5962
-
Federal
stock class
designator
\
87549
RHA
designator
(see 1.2.1)
01
C
A
Device
type
(see 1.2.2)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
For device class V:
5962
F
Federal
stock class
designator
\
87549
RHA
designator
(see 1.2.1)
01
Device
type
(see 1.2.2)
/
V
X
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
A
Lead
finish
(see 1.2.5)
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
Circuit function
01
54AC00
Quad 2-input NAND gate
02
54AC11000
Quad 2-input NAND gate
03
54AC00-SP
Quad 2-input NAND gate
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as listed
below. Since the device class designator has been added after the original issuance of this drawing, device classes M and Q
designators will not be included in the PIN and will not be marked on the device.
Device class
M
Q or V
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
Device requirements documentation
Vendor self-certification to the requirements for MIL-STD-883 compliant,
non-JAN class level B microcircuits in accordance with MIL-PRF-38535,
appendix A
Certification and qualification to MIL-PRF-38535
SIZE
5962-87549
A
REVISION LEVEL
K
SHEET
2
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
C
D
E
F
2
X
Descriptive designator
GDIP1-T14 or CDIP2-T14
GDFP1-F14 or CDFP2-F14
GDIP1-T16 or CDIP2-T16
GDFP2-F16 or CDFP3-F16
CQCC1-N20
CDFP3-F14
Terminals
Package style
14
14
16
16
20
14
Dual-in-line
Flat pack
Dual-in-line
Flat pack
Square leadless chip carrier
Flat pack
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
1.3 Absolute maximum ratings. 1/ 2/ 3/
Supply voltage range (VCC) .................................................................................. -0.5 V dc to +7.0 V dc
DC input voltage range (VIN) ................................................................................ -0.5 V dc to VCC + 0.5 V dc
DC output voltage range (VOUT) ........................................................................... -0.5 V dc to VCC + 0.5 V dc
Clamp diode current (IIK, IOK) ............................................................................... ±20 mA
DC output current ................................................................................................ ±50 mA
DC VCC or GND current (per pin) ......................................................................... ±50 mA
Storage temperature range (TSTG) ....................................................................... -65°C to +150°C
Maximum power dissipation (PD) ........................................................................ 500 mW
Lead temperature (soldering, 10 seconds) .......................................................... +260°C
Thermal resistance, junction-to-case (θJC) ........................................................... See MIL-STD-1835
Junction temperature (TJ) ................................................................................... +175°C 4/
1.4 Recommended operating conditions. 2/ 3/ 5/ 6/
Supply voltage range (VCC) .................................................................................. +2.0 V dc to +6.0 V dc
Input voltage range (VIN) ...................................................................................... +0.0 V dc to VCC
Output voltage range (VOUT)................................................................................. +0.0 V dc to VCC
Case operating temperature range (TC) ............................................................... -55°C to +125°C
Minimum input rise or fall rate (∆t/∆V):
Device type 01and 03 ...................................................................................... 0 to 8 ns/V
Device type 02 ................................................................................................. 0 to 10 ns/V
1.5 Radiation features.
For Device type 01:
Maximum total dose available (dose rate = 50 – 300 rads (Si)/s) .................... 300 krads (Si)
2
No Single Event Latchup (SEL) occurs at effective LET (see 4.4.4.2) ............. ≤ 93 MeV-cm /mg
2
No Single Event Upset (SEU) occurs at effective LET (see 4.4.4.2)................ ≤ 93 MeV-cm /mg
For Device type 03:
Maximum total dose available (dose rate = 50 – 300 rads (Si)/s) .................... 100 krads (Si)
2
No Single Event Latchup (SEL) occurs at effective LET (see 4.4.4.2) ............. ≤ 85 MeV-cm /mg
2
No Single Event Upset (SEU) occurs at effective LET (see 4.4.4.2)................ ≤ 85 MeV-cm /mg
1/
2/
3/
4/
5/
6/
7/
7/
7/
7/
7/
Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
Unless otherwise noted, all voltages are referenced to GND.
The limits for the parameters specified herein shall apply over the full specified VCC range and case temperature range of
-55°C to +125°C.
Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in
accordance with method 5004 of MIL-STD-883.
Operation from 2.0 V dc to 3.0 V dc is provided for compatibility with data retention and battery back-up systems. Data
retention implies no input transition and no stored data loss with the following conditions: VIH ≥ 70% VCC, VIL ≤ 30% VCC,
VOH ≥ 70% VCC at -20µA, VOL ≤ 30% VCC at 20 µA.
Unused inputs must be held high or low to prevent them from floating.
Limits are guaranteed by design or process, but not production tested unless specified by the customer through the
purchase order or contract.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-87549
A
REVISION LEVEL
K
SHEET
3
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://quicksearch.dla.mil/ or from the Standardization Document Order
Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract.
JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)
EIA/JEDEC Standard JESD78 - IC Latch-up Test
JEDEC Standard JESD20 - Standard for Description of 54/74ACXXXX and 54/74ACTXXXX Advanced HighSpeed CMOS Devices.
(Copies of these documents are available online at http://www.jedec.org or from JEDEC – Solid State Technology Association,
3103 North 10th Street, Suite 240–S, Arlington, VA 22201.)
ASTM INTERNATIONAL (ASTM)
ASTM F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion
Irradiation of semiconductor Devices.
(Copies of these documents are available online at http://www.astm.org or from ASTM International, 100 Barr Harbor Drive,
P.O. Box C700, West Conshohocken, PA, 19428-2959).
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-87549
A
REVISION LEVEL
K
SHEET
4
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.1.1 Microcircuit die. For the requirements of microcircuit die, see appendix A to this document.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Truth table. The truth table shall be as specified on figure 2.
3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3.
3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4.
3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document
revision level control and shall be made available to the preparing or acquiring activity upon request.
3.3 Electrical performance characteristics and pos-irradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and pos-irradiation parameter limits are as specified in table IA and shall apply over the
full case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table IA.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime-VA, prior to listing as an approved source of
supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MILPRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DLA Land and Maritime-VA, of change of
product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DLA Land and Maritime, DLA Land and Maritime's agent,
and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore
documentation shall be made available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 36 (see MIL-PRF-38535, appendix A).
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-87549
A
REVISION LEVEL
K
SHEET
5
TABLE IA. Electrical performance characteristics.
Test and
MIL-STD-883
test method 1/
Symbol
Test conditions 2/ 3/
-55°C ≤ TC ≤ +125°C
+3.0 V ≤ VCC ≤ +5.5 V
Unless otherwise specified
Device type
and
Device class
VCC
Group A
subgroups
Limits 4/
Unit
Min
Max
Positive input
clamp voltage
3022
VIC+
For input under test,
IIN = 1.0 mA
All
Q, V
0.0 V
1
0.4
1.5
V
Negative input
clamp voltage
3022
VIC-
For input under test,
IIN = -1.0 mA
All
Q, V
Open
1
-0.4
-1.5
V
High level output
voltage
3006
VOH
5/
VIN = VIH minimum or
VIL maximum
IOH = -50 µA
All
All
3.0 V
1, 2, 3
2.9
VIN = VIH minimum or
VIL maximum
IOH = -12 mA
All
All
3.0 V
VIN = VIH minimum or
VIL maximum
IOH = -24 mA
All
All
4.5 V
4.5 V
4.4
5.5 V
5.4
5.5 V
Low level output
voltage
3007
VOL
5/
V
1
2.56
2, 3
2.4
1
3.86
2, 3
3.7
1
4.86
2, 3
4.7
3.85
VIN = VIH minimum or
VIL maximum
IOH = -50 mA
All
All
5.5 V
1, 2, 3
VIN = VIH minimum or
VIL maximum
IOL =+50 µA
All
All
3.0 V
1, 2, 3
VIN = VIH minimum or
VIL maximum
IOL = +12 mA
All
All
3.0 V
VIN = VIH minimum or
VIL maximum
IOL = +24 mA
All
All
4.5 V
0.1
4.5 V
0.1
5.5 V
0.1
5.5 V
VIN = VIH minimum or
VIL maximum
IOL = +50 mA
High level input
voltage
Low level input
voltage
VIH
6/
VIL
6/
1
0.36
2, 3
0.5
1
0.36
2, 3
0.5
1
0.36
2, 3
0.5
1.65
All
All
5.5 V
1, 2, 3
All
All
3.0 V
1, 2, 3
All
All
2.1
V
4.5 V
3.15
5.5 V
3.85
3.0 V
V
1, 2, 3
0.9
4.5 V
1.35
5.5 V
1.65
V
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-87549
A
REVISION LEVEL
K
SHEET
6
TABLE IA. Electrical performance characteristics – Continued.
Test and
MIL-STD-883
test method 1/
Symbol
Input leakage
current low
3009
IIL
Input leakage
current high
3010
IIH
Quiescent supply
current, output
high
3005
ICCH
Test conditions 2/ 3/
-55°C ≤ TC ≤ +125°C
+3.0 V ≤ VCC ≤ +5.5 V
Unless otherwise specified
Device
type
and
Device
class
VCC
All
All
5.5 V
All
All
5.5 V
03
All
5.5 V
01, 02
All
5.5 V
VIN = 0.0 V
VIN = 5.5 V
VIN = VCC or GND
IOUT = 0 A
M, D, P, L, R, F
7/
Quiescent supply
current, output
low
3005
ICCL
Group A
subgroups
Min
M, D, P, L, R, F
7/
03
All
5.5 V
01, 02
All
5.5 V
Unit
Max
1
-0.1
2, 3
-1.0
1
0.1
2, 3
1.0
1
4.0
2, 3
40.0
1
2.0
2, 3
40
1
50
1
4.0
2, 3
40.0
1
2.0
2, 3
40
1
50
01,
Q, V
VIN = VCC or GND
IOUT = 0 A
Limits 4/
01,
Q, V
µA
µA
µA
µA
Input capacitance
3012
CIN
See 4.4.1c
TC = +25°C
All
All
5.0 V
4
10.0
pF
Power dissipation
capacitance
CPD
8/
See 4.4.1c
TC = +25°C, f = 1 MHz
All
All
5.0 V
4
88.0
pF
VIN = VIH or VIL
Verify output VOUT
See 4.4.1b
All
All
3.0 V
7, 8
L
H
5.5 V
7, 8
L
H
Functional test
3014
Propagation delay
time, mA or mB
to mY
3003
9/
tPHL
10/
CL = 50 pF minimum
RL = 500Ω
See figure 4
01, 03
All
3.0 V
02
All
01, 03
All
02
All
9
1.0
9.5
10, 11
1.0
11.0
9
1.0
9.8
10, 11
1.0
11.9
9
1.5
8.0
10, 11
1.0
8.5
9
1.0
6.5
10, 11
1.0
8.1
4.5 V
ns
See footnotes on next sheet.
TABLE IA. Electrical performance characteristics – Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-87549
A
REVISION LEVEL
K
SHEET
7
Test and
MIL-STD-883
test method 1/
Propagation delay
time, mA or mB
to mY
3003
Symbol
tPLH
10/
Test conditions 2/ 3/
-55°C ≤ TC ≤ +125°C
+3.0 V ≤ VCC ≤ +5.5 V
Unless otherwise specified
Device
type
and
Device
class
VCC
01, 03
All
3.0 V
CL = 50 pF minimum
RL = 500Ω
See figure 4
Group A
subgroups
02
All
01, 03
All
Unit
Min
Max
9
1.0
9.5
10, 11
1.0
11.0
9
1.0
9.8
10, 11
1.0
11.9
9
1.5
8.0
10, 11
1.0
8.5
9
1.0
6.5
10, 11
1.0
8.1
4.5 V
02
All
Limits 4/
ns
1/
For tests not listed in the referenced MIL-STD-883, [e.g. VIH, VIL], utilize the general test procedure under the conditions
listed herein.
2/
Each input/output, as applicable, shall be tested at the specified temperature, for the specified limits, to the tests in table I
herein. Output terminals not designated shall be high level logic, low level logic, or open, except as follows:
a. VIC (pos) tests, the GND terminal can be open. TC = +25°C.
b. VIC (neg) tests, the VCC terminal shall be open. TC = +25°C.
c. All ICC tests, the output terminal shall be open. When performing these tests, the current meter shall be placed in the
circuit such that all current flows through the meter.
3/ RHA device type 01 supplied to this drawing have been characterized through all levels M, D, P, L, R and F of irradiation.
However, device type 01 is only tested at the ‘F’ level. Pre and post irradiation values are identical unless otherwise specified
in table IA. When performing post irradiation electrical measurements for any RHA level TA = +25°C.
RHA device type 03 supplied to this drawing have been characterized through all levels M, D, P, L and R of irradiation.
However, device type 03 is only tested at the ‘R’ level. Pre and post irradiation values are identical unless otherwise
specified in table IA.
Pre and post irradiation values are identical unless otherwise specified in table IA. When performing post irradiation electrical
measurements for any RHA level, TA=+25°C.
4/
For negative and positive voltage and current values, the sign designates the potential difference in reference to GND and
the direction of current flow, respectively; and the absolute value of the magnitude, not the sign, is relative to the minimum
and maximum limits, as applicable, listed herein. All devices shall meet or exceed the limits specified in table I, as
applicable, at 3.0 V ≤ VCC ≤ 3.6 V and 4.5 V ≤ VCC ≤ 5.5 V.
5/
The VOH and VOL tests shall be tested at VCC = 3.0 V and 4.5 V. The VOH and VOL tests are guaranteed, if not tested, for
other values of VCC. Limits shown apply to operation at VCC = 3.3 V ±0.3 V and VCC = 5.0 V ±0.5 V. Tests with input current
at +50 mA or -50 mA are performed on only one input at a time with duration not to exceed 2 ms. Transmission driving
tests may be performed using VIN = VCC or GND. When VIN = VCC or GND is used, the test is guaranteed for
VIN = VIH minimum and VIL maximum.
6/
The VIH and VIL tests are not required if applied as forcing functions for VOH and VOL tests.
7/
The maximum limit for this parameter at 100 krads (Si) is 2 µA.
8/
Power dissipation capacitance (CPD) determines both the power consumption (PD) and dynamic current consumption (IS).
Where:
PD = (CPD + CL) (VCC x VCC) f + (ICC x VCC)
IS = (CPD + CL) VCC f + ICC
f is the frequency of the input signal and CL is the external output load capacitance.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-87549
A
REVISION LEVEL
K
SHEET
8
TABLE IA. Electrical performance characteristics – Continued.
9/
Tests shall be performed in sequence, attributes data only. Functional tests shall include the truth table and other logic
patterns used for fault detection. The test vectors used to verify the truth table shall, at a minimum, test all functions of each
input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth table
in figure 2 herein. Functional tests shall be performed in sequence as approved by the qualifying activity on qualified
devices. Allowable tolerances in accordance with MIL-STD-883 for the input voltage levels may be incorporated.
For
VOUT measurements, L ≤ 0.3VCC and H ≥ 0.7VCC.
10/ For propagation delay tests, all paths must be tested. AC limits at VCC = 5.5 V are equal to the limits at VCC = 4.5 V and
guaranteed by testing at VCC = 4.5 V. AC limits at VCC = 3.6 V are equal to limits at VCC = 3.0 V and guaranteed by testing
at VCC = 3.0 V. Minimum ac limits for VCC = 5.5 V are 1.0 ns and guaranteed by guard banding the VCC = 4.5 V minimum
limits to 1.5 ns.
TABLE IB. SEP test limits.
1/ 2/
Device
type
SEP
TC =
temperature
±10°C
Bias VCC
Effective LET
01
No SEL
+125°C
5.5 V
LET ≤ 93 MeV-cm /mg
01
No SEU
+25°C
3.6 V
LET ≤ 93 MeV-cm /mg
03
No SEL 3/
+125°C
4.5 V
LET ≤ 85 MeV-cm /mg
03
No SEU 3/
+25°C
2.0 V
LET ≤ 85 MeV-cm /mg
03
No SEU 3/
+125°C
4.5 V
LET ≤ 85 MeV-cm /mg
2
2
2
2
2
1/ For SEP test conditions, see 4.4.4.2 herein.
2/ Technology characterization and model verification supplemented by in-line data may be used in lieu of
end-of-line testing. Test plan must be approved by TRB and qualifying activity.
3/ Contact vendor for SEP test report for device type 03. New SEP testing must be negotiated prior to purchase
order for device type 03.
STANDARD
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Device types
Case
outlines
01 and 03
C, D, and X
Terminal
number
02
2
E and F
Terminal symbol
2
Terminal symbol
1
1A
NC
1A
NC
2
1B
1A
1Y
VCC
3
1Y
1B
2Y
2B
4
2A
1Y
GND
2A
5
2B
NC
GND
1B
6
2Y
2A
3Y
NC
7
GND
NC
4Y
1A
8
3Y
2B
4B
1Y
9
3A
2Y
4A
2Y
10
3B
GND
3B
GND
11
4Y
NC
3A
NC
12
4A
3Y
VCC
GND
13
4B
3A
VCC
3Y
14
VCC
3B
2B
4Y
15
---
NC
2A
4B
16
---
4Y
1B
NC
17
---
NC
---
4A
18
---
4A
---
3B
19
---
4B
---
3A
20
---
VCC
---
VCC
NC = No internal connection
FIGURE 1. Terminal connections.
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Inputs
Outputs
mA
mB
mY
L
L
H
H
L
H
L
H
H
H
H
L
H = High voltage level
L = Low voltage level
FIGURE 2. Truth table.
FIGURE 3. Logic diagram.
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NOTES:
1. When measuring tPLH and tPHL: VTEST = open.
2. CL = 50 pF or equivalent (includes probe and jig capacitance).
3. RL = 500Ω or equivalent.
4. Input signal from pulse generator: VIN = 0.0 V to VCC; PRR ≤ 1 MHz; ZO = 50Ω; tr ≤ 3.0 ns; tf ≤ 3.0 ns; tr and tf shall be
measured from 10% of VCC to 90% of VCC and from 90% of VCC to 10% of VCC, respectively; duty cycle = 50 percent.
5. Timing parameters shall be tested at a minimum input frequency of 1MHz.
6. The outputs are measured one at a time with one transition per measurement.
FIGURE 4. Switching waveforms and test circuit.
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4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a.
Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision
level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified
in method 1015 of MIL-STD-883.
(2) TA = +125°C, minimum.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
4.2.2 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained
under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance
with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit
shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified
in method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4).
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TABLE IIA. Electrical test requirements.
Test requirements
Subgroups
(in accordance with
MIL-STD-883,
method 5005, table I)
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Device
class M
Device
class Q
Device
class V
Interim electrical
parameters (see 4.2)
---
---
1
Final electrical
parameters (see 4.2)
1/ 1, 2, 3, 7,
8, 9
1/ 1, 2, 3, 7,
8, 9
2/ 3/ 1, 2, 3, 7,
8, 9
Group A test
requirements (see 4.4)
1, 2, 3, 4, 7,
8, 9, 10, 11
1, 2, 3, 4, 7,
8, 9, 10, 11
1, 2, 3, 4, 7,
8, 9, 10, 11
Group C end-point electrical
parameters (see 4.4)
1, 2, 3
1, 2, 3
3/ 1, 2, 3, 7,8,
9, 10, 11
Group D end-point electrical
parameters (see 4.4)
1, 2, 3
1, 2, 3
1, 2, 3
Group E end-point electrical
parameters (see 4.4)
1, 7, 9
1, 7, 9
1, 7, 9
1/ PDA applies to subgroup 1.
2/ PDA applies to subgroups 1, 7, and deltas.
3/ Delta limits as specified in table IIB shall be required where specified, and the delta limits shall be completed
with reference to the zero hour electrical parameters.
TABLE IIB. Burn-in and operating life test Delta parameters (+25°C). 1/
Parameter 2/
Symbol
Delta Limits
ICCH, ICCL
±150 nA
Input current low level
IIL
±20 nA
Input current high level
IIH
±20 nA
Output voltage low level
(VCC = 5.5 V, IOL = 24 mA)
VOL
±0.04 V
Output voltage high level
(VCC = 5.5 V, IOH = -24 mA)
VOH
±0.2 V
Quiescent supply current
1/ This table is a representation of what vendor CAGE F8859 and
vendor CAGE 01295 have experienced and is guaranteed
and not meant to be construed as a quality assurance
requirement for any other vendor.
2/ These parameters shall be recorded before and after the
required burn-in and life tests to determine the delta limits.
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4.4.1 Group A inspection.
a.
Tests shall be as specified in table IIA herein.
b.
For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table in figure 2 herein. The test
vectors used to verify the truth table shall, at a minimum, test all functions of each input and output. All possible input
to output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 2, herein. For device
classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device.
c.
CIN and CPD shall be measured only for initial qualification and after process or design changes which may affect
capacitance. CIN shall be measured between the designated terminal and GND at a frequency of 1 MHz. CPD shall be
tested in accordance with the latest revision of JEDEC Standard JESD20 and table IA herein. For CIN and CPD, test all
applicable pins on five devices with zero failures.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a.
Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify
the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method
1005 of MIL-STD-883.
b.
TA = +125°C, minimum.
c.
Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a. End-point electrical parameters shall be as specified in table IIA herein.
b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device
classes must meet the post irradiation end-point electrical parameter limits as defined in table IA at
TA = +25°C +5°C, after exposure, to the subgroups specified in table IIA herein.
4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883
method 1019, condition A and as specified herein.
4.4.4.1.1 Accelerated annealing test. Accelerated annealing tests shall be performed on all devices requiring a RHA level
greater than 5k rads (Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and shall
be the pre-irradiation end-point electrical parameter limit at 25°C ±5°C. Testing shall be performed at initial qualification and
after any design or process changes which may affect the RHA response of the device.
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4.4.4.2 Single event phenomena (SEP). When specified in the purchase order or contract, SEP testing shall be required on
class V devices. SEP testing shall be performed on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as
approved by the qualifying activity at initial qualification and after any design or process changes which may affect the upset or
latchup characteristics. Test four devices with zero failures. ASTM F1192 may be used as a guideline when performing SEP
testing. The test conditions for SEP are as follows:
a.
The ion beam angle of incidence shall be between normal to the die surface and 60° to the normal, inclusive
(i.e. 0° ≤ angle ≤ 60°). No shadowing of the ion beam due to fixturing or package related effects is allowed.
b.
The fluence shall be ≥ 100 errors or ≥ 10 ions/cm .
c.
The flux shall be between 10 and 10 ions/cm /s. The cross-section shall be verified to be flux independent by
measuring the cross-section at two flux rates which differ by at least an order of magnitude.
d.
The particle range shall be ≥ 20 microns in silicon.
e.
The upset test temperature shall be +25°C and the latchup test temperature shall be the maximum rated operating
temperature ±10°C.
f.
Bias conditions shall be defined by the manufacturer for latchup measurements.
g.
For SEP test limits, see table IB herein.
7
2
5
2
2
4.5 Methods of inspection. Methods of inspection shall be specified as follows:
4.5.1 Voltage and current. Unless otherwise specified, all voltages given are referenced to the microcircuit GND terminal.
Currents given are conventional current and positive when flowing into the referenced terminal.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a
contractor- prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform DLA Land and Maritime, when a system application requires
configuration control and which SMD's are applicable to that system. DLA Land and Maritime will maintain a record of users and
this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-8108.
6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA,, Columbus, Ohio 43218-3990,
or telephone (614)-692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
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6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DLA Land and Maritime-VA, and
have agreed to this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DLA Land and Maritime-VA,.
6.7 Additional information. When specified in the purchase order or contract, a copy of the following additional data shall be
supplied.
a. RHA test conditions (SEP).
b. Number of upsets (SEU).
c. Number of transients (SET).
d. Occurrence of latch-up (SEL).
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-87549
A.1 SCOPE
A.1.1 Scope. This appendix establishes minimum requirements for microcircuit die to be supplied under the Qualified
Manufacturers List (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers
approved QM plan for use in monolithic microcircuits, multi-chip modules (MCMs), hybrids, electronic modules, or devices using
chip and wire designs in accordance with MIL-PRF-38534 are specified herein. Two product assurance classes consisting of
military high reliability (device class Q) and space application (device class V) are reflected in the Part or Identification Number
(PIN). When available, a choice of Radiation Hardiness Assurance (RHA) levels is reflected in the PIN.
A.1.2 PIN. The PIN is as shown in the following example:
For device class V:
5962
F
Federal
stock class
designator
\
RHA
designator
(see A.1.2.1)
87549
01
Device
type
(see A.1.2.2)
/
V
Device
class
designator
(see A.1.2.3)
9
A
Die
code
Die
details
(see A.1.2.4)
\/
Drawing number
A.1.2.1 RHA designator. Device classes Q and V RHA identified die meet the MIL-PRF-38535 specified RHA levels. A dash
(-) indicates a non-RHA die.
A.1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
Circuit function
01
54AC00
Quad 2-input NAND gate
03
AC00KGD-SP
Quad 2-input NAND gate
A.1.2.3 Device class designator.
Device class
Q or V
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-87549
A.1.2.4 Die details. The die details designation is a unique letter which designates the die's physical dimensions, bonding
pad location(s) and related electrical function(s), interface materials, and other assembly related information, for each product
and variant supplied to this appendix.
A.1.2.4.1 Die physical dimensions.
Die type
Figure number
01
03
A-1
A-2
A.1.2.4.2 Die bonding pad locations and electrical functions.
Die type
Figure number
01
03
A-1
A-2
A.1.2.4.3 Interface materials.
Die type
Figure number
01
03
A-1
A-2
A.1.2.4.4 Assembly related information.
Die type
Figure number
01
03
A-1
A-2
A.1.3 Absolute maximum ratings. See paragraph 1.3 herein for details.
A.1.4 Recommended operating conditions. See paragraph 1.4 herein for details.
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-87549
A.2. APPLICABLE DOCUMENTS
A.2.1 Government specification, standards, and handbooks. The following specification, standard, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in
the solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARD
MIL-STD-883
-
Test Method Standard Microcircuits.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103
MIL-HDBK-780
-
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://quicksearch.dla.mil/ or from the Standardization Document Order
Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
A.2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
A.3 REQUIREMENTS
A.3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer’s Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein.
A.3.2 Design, construction and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein and the manufacturer’s QM plan for device classes Q and V.
A.3.2.1 Die physical dimensions. The die physical dimensions shall be as specified in A.1.2.4.1 and on figure A-1 and
figure A-2.
A.3.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations and electrical functions shall be as
specified in A.1.2.4.2 and on figure A-1 and figure A-2.
A.3.2.3 Interface materials. The interface materials for the die shall be as specified in A.1.2.4.3 and on figure A-1 and
figure A-2.
A.3.2.4 Assembly related information. The assembly related information shall be as specified in A.1.2.4.4 and on figure A-1
and figure A-2.
A.3.2.5 Truth table. The truth table shall be as defined in paragraph 3.2.3 herein.
A.3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be as defined in paragraph 3.2.6 herein.
A.3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and post-irradiation parameter limits are as specified in table IA of the body of this
document.
A.3.4 Electrical test requirements. The wafer probe test requirements shall include functional and parametric testing sufficient
to make the packaged die capable of meeting the electrical performance requirements in table IA.
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-87549
A.3.5 Marking. As a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a
customer, shall be identified with the wafer lot number, the certification mark, the manufacturer’s identification and the PIN listed
in A.1.2 herein. The certification mark shall be a “QML” or “Q” as required by MIL-PRF-38535.
A.3.6 Certification of compliance. For device classes Q and V, a certificate of compliance shall be required from a
QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see A.6.4 herein). The certificate of
compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this appendix shall
affirm that the manufacturer’s product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and the
requirements herein.
A.3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535
shall be provided with each lot of microcircuit die delivered to this drawing.
A.4 VERIFICATION
A.4.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures shall be in accordance
with MIL-PRF-38535 or as modified in the device manufacturer’s Quality Management (QM) plan. The modifications in the QM
plan shall not affect the form, fit, or function as described herein.
A.4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the
manufacturer’s QM plan. As a minimum, it shall consist of:
a.
Wafer lot acceptance for class V product using the criteria defined in MIL-STD-883, method 5007.
b.
100% wafer probe (see paragraph A.3.4 herein).
c.
100% internal visual inspection to the applicable class Q or V criteria defined in MIL-STD-883, method 2010 or the
alternate procedures allowed in MIL-STD-883, method 5004.
A.4.3 Conformance inspection.
A.4.3.1 Group E inspection. Group E inspection is required only for parts intended to be identified as radiation assured (see
A.3.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. End point electrical testing of
packaged die shall be as specified in table IIA herein. Group E tests and conditions are as specified in paragraphs 4.4.4 herein.
A.5 DIE CARRIER
A.5.1 Die carrier requirements. The requirements for the die carrier shall be accordance with the manufacturer’s QM plan or
as specified in the purchase order by the acquiring activity. The die carrier shall provide adequate physical, mechanical and
electrostatic protection.
A.6 NOTES
A.6.1 Intended use. Microcircuit die conforming to this drawing are intended for use in microcircuits built in accordance with
MIL-PRF-38535 or MIL-PRF-38534 for government microcircuit applications (original equipment), design applications, and
logistics purposes.
A.6.2 Comments. Comments on this appendix should be directed to DLA Land and Maritime-VA,, P.O. Box 3990, Columbus,
Ohio, 43218-3990 or telephone (614) 692-0547.
A.6.3 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
A.6.4 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed within QML-38535 have submitted a certificate of compliance (see A.3.6 herein) to DLA Land and
Maritime-VA, and have agreed to this drawing.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-87549
A
REVISION LEVEL
K
SHEET
21
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-87549
Optional manufacturer's logo
Pad size:
Pad numbers 1 to 6 and 8 to 13:
100 x 100 µm
Pad numbers 7 (GND) and 14 (VCC): 100 x 280 µm
NOTE: Pad numbers reflect terminal numbers when placed in case outline X (see figure 1).
FIGURE A-1.. Die bonding pad locations and electrical functions.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-87549
A
REVISION LEVEL
K
SHEET
22
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-87549
Die physical dimensions.
Die size:
1991 x 1281 µm
Die thickness:
285 ±25 µm
Interface materials.
Top metallization:
Al Si Cu
Thickness:
0.85 µm
Backside metallization:
None
Glassivation.
Type:
PVapox + Nitride
Thickness:
5000 Å – 7000Å
Substrate:
Silicon
Assembly related information.
Substrate potential:
Floating or tied to GND
Special assembly instructions:
Bond pad #14 (VCC) first
FIGURE A-1.. Die bonding pad locations and electrical functions – continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-87549
A
REVISION LEVEL
K
SHEET
23
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-87549
Bond Pad Coordinates in Microns
DESCRIPTION
PAD NUMBER
X MIN
Y MIN
X MAX
Y MAX
1A
1B
1Y
1
2
3
96.3
95
508
510.5
94
94
201.3
200
613
615.5
199
199
2A
2B
2Y
4
5
6
1149
1562
1841.5
94
94
145.5
1254
1667
1946.5
199
199
250.5
GND
3Y
3A
7
8
9
1841.5
1841
1750.5
445.5
783
991
1946.5
1946
1855.5
550.5
888
1096
3B
4Y
4A
4B
VCC
10
11
12
13
14
1176.5
921
736
95
102.5
991
991
991
991
692
1281.5
1026
841
200
207.5
1096
1096
1096
1096
797
NOTE: Pad numbers reflect terminal numbers when placed in case outline X (see figure 1).
FIGURE A-2.. Die bonding pad locations and electrical functions.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-87549
A
REVISION LEVEL
K
SHEET
24
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-87549
Die physical dimensions.
Die size:
2118X1268 µm
Die thickness:
381 µm
Interface materials.
Top metallization:
TiW/AlCu2
Thickness:
15.8 µm
Backside metallization:
Silicon with backgrind
Glassivation.
Type:
PVapox + Nitride
Thickness:
8200Å
Substrate:
Silicon
Assembly related information.
Substrate potential:
Floating or tied to GND
Special assembly instructions:
Bond pad #14 (VCC) first
FIGURE A-2. Die bonding pad locations and electrical functions – continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-87549
A
REVISION LEVEL
K
SHEET
25
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 15-04-13
Approved sources of supply for SMD 5962-87549 are listed below for immediate acquisition information only and shall be added to
MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or
deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to
and accepted by DLA Land and Maritime -VA. This information bulletin is superseded by the next dated revision of MIL-HDBK-103
and QML-38535. DLA Land and Maritime maintains an online database of all current sources of supply at
http://www.landandmaritime.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
01295
SNJ54AC00J
0C7V7
54AC00DMQB
01295
SNJ54AC00W'
0C7V7
54AC00FMQB
01295
SNJ54AC00FK
0C7V7
54AC00LMQB
5962-8754901XA
0C7V7
54AC00XA
5962F8754901CA
F8859
RHFAC00D04Q
5962F8754901CC
F8859
RHFAC00D03Q
5962F8754901V9A
F8859
AC00DIE2V
5962F8754901XA
F8859
RHFAC00K02Q
5962F8754901XC
F8859
RHFAC00K01Q
5962F8754901VXA
F8859
RHFAC00K02V
5962F8754901VXC
F8859
RHFAC00K01V
5962F8754901VCA
F8859
RHFAC00D04V
5962F8754901VCC
F8859
RHFAC00D03V
5962-8754901CA
5962-8754901DA
5962-87549012A
5962-87549022A
3/
SNJ54AC11000FK
5962-8754902EA
3/
SNJ54AC11000J
5962-8754902FA
3/
SNJ54AC11000W
5962-8754903VCA
01295
SNV54AC00J-SP
5962-8754903VDA
01295
SNV54AC00W-SP
5962R8754903VCA
01295
SNVR54AC00J
5962R8754903VDA
01295
SNVR54AC00W
5962R8754903V9A
01295
AC00KGD-SP
1/
The lead finish shown for each PIN representing a hermetic
package is the most readily available from the manufacturer
listed for that part. If the desired lead finish is not listed,
contact the vendor to determine its availability.
2/
Caution. Do not use this number for item acquisition. Items
acquired to this number may not satisfy the performance
requirements of this drawing.
3/
Not available from an approved source of supply.
Sheet
1 of 2
STANDARD MICROCIRCUIT DRAWING BULLETIN - Continued.
DATE: 15-04-13
Vendor CAGE
number
Vendor name
and address
F8859
ST Microelectronics
3 rue de Suisse
CS 60816
35208 RENNES cedex2-FRANCE
01295
Texas Instruments Incorporated
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243
Point of contact: U.S. Highway 75 South
P.O. Box 84, M/S 853
Sherman, TX 75090-9493
0C7V7
e2v, Inc.
(dba QP Semiconductor, Inc)
765 Sycamore Drive
Milpitas, CA 95035
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
Sheet
2 of 2