REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Make corrections to table I minimum propagation delay times at 2.7 V. Update boilerplate to MIL-PRF-38535 requirements. – jak 00-12-12 Thomas M. Hess B Update boilerplate to MIL-PRF-38535 requirements. – LTG 07-10-24 Thomas M. Hess C Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. LTG 13-01-25 Thomas M. Hess REV SHEET REV SHEET REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http://www.landandmaritime.dla.mil Joseph A. Kerby STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles F. Saffle, Jr. APPROVED BY Monica L. Poelking THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A DRAWING APPROVAL DATE 00-07-11 REVISION LEVEL C MICROCIRCUIT, DIGITAL, LOW VOLTAGE CMOS, QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER, MONOLITHIC SILICON SIZE CAGE CODE A 67268 SHEET DSCC FORM 2233 APR 97 5962-00506 1 OF 14 5962-E213-13 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 00506 Federal stock class designator \ RHA designator (see 1.2.1) 01 Q E A Device type (see 1.2.2) Device class designator (see 1.2.3) Case outline (see 1.2.4) Lead finish (see 1.2.5) / \/ Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number 01 Circuit function 54LVC157A 2-line to 1-line data selector/multiplexer 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter E F 2 Descriptive designator GDIP1-T16 or CDIP2-T16 GDFP2-F16 or CDFP3-F16 CQCC1-N20 Terminals 16 16 20 Package style Dual-in-line Flat pack Square leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-00506 A REVISION LEVEL C SHEET 2 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VCC) .................................................................................. -0.5 V dc to +6.5 V dc DC input voltage range (VIN) ................................................................................ -0.5 V dc to +6.5 V dc 4/ DC output voltage range (VOUT) ........................................................................... -0.5 V dc to VCC + 0.5 V dc 4/ 5/ Input clamp current (IIK) (VIN < 0.0) ...................................................................... -50 mA Output clamp current (IOK) (VOUT < 0.0 or VOUT > VCC) ......................................... -50 mA Continuous output current (IO) ............................................................................. ±50 mA Continuous current through VCC or GND ............................................................. ±100 mA Maximum power dissipation at TA = +55°C (in still air) (PD) ................................. 550 mW 6/ Storage temperature range (TSTG) ....................................................................... -65°C to +150°C Lead temperature (soldering, 10 seconds) .......................................................... +300°C Thermal resistance, junction-to-case (θJC) ........................................................... See MIL-STD-1835 Junction temperature (TJ) .................................................................................... +150°C 1.4 Recommended operating conditions. 2/ 3/ 7/ Supply voltage range (VCC): Operating ........................................................................................................... +2.0 V dc to +3.6 V dc Data retention only ............................................................................................. +1.5 V dc Minimum high level input voltage (VIH): VCC = 2.7 V to 3.6 V ............................... +2.0 V Maximum low level input voltage (VIL): VCC = 2.7 V to 3.6 V ................................ +0.8 V Input voltage range (VIN) ...................................................................................... +0.0 V dc to 5.5 V dc Output voltage range (VOUT)................................................................................. +0.0 V dc to VCC Maximum high level output current (IOH): VCC = 2.7 V ........................................................................................................ -12 mA VCC = 3.0 V ........................................................................................................ -24 mA Maximum low level output current (IOL): VCC = 2.7 V ........................................................................................................ +12 mA VCC = 3.0 V ........................................................................................................ +24 mA Input transition rise or fall rate (∆t/∆V):................................................................. 0.0 to 10.0 ns/V Case operating temperature range (TC) ............................................................... -55°C to +125°C ______ 1/ 2/ 3/ 4/ 5/ 6/ 7/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Unless otherwise noted, all voltages are referenced to GND. The limits for the parameters specified herein shall apply over the full specified VCC range and case temperature range of -55°C to +125°C. The input and output negative-voltage ratings may be exceeded provided that the input and output clamp-current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. Unused inputs must be held high or low to prevent them from floating. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-00506 A REVISION LEVEL C SHEET 3 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Copies of these documents are available online at https://assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 as specified herein, or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Ground bounce load circuit and waveforms. The ground bounce load circuit and waveforms shall be as specified on figure 4. 3.2.6 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 5. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-00506 A REVISION LEVEL C SHEET 4 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. . STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-00506 A REVISION LEVEL C SHEET 5 TABLE I. Electrical performance characteristics. Test and MIL-STD-883 test method 1/ High level output voltage 3006 Low level output voltage 3007 Symbol VOH VOL Test conditions 2/ -55°C ≤ TC ≤ +125°C +2.0 V ≤ VCC ≤ +3.6 V unless otherwise specified For all inputs affecting output under test VIN = VIH = 2.0 V or VIL = 0.8 V For all other inputs VIN = VCC or GND For all inputs affecting output under test VIN = VIH = 2.0 V or VIL = 0.8 V For all other inputs VIN = VCC or GND VCC Group A subgroups Limits 3/ Min Max IOH = -100 µA 2.7 V and 3.6 V 1, 2, 3 VCC-0.2 IOH = -12 mA 2.7 V 1, 2, 3 2.2 3.0 V Unit V 2.4 IOH = -24 mA 3.0 V 1, 2, 3 IOL = +100 µA 2.7 V and 3.6 V 1, 2, 3 0.2 IOL = +12 mA 2.7 V 1, 2, 3 0.4 IOL = +24 mA 3.0 V 1, 2, 3 0.55 2.2 V Input current high 3010 IIH For input under test, VIN = 5.5 V 3.6 V 1, 2, 3 +5.0 µA Input current low 3009 IIL For input under test, VIN = GND 3.6 V 1, 2, 3 -5.0 µA Quiescent supply current 3005 ICC For all inputs, VIN = VCC or GND IOUT = 0 A 3.6 V 1, 2, 3 10.0 µA Quiescent supply current delta TTL input levels 3005 ∆ICC For input under test, VIN = VCC-0.6 V For all other inputs at VIN = VCC or GND 2.7 V and 3.6 V 1, 2, 3 500 µA Input capacitance 3012 CIN TC = +25°C VIN = VCC or GND, See 4.4.1c 3.3 V 4 8.0 pF Power dissipation capacitance CPD 4/ See 4.4.1c TC = +25°C, f = 10 MHz 3.3 V 4 20.0 pF VIN = VIH = 2.0 V or VIL = 0.8 V Verify output VO, See 4.4.1b 2.0 V, 2.7 V and 3.6 V 7, 8 VIH = 2.7 V, VIL = 0.0 V TC = +25°C See 4.4.1d See figure 4 3.0 V 4 1040 3.0 V 4 -780 VOHP 6/ 3.0 V 4 750 VOHV 6/ 3.0 V 4 1080 Functional test 3014 Low level ground bounce noise 5/ VOLP 6/ VOLV 6/ High level VCC bounce noise L H mV See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-00506 A REVISION LEVEL C SHEET 6 TABLE I. Electrical performance characteristics - Continued. Test and MIL-STD-883 test method 1/ Symbol Test conditions 2/ -55°C ≤ TC ≤ +125°C +2.0 V ≤ VCC ≤ +3.6 V unless otherwise specified CL = 50 pF minimum See figure 5 VCC Propagation delay time, mA or mB to mY 3003 tPHL1, tPLH1 7/ Propagation delay time, A/B to mY 3003 tPHL2, tPLH2 7/ 2.7 V Propagation delay time, G to mY 3003 tPHL3, tPLH3 7/ 2.7 V 2.7 V Group A subgroups Limits 3/ Min Max 9,10,11 3.0 V and 3.6 V 6.2 0.8 8.2 0.8 7.0 9,10,11 3.0 V and 3.6 V ns 5.4 9,10,11 3.0 V and 3.6 V Unit 7.8 0.8 6.5 1/ For tests not listed in the referenced MIL-STD-883, utilize the general test procedure of 883 under the conditions listed herein. 2/ Each input/output, as applicable, shall be tested at the specified temperature, for the specified limits, to the tests in table I herein. Output terminals not designated shall be high level logic, low level logic, or open, except for the ICC test, where the output terminals shall be open. When performing the ICC test, the current meter shall be placed in the circuit such that all current flows through the meter. The values to be used for VIH and VIL shall be the VIH minimum and VIL maximum values listed in section 1.4 herein. 3/ For negative and positive voltage and current values, the sign designates the potential difference in reference to GND and the direction of current flow, respectively; and the absolute value of the magnitude, not the sign, is relative to the minimum and maximum limits, as applicable, listed herein. 4/ Power dissipation capacitance (CPD) determines both the power consumption (PD) and current consumption (IS). Where: PD = (CPD + CL) (VCC x VCC)f + (ICC x VCC) IS = (CPD + CL) VCCf + ICC f is the frequency of the input signal; and CL is the external output load capacitance. 5/ Tests shall be performed in sequence, attributes data only. Functional tests shall include the truth table and other logic patterns used for fault detection. The test vectors used to verify the truth table shall, at a minimum, test all functions of each input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 2 herein. Functional tests shall be performed in sequence as approved by the qualifying activity on qualified devices. Allowable tolerances per MIL-STD-883 may be incorporated. For outputs, L ≤ VIL max, H ≥ VIH min, where VIL max and VIH min are listed in section 1.4 herein. 6/ This test is for qualification only. Ground and VCC bounce tests are performed on a non-switching (quiescent) output and are used to measure the magnitude of induced noise caused by other simultaneously switching outputs. The test is performed on a low noise bench test fixture. For the device under test, all outputs shall be loaded with 500Ω of load resistance and a minimum of 50 pF of load capacitance (see figure 4). Only chip capacitors and resistors shall be used. The output load components shall be located as close as possible to the device outputs. It is suggested, that whenever possible, this distance be kept to less than 0.25 inches. Decoupling capacitors shall be placed in parallel from VCC to ground. The values of these decoupling capacitors shall be determined by the device manufacturer. The low and high level ground and VCC bounce noise is measured at the quiet output using a 1 GHz minimum bandwidth oscilloscope with a 50Ω input impedance. The device inputs shall be conditioned such that all outputs are at a high nominal VOH level. The device inputs shall then be conditioned such that they switch simultaneously and the output under test remains at VOH as all other outputs possible are switched from VOH to VOL. VOHV and VOHP are then measured from the nominal VOH level to the largest negative and positive peaks, respectively (see figure 4). This is then repeated with the same outputs not under test switching from VOL to VOH. The device inputs shall be conditioned such that all outputs are at a low nominal VOL level. The device inputs shall then be conditioned such that they switch simultaneously and the output under test remains at VOL as all other outputs possible are switched from VOL to VOH. VOLP and VOLV are then measured from the nominal VOL level to the largest positive and negative peaks, respectively (see figure 4). This is then repeated with the same outputs not under test switching from VOH to VOL. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-00506 A REVISION LEVEL C SHEET 7 TABLE I. Electrical performance characteristics - Continued. 7/ For propagation delay tests, all paths must be tested. Device type 01 Case outlines E, F 2 Terminal number Terminal symbol Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A/B 1A 1B 1Y 2A 2B 2Y GND 3Y 3B 3A 4Y 4B 4A NC A/B 1A 1B 1Y NC 2A 2B 2Y GND NC 3Y 3B 3A 4Y NC 4B 4A G VCC --------- 16 17 18 19 20 G VCC NC = No internal connection Pin description Terminal symbol Description G Enable input (active low) mA, mB (m = 0 to 4) Data inputs A/B Select inputs mY (m = 0 to 4) Outputs FIGURE 1. Terminal connections. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-00506 A REVISION LEVEL C SHEET 8 Inputs Output G mA mB mY H A/B X X X L L L L X L L L H X H L H X L L L H X H H H = High voltage level L = Low voltage level X = Irrelevant FIGURE 2. Truth table. FIGURE 3. Logic diagram. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-00506 A REVISION LEVEL C SHEET 9 NOTES: 1. CL includes a 47 pF chip capacitor (-0 percent, +20 percent) and at least 3 pF of equivalent capacitance from the test jig and probe. 2. RL = 450Ω ±1 percent, chip resistor in series with a 50Ω termination. For monitored outputs, the 50Ω termination shall be the 50Ω characteristic impedance of the coaxial connector to the oscilloscope. 3. Input signal to the device under test: a. VIN = 0.0 V to 2.7 V; duty cycle = 50 percent; fIN ≤ 1 MHz. b. tr, tf = 3.0 ns ±1.0 ns. For input signal generators incapable of maintaining these values of tr and tf, the 3.0 ns limit may be increased up to 10 ns, as needed, maintaining the ±1.0 ns tolerance and guaranteeing the results at 3.0 ns ±1.0 ns; skew between any two switching inputs signals (tsk): ±250 ps. FIGURE 4. Ground bounce test circuit and waveforms. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-00506 A REVISION LEVEL C SHEET 10 NOTES: 1. 2. 3. 4. 5. CL = 50 pF (includes test jig and probe capacitance). RL = 500Ω, RT = 50Ω or equivalent. Input signal from pulse generator: VIN = 0.0 V to VCC; PRR ≤ 1 MHz; tr = 2.5 ns; tf = 2.5 ns; tr and tf shall be measured from 2.43 V to 0.27 V and from 0.27 V to 2.43V, respectively; duty cycle = 50 percent. Timing parameters shall be tested at a minimum input frequency of 1 MHz. The outputs are measured one at a time with one transition per measurement. FIGURE 5. Switching waveforms and test circuit. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-00506 A REVISION LEVEL C SHEET 11 4. VERIFICATION 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. 4.2.1 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table II herein. c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MIL-PRF-38535, appendix B. 4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF-38535 including groups A, B, C, D, and E inspections, and as specified herein. 4.4.1 Group A inspection. a. Tests shall be as specified in table II herein. b. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table in figure 2 herein. The test vectors used to verify the truth table shall, at a minimum, test all functions of each input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 2, herein. For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device. c. CIN, and CPD shall be measured only for initial qualification and after process or design changes which may affect capacitance. CIN and shall be measured between the designated terminal and GND at a frequency of 1 MHz. This test may be performed at 10 MHz and guaranteed, if not tested, at 1 MHz. The DC bias for the pin under test (VBIAS) = 2.5 V or 3.0 V. For CIN, and CPD, test all applicable pins on five devices with zero failures. For CIN a device manufacturer may qualify devices by functional groups. A specific functional group shall be composed of function types, that by design, will yield the same capacitance values when tested in accordance with table I, herein. The device manufacturer shall set a function group limit for the CIN test. The device manufacturer may then test one device functional group, to the limits and conditions specified herein. All other device functions in that particular functional group shall be guaranteed, if not tested, to the limits and test conditions specified in table I, herein. The device manufacturers shall submit to DLA Land and Maritime-VA the device functions listed in each functional group and the test results for each device tested. 4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table II herein. 4.4.2.1 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-00506 A REVISION LEVEL C SHEET 12 TABLE II. Electrical test requirements. Test requirements Subgroups (in accordance with MIL-PRF-38535, table III) Device class Q Device class V Interim electrical parameters (see 4.2) --- 1 Final electrical parameters (see 4.2) 1/ 1, 2, 3, 7, 8, 9, 10, 11 2/ 1, 2, 3, 7, 8, 9, 10, 11 Group A test requirements (see 4.4) 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 Group C end-point electrical parameters (see 4.4) 1, 2, 3 1, 2, 3, 7,8, 9, 10, 11 Group D end-point electrical parameters (see 4.4) 1, 2, 3 1, 2, 3 Group E end-point electrical parameters (see 4.4) 1, 7, 9 1, 7, 9 1/ PDA applies to subgroup 1. 2/ PDA applies to subgroups 1 and 7. 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table II herein. 4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). a. End-point electrical parameters shall be as specified in table II herein. b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535 for the RHA level being tested. All device classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25°C ±5°C, after exposure, to the subgroups specified in table II herein. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes Q and V. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing. 6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-00506 A REVISION LEVEL C SHEET 13 6.3 Record of users. Military and industrial users should inform DLA Land and Maritime when a system application requires configuration control and which SMD's are applicable to that system. DLA Land and Maritime will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-0544. 6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA, Columbus, Ohio 43218-3990, or telephone (614) 692-0540. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535 and MIL-HDBK-1331. 6.6 Sources of supply. 6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in MIL-HDBK-103 and QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DLA Land and Maritime-VA and have agreed to this drawing. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-00506 A REVISION LEVEL C SHEET 14 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 13-01-25 Approved sources of supply for SMD 5962-00506 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DLA Land and Maritime-VA. This information bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/. Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar PIN 2/ 5962-0050601QEA 01295 SNJ54LVC157AJ 5962-0050601QFA 01295 SNJ54LVC157AW 5962-0050601Q2A 01295 SNJ54LVC157AFK 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. Vendor CAGE number 01295 Vendor name and address Texas Instruments Incorporated Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin.