DATASHEET

ISL8120IR
Data Sheet
November 11, 2011
Dual/n-Phase Buck PWM Controller with
Integrated Drivers
The ISL8120IRZEC integrates two voltage-mode
synchronous buck PWM controllers to control a dual
independent voltage regulator or a 2-phase single output
regulator. It has PLL circuits and can output a phase-shiftprogrammable clock signal for the system to be expanded to
3-, 4-, 6-, 12- phases with desired interleaving phase shift. It
also integrates current sharing control for the power module
to operate in parallel, which offers high system flexibility.
It has voltage feed forward compensation to maintain a
constant loop gain for optimal transient response, especially
for applications with a wide input voltage range. Its
integrated high speed MOSFET drivers and multi-feature
functions provide complete control and protection for a
2/n-phase synchronous buck converter, dual independent
regulators, or DDR tracking applications (VDDQ and VTT
outputs).
The output voltage of a ISL8120IRZEC-based converter can be
precisely regulated to as low as the internal reference voltage
0.6V, with a system accuracy of ±0.9% over industrial
temperature and line load variations. Channel 2 can track an
external ramp signal for DDR/tracking applications.
FN6763.2
Features
• Full Traceability Through Assembly and Test by
Date/Trace Code Assignment
• Enhanced Process Change Notification per MIL-PRF-38535
• Enhanced Obsolescence Management
• Wide VIN Range Operation: 3V to 22V
- VCC Operation from 3V to 5.60V
• Fast Transient Response
- 80MHz Bandwidth Error Amplifier
- Voltage-Mode PWM Leading-Edge Modulation Control
- Voltage Feed-Forward
• Dual Channel 5V High Speed 4A MOSFET Gate Drivers
- Internal Bootstrap Diodes
• Internal Linear Regulator Provides a 5.4V Bias from VIN
• External Soft-Start Ramp Reference Input for
DDR/Tracking Applications
• Excellent Output Voltage Regulation
- 0.6V ±0.6%/±0.9% Internal Reference Over Industrial
Temperature
- True Differential Remote Voltage Sensing
• Oscillator Programmable from 150kHz to 1.5MHz
• Frequency Synchronization
The ISL8120IRZEC integrates an internal linear regulator,
which generates VCC from input rail for applications with
only one single supply rail. The internal oscillator is
adjustable from 150kHz to 1.5MHz, and is able to track an
external clock signal for frequency synchronization and
phase paralleling applications. The integrated Pre-Biased
Digital Soft-Start, Differential Remote Sensing Amplifier, and
Programmable Input Voltage POR features enhance the
value of ISL8120IRZEC.
• Scale for 1-, 2-, 3-, 4-, 6-, up to 12- Phase with Single
Output
The ISL8120IRZEC protects against overcurrent conditions
by inhibiting the PWM operation while monitoring the current
with rDS(ON) of the lower MOSFET, DCR of the output
inductor, or a precision resistor. It also has a PRE-POR
Overvoltage Protection option, which provides some
protection to the load device if the upper MOSFET(s) is
shorted. See “PRE-POR Overvoltage Protection (PRE-POROVP)” on page 24 for details.
• Overcurrent Protection
The ISL8120IRZEC’s Fault Hand Shake feature protects any
channel from overloading/stressing due to system faults or
phase failure. The undervoltage fault protection features are
also designed to prevent a negative transient on the output
voltage during falling down. This eliminates the Schottky
diode that is used in some systems for protecting the load
device from reversed output voltage damage.
- Excellent Phase Current Balancing
- Programmable Phase Shift Between the 2 Phases
Controlled by the ISL8120IRZEC and Programmable
Phase Shift for Clockout Signal
- Interleaving Operation Results in Minimum Input RMS
Current and Minimum Output Ripple Current
• Fault Hand Shake Capability for High System Reliability
- DCR, rDS(ON), or Precision Resistor Current Sensing
- Independent and Average Phase Current OCP
• Output Overvoltage and Undervoltage Protections
• Programmable Phase Shift in Dual Mode Operation
• Digital Soft-Start with Pre-Charged Output Start-up Capability
• Power-Good Indication
• Dual Independent Channel Enable Inputs with Precision
Voltage Monitor and Voltage Feed-Forward Capability
- Programmable Input Voltage POR and its Hysteresis
with a Resistor Divider at EN Input
• Over-Temperature Protection
• Pre-Power-On-Reset Overvoltage Protection Option
• 32 Ld 5x5 QFN Package - Near Chip-Scale Footprint
- Enhanced Thermal Performance for MHz Applications
• Pb-Free (RoHS compliant)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008, 2009, 2011. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL8120IR
Applications
Ordering Information
• Power Supply for Datacom/Telecom and POL
PART
NUMBER
(Note)
• Paralleling Power Module
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE PKG.
(Pb-free) DWG. #
• Wide and Narrow Input Voltage Range Buck Regulators
ISL8120IRZEC
• DDR I and II Applications
ISL8120IRZ-TEC* ISL8120 IRZ -40 to +85 32 Ld QFN L32.5x5B
ISL8120 IRZ -40 to +85 32 Ld QFN L32.5x5B
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
• High Current Density Power Supplies
• Multiple Outputs VRM and VRD
Related Literature
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN (MLFP) Packages”
Pinout
FB1
VMON1
VSEN1-
VSEN1+
ISEN1B
ISEN1A
VCC
BOOT1
ISL8120IRZEC
(32 LD QFN)
TOP VIEW
32
31
30
29
28
27
26
25
COMP1 1
24 UGATE1
ISET 2
23 PHASE1
ISHARE 3
22 LGATE1
21 PVCC
EN/VFF1 4
33
GND
FSYNC 5
20 LGATE2
EN/VFF2 6
19 PHASE2
CLKOUT/REFIN 7
18 UGATE2
17 BOOT2
2
9
10
11
12
13
14
15
16
COMP2
FB2
VMON2
VSEN2-
VSEN2+
ISEN2B
ISEN2A
VIN
PGOOD 8
FN6763.2
November 11, 2011
Block Diagram (1/2)
EN/FF1
PVCC
VCC
VIN
INTERNAL
LINEAR REGULATOR
POWER-ON
RESET (POR)
5.4V
3
OTP
OVER-TEMPERATURE
PROTECTION (OTP)
CHANNEL 1
REFERENCE
VREF = 0.6V
BOOT1
SOFT-START AND
FAULT LOGIC
UGATE1
VCC
VREF
700mV
SAW1
AVG_OCP
FB1
GATE
CONTROL
∑
E/A1
PWM1
7-CYCLE
DELAY
COMP1
PVCC
OV/UV
COMP1
CHANNEL1
OCP
ICSH_ERR
CORRECTION
IAVG_CS
AVERAGE
OCP
1V
VSEN1+
CURRENT
ICS1
ISHARE
CHANNEL 1
UNITY GAIN
DIFF AMP1
PGOOD
COMP1
PGOOD
ISEN1A
CURRENT
SAMPLING
105µA
VSEN1-
LGATE1
CURRENT
CORRECTION
ISEN1B
ICSH_ERR
(BOTTOM PAD) GND
VMON1
PGOOD
FIGURE 1. CHANNEL/PHASE 1 (VDDQ)
ISL8120IR
PHASE1
+
FN6763.2
November 11, 2011
Block Diagram (2/2)
ISHARE
CLKOUT/REFIN FSYNC
EN/FF2
ICSH_ERR
RELATIVE
PHASE
CONTROL
IAVG_CS+15µA
CURRENT
SHARE
BLOCK
SAW1
IAVG_CS+15µA
ISET
IAVG_CS
OTP POR
4
k*VDDQ
VREF
CHANNEL 2
VCC
MASTER CLOCK
OSCILLATOR
GENERATOR
ICS1
+
ICS2
+
AVERAGE
M/D
CONTROL
CURRENT
IAVG
SOFT-START AND
FAULT LOGIC
BOOT2
PVCC
VREF2
700mV
E/A2
7-CYCLE
DELAY
COMP2
+
PWM2
∑
-
CURRENT
VREF
OV/UV
COMP2
PHASE2
GATE
CONTROL
CORRECTION
PVCC
-
LGATE2
+
CHANNEL2
OCP
ICS2
GND
CHANNEL 2
105µA
VSEN2+
ISEN2A
CURRENT
SAMPLING
ISEN2B
VSEN2PGOOD
COMP2
UNITY GAIN
DIFF AMP2
PGOOD
M/D = 1: multiphase
VMON2
M/D = 0: DUAL OUTPUT OPERATION
IAVG_CS = IAVG or ICS1
IAVG = (ICS1 + ICS2) / 2
FN6763.2
November 11, 2011
ICSH_ERR = (VISARE - VISET)/GCS
0.6V =k*VDDQ
FIGURE 2. CHANNEL/PHASE 2 (VTT)
ISL8120IR
AVG_OCP
FB2
UGATE2
SAW2
M/D CONTROL
ISL8120IR
Typical Application I (Dual Regulators with DCR Sensing and Remote Sense)
VIN
VIN_F
+3.3 TO +22V
RCC
CF2
LIN
CHFIN
CBIN
CF1
VCC
PVCC
BOOT1
CBOOT1
UGATE1
VIN
Q1
LOUT1
PHASE1
CF3
VOUT1
COUT1
LGATE1
2kΩ
Q2
ISEN1A
COMP1
ISL8120IRZEC
10Ω
RISEN1
ISEN1B
10Ω
ZCOMP1
FB1
CLKOUT/REFIN
ZFB1
VCC
VMON1
VSENSE1+
RFB1
VSEN1+
ROS1
VSEN1-
PGOOD
CSEN1
VSENSE1-
VIN_F
BOOT2
CBOOT2
RFS
UGATE2
FSYNC
Q3
LOUT2
PHASE2
VOUT2
Q4
LGATE2
COUT2
2kΩ
ISEN2A
10Ω
ISEN2B
COMP2
EN2/FF2
RISEN2
10Ω
ZCOMP2
FB2
EN1/FF1
ZFB2
RSET
VMON2
ISET
RFB2
VSEN2+
ISHARE
VSEN2-
ROS2
CSEN2
VSENSE2+
VSENSE2-
GND
5
FN6763.2
November 11, 2011
ISL8120IR
Typical Application II (Double Data Rate I or II)
VIN
VIN_F
+3.3 TO +22V
RCC
CF2
LIN
CHFIN
CBIN
CF1
VCC
PVCC
BOOT1
CBOOT1
UGATE1
VIN
2.5V
1.8V
LOUT1
PHASE1
CF3
RFS
Q1
(DDR I)
(DDR II)
VDDQ
COUT1
LGATE1
FSYNC
2kΩ
Q2
ISEN1A
COMP1
ISL8120IRZEC
10Ω
RISEN1
ISEN1B
10Ω
ZCOMP1
FB1
ZFB1
VMON1
VSENSE1+
RFB1
VSEN1+
VDDQ
ROS1
VSEN1-
CSEN1
VSENSE1-
R*(VDDQ/0.6-1)
(See notes below)
CLKOUT/REFIN
R
1nF
VDDQ Or VIN_F
BOOT2
CBOOT2
UGATE2
(Or tie REFIN pin to VMON1 pin)
Q3
1.25V (DDR I)
0.9V (DDR II)
LOUT2
PHASE2
VTT
LGATE2
COUT2
Q4
( VDDQ/2)
2kΩ
ISEN2A
10Ω
ISEN2B
COMP2
RISEN2
10Ω
ZCOMP1
FB2
PGOOD
ZFB1
VMON2
RSET
ISET
RFB2
VSEN2+
ISHARE
ROS2
GND
VSEN2-
CSEN2
VSENSE2+
VSENSE2-
Note 1: Set the upper resistor to be a little higher than R*(VDDQ/0.6 - 1) will set the final REFIN voltage (stead state voltage after soft-start) derived from
the VDDQ to be a little higher than internal 0.6V reference. In this way, the VTT final voltage will use the internal 0.6V reference after soft-start.
Note 2: Another way to set REFIN voltage is to connect VMON1 directly to REFIN pin.
6
FN6763.2
November 11, 2011
ISL8120IR
Typical Application III (2-Phase Operation with rDS(ON) Sensing and Voltage Trimming)
VIN
+3V TO +22V
LIN
CHFIN
CF1
RCC
VCC
CBIN
CF2
PVCC
BOOT1
CBOOT1
UGATE1
VIN
Q1
LOUT1
VOUT1
PHASE1
CF3
EN/FF1,2
COUT1
Q2
LGATE1
ISEN1A
10Ω
RISEN1
ISEN1B
ISL8120IRZEC
COMP1/2
VSENSE1+
10Ω
VSENSE1-
ZCOMP1
FB1
RSET
ISET
DNP
VMON1/2
ISHARE
RFB1
VSEN1+
ROS1
VSEN1-
0Ω
CSEN1
PULLED TO VSENSE1TRIM UP
TRIM DOWN
PGOOD
PULLED TO VSENSE1+
VIN_F
BOOT2
CBOOT2
RFS
UGATE2
FSYNC
Q3
LOUT2
PHASE2
LGATE2
Q4
ISEN2A
CLKOUT/REFIN
RISEN2
ISEN2B
VCC
GND
FB2
VSEN2-
VSEN2+
GND
7
FN6763.2
November 11, 2011
ISL8120IR
Typical Application IV (3-Phase Regulator with Precision Resistor Sensing)
VIN
LIN
+3V TO +22V
CIN
CF2
RCC
VCC
VIN_F
PVCC
CF1
BOOT1
CBOOT2
VIN
CF3
UGATE1
LOUT2
VOUT
PHASE1
ISL8120IRZEC
EN/FF1
Q1
LGATE1
PHASE 2
COUT
Q2
ISEN1A
CLKOUT/REFIN
PGOOD
RISEN2
ISEN1B
COMP1
10Ω
FB1
BOOT2
10Ω
VMON1
UGATE2
PHASE2
VSEN1+
LGATE2
VSEN1-
ISEN2A
VSENSE1+
VCC
VSENSE1-
GND
ISEN2B
EN/FF2
GND
FSYNC
FB2
VMON2
ISHARE
VSEN2+
ISET
VSEN2-
R
R
RCC
VCC
CF1
CF2
PVCC
VIN_F
BOOT1
VIN
FSYNC
CF3
UGATE1
Q1
PHASE1
RFS
EN/FF1,2
LGATE1
Q2
PGOOD
EN/FF1,2
VIN_F
BOOT2
ISL8120IRZEC
PHASE 1 AND 3
Q3
ISEN1A
RISEN1
ISEN1B
CBOOT3
LOUT3
CBOOT1
LOUT1
UGATE2
COMP1/2
PHASE2
ZCOMP1
FB1
Q4
ZFB1
VMON1/2
LGATE2
RFB1
VSEN1+
ISEN2A
VSEN1-
ROS1
CSEN1
ISEN2B
RISEN3
VCC
GND
VCC
ISHARE
FB2
VSEN2+
R
VSEN2-
CLKOUT/REFIN
GND
ISET
R
8
FN6763.2
November 11, 2011
ISL8120IR
Typical Application V (4 Phase Operation with DCR Sensing)
VIN
LIN
+3V TO +22V
VIN_F
CIN
VCC
RCC
CF2
PVCC
CF1
BOOT1
CBOOT2
VIN
CF3
UGATE1
CLKOUT/REFIN
Q1
LGATE1
EN/FF1,2
VCC
VCC
VCC
FB2
ISL8120IRZEC
ISEN1A
PHASE 2 AND 4
ISEN1B
VSEN1,2-
10Ω
RISEN2
COMP1/2
VIN_F
BOOT2
Q3
Q4
10Ω
FB1
CBOOT4
LOUT4
VOUT1
COUT
Q2
PGOOD
VSEN1,2+
LOUT2
PHASE1
UGATE2
VMON1/2
PHASE2
ISET
ISEN2A
COS
ROS1
R
GND
LGATE2
RFB1
2ND DIVIDER TO AVOID
SINGLE POINT FAILURE
VSENSE1+
VSENSE1-
FSYNC
ISEN2B
ISHARE
RISEN4
R
VCC
RCC
CF1
CF2
PVCC
VIN_F
BOOT1
VIN
FSYNC
CF3
UGATE1
Q1
CBOOT1
LOUT1
PHASE1
RFS
LGATE1
EN/FF1,2
Q2
PGOOD
VIN_F
ISL8120IRZEC
ISEN1A
PHASE 1 AND 3
ISEN1B
BOOT2
CBOOT3
LOUT3
UGATE2
Q3
COMP1/2
PHASE2
RISEN1
ZCOMP1
ZFB1
FB1
VMON1/2
Q4
LGATE2
RFB1
VSEN1+
ISEN2A
RISEN3
VSEN1-
ROS1
CSEN1
ISEN2B
ISHARE
FB2
VCC
VSEN2+
VCC
R
VSEN2-
VCC
CLKOUT/REFIN
GND
ISET
R
9
FN6763.2
November 11, 2011
ISL8120IR
Typical Application VI (3-Phase Regulator with Resistor Sensing and 1 Phase Regulator)
VIN
LIN
+3V TO +22V
VCC
VIN_F
CIN
CF2
RCC
PVCC
CF1
BOOT1
CBOOT2
VIN
CF3
UGATE1
PHASE 2
LOUT2
VOUT1
PHASE1
EN/FF2
LGATE1
EN/FF1
PGOOD
VCC
Q1
COUT1
Q2
ISEN1A
CLKOUT/REFIN
VIN_F
RISEN2
ISEN1B
COMP1
BOOT2
10Ω
CBOOT4
LOUT4
VOUT2
Q3
UGATE2
FB1
PHASE2
VMON1
COUT2
10Ω
ISL8120IRZEC
VSEN1+
LGATE2
Q4
VSEN1ISEN2A
VSENSE1+
VCC
ISET
10Ω
VSENSE1-
ISEN2B
R
10Ω
ZFB2
RISEN4
ZCOMP2
FSYNC
FB2
ISHARE
VMON2
VSEN2+
VSENSE2+
VSEN2-
GND
R
PHASE 2
VSENSE2-
VCC
RCC
CF1
CF2 VIN_F
PVCC
BOOT1
VIN
FSYNC
CF3
UGATE1
CBOOT1
LOUT1
Q1
PHASE1
RFS
LGATE1
PGOOD
Q2
EN/FF1, 2
VIN_F
BOOT2
ISL8120IRZEC
Q3
RISEN1
ISEN1B
CBOOT3
LOUT3
ISEN1A
UGATE2
COMP1/2
PHASE2
ZCOMP1
FB1
Q4
ZFB1
VMON1/2
LGATE2
RFB1
VSEN1+
ISEN2A
VSEN1-
ROS1
CSEN1
ISEN2B
VCC
RISEN3
GND
VCC
ISHARE
FB2
VSEN2+
PHASE 1 AND 3
R
ISET
VSEN2+
10
CLKOUT/REFIN
VSEN2GND
R
FN6763.2
November 11, 2011
ISL8120IR
Typical Application VII (6 Phase Operation with DCR Sensing)
+3V TO +22V
VIN
VIN_F
LIN
RCC
VCC
CF1
VIN
CLKOUT/REFIN
CF3
EN/FF1, 2
PVCC
BOOT1
CIN
CF2
UGATE1
PHASE1
Q1
LGATE1
Q2
CBOOT3
LOUT3
PGOOD
GND
VCC
VIN_F
CBOOT6
LOUT6
FB2
VSEN2+
VSEN2BOOT2
Q3
Q4
ISL8120IRZEC
PHASE 3 AND 6
UGATE2
PHASE2
LGATE2
ISEN1A
ISEN1B
COMP1/2
FB1
VMON1/2
VSEN1+
VSEN1ISET
RISEN3
VCC
R
ISEN2A
FSYNC
ISEN2B
ISHARE
GND
RISEN6
R
VCC
CF1
RCC
VIN
CF3
EN/FF1, 2
PVCC
BOOT1
VIN_F
CF2
UGATE1
PHASE1
Q1
LGATE1
Q2
PGOOD
VIN_F
CBOOT5
LOUT5
Q4
RISEN5
ISEN1A
ISEN1B
BOOT2
Q3
GND
VCC
UGATE2
PHASE2
ISL8120IRZEC
LGATE2
RISEN2
COMP1/2
FB1
VMON1/2
VSEN1+
VSEN1-
ISEN2A
VCC
CLKOUT/REFIN
ISEN2B
FSYNC
FB2
VSEN2+
VSEN2-
CBOOT2
LOUT2
PHASE 2 AND 5
ISHARE
ISET
GND
R
R
VIN_F
VCC
CF1
CF3
FSYNC
RCC
VIN
EN/FF1, 2
PGOOD
VIN_F
CBOOT4
LOUT4
UGATE2
PHASE2
ISL8120IRZEC
Q4
LGATE2
RISEN4
GND
VCC
FB2
VSEN2+
VSEN2-
LGATE1
Q2
PHASE 1 AND 4
CBOOT1
LOUT1
VOUT1
COUT1
RISEN1
10Ω
ZFB1
10Ω
ZCOMP1
VMON2
ROS1
VSEN1ISHARE
GND
11
Q1
VSEN1+
ISEN2A
ISEN2B
CF2
UGATE1
PHASE1
ISEN1A
ISEN1B
VMON1
FB1
COMP1/2
BOOT2
Q3
PVCC
BOOT1
CLKOUT/REFIN
ISET
RFB1
ROS1
RFB1
CSEN1
VSENSE1+
VSENSE1-
R
R
FN6763.2
November 11, 2011
ISL8120IR
Typical Application VIII (Multiple Power Modules in Parallel with Current Sharing Control)
VIN
LIN
+3V TO +22V
VIN_F
CIN
VCC
RCC2
CF4
BOOT1
CBOOT3
VIN
CF6
CF5
PVCC
UGATE1
PGOOD
Q5
LOUT3
VOUT2
PHASE1
CLKOUT/REFIN
LGATE1
COUT2
Q6
EN/FF1, 2
ISEN1A
VIN_F
BOOT2
ISEN1B
CBOOT4
LOUT4
PHASE2
10Ω
COMP1/2
ISL8120IRZEC
Q8
LGATE2
ZCOMP2
ZFB2
FB1
VMON1/2
RFB2
VSEN1+
ISEN2A
RISEN4
GND
VCC
2-PHASE
MODULE #1
ROS2
RCSR2
VSEN1-
ISEN2B
VSEN2+
FB2
10Ω
RISEN3
UGATE2
Q7
CSEN2
VSENSE2+
VSENSE2VLOAD
FSYNC
ISHARE
VSEN2-
GND
ISET
R
R
VCC
RCC1
CF1
VIN_F
CF2
PVCC
BOOT1
VIN
FSYNC
CF3
UGATE1
Q1
CBOOT1
LOUT1
VOUT1
PHASE1
RFS
LGATE1
EN/FF1, 2
COUT1
Q2
PGOOD
ISEN1A
VIN_F
BOOT2
RISEN1
ISEN1B
CBOOT2
LOUT2
Q3
UGATE2
COMP1/2
PHASE2
ZFB1
FB1
ISL8120IRZEC
Q4
10Ω
ZCOMP1
LGATE2
RFB1
VSEN1+
ISEN2A
RISEN2
10Ω
VMON1/2
VSEN1-
RCSR1
ROS1
CSEN1
VSENSE1+
VSENSE1-
ISEN2B
ISHARE
VSEN2+
GND
VCC
FB2
2-PHASE
R
MODULE #2
CLKOUT/REFIN
VSEN2GND
ISET
R
12
FN6763.2
November 11, 2011
ISL8120IR
Typical Application VIIII (4 Outputs Operation with DCR Sensing)
VIN
LIN
+3V TO +22V
CF3
VSENSE4+
EN/FF2
VSEN2+
RFB4
VSENSE4ZFB3
2Ω
PVCC
BOOT1
VIN
CLKOUT/REFIN
CSEN4
ROS4
2Ω
RCC
VCC
CF1
VIN_F
COUT4 CBOOT6
LOUT6
VOUT4
VSEN2VMON2
FB2
ZCOMP4 COMP2
PGOOD
BOOT2
Q4
Q1
LGATE1
Q2
CBOOT3
LOUT3
VOUT3
COUT3
(PHASE 3 AND 6)
2Ω
RISEN3
2Ω
ZFB3
RFB3
VSEN1+
ROS3
VSEN1ISHARE/ISET
EN/FF1
R
FSYNC
VSENSE3+
CSEN3
VSENSE3-
ISEN2A OUTPUT 3 AND 4 GND
ISEN2B
RCC
VCC
CF1
PVCC
BOOT1
VIN
CF3
EN/FF1, 2
PGOOD
VIN_F
LOUT5
UGATE1
PHASE1
COMP1
FB1
VMON1
ISL8120IRZEC
LGATE2
RISEN6
CBOOT2
CF2
ISEN1A
ISEN1B
UGATE2
PHASE2
Q3
VIN_F
CIN
BOOT2
Q4
LGATE2
ISL8120IRZEC
(PHASE 2 AND 5)
VCC
LGATE1
Q2
CBOOT1
LOUT2
VOUT2
COUT2
RISEN2
2Ω
2Ω
RFB2
CSEN2
ROS2
VSEN1CLKOUT/REFIN
FSYNC
ISEN2B
GND
Q1
COMP1/2 ZCOMP2
FB1
ZFB2
VMON1/2
VSEN1+
ISEN2A
RISEN5
UGATE1
PHASE1
ISEN1A
ISEN1B
UGATE2
PHASE2
Q3
VIN_F
CF2
VSENSE2+
VSENSE2-
ISHARE/ISET
FB2
VSEN2+
VSEN2-
OUTPUT 2
GND
R
VIN_F
VCC
CF1
FSYNC
CF3
RCC
VIN
EN/FF1, 2
PGOOD
VIN_F
CBOOT4
LOUT4
BOOT2
Q3
Q4
UGATE2
PHASE2
LGATE2
ISL8120IRZEC
(PHASE 1 AND 4)
GND
VCC
FB2
VSEN2+
VSEN2-
CF2
UGATE1
PHASE1
Q1
LGATE1
Q2
ISEN1A
ISEN1B
VMON1
FB1
COMP1/2
VOUT1
COUT1
RISEN1
2Ω
ZFB1
2Ω
ZCOMP1
ROS1
RFB1
ROS1
VSEN1ISHARE/ISET
OUTPUT 1
CBOOT1
LOUT1
VMON2
VSEN1+
ISEN2A
ISEN2B
RISEN4
PVCC
BOOT1
CLKOUT/REFIN
RFB1
CSEN1
VSENSE1+
VSENSE1-
R
GND
13
FN6763.2
November 11, 2011
ISL8120IR
Absolute Maximum Ratings
Thermal Information
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +27V
Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
BOOT/UGATE Voltage, VBOOT . . . . . . . . . . . . . . . . . . -0.3V to +36V
Phase Voltage, VPHASE . . . . . . . . . . VBOOT - 7V to VBOOT + 0.3V
BOOT to PHASE Voltage, VBOOT - VPHASE . . -0.3V to VCC +0.3V
Input, Output or I/O Voltage . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V
Thermal Resistance (Typical Notes 1, 2)
θJA(°C/W)
θJC(°C/W)
32 Ld QFN Package . . . . . . . . . . . . . . 32
3.5
Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 22V
Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . . 3V to 5.6V
Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . 3V to 5.6V
Boot to Phase Voltage (Overcharged), VBOOT - VPHASE . . . . . .<6V
Industrial Ambient Temperature Range . . . . . . . . . . .-40°C to +85°C
Maximum Junction Temperature Range . . . . . . . . . . . . . . . . +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
3. Limits should be considered typical and are not production tested.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are
100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VCC SUPPLY CURRENT
Nominal Supply VIN Current
IQ_VIN
VIN = 20V; VCC = PVCC; No Load;
FSW = 500kHz
11
15
20
mA
Nominal Supply VIN Current
IQ_VIN
VIN=3.3V;VCC = PVCC; No Load;
FSW = 500kHz
8
12
14
mA
Shutdown Supply PVCC Current
IPVCC
EN = 0V, PVCC = 5V
0.5
1
1.4
mA
7
10
12
mA
Shutdown Supply VCC Current
IVCC
EN = 0V, VCC = 3V
IPVCC
PVCC = 4V to 5.6V
250
mA
PVCC = 3V to 4V
150
mA
INTERNAL LINEAR REGULATOR
Maximum Current (Note 3)
Saturated Equivalent Impedance (Note 3)
RLDO
P-Channel MOSFET (VIN = 5V)
PVCC Voltage Level
PVCC
IPVCC = 0mA to 250mA
Ω
1
5.1
5.4
5.6
V
Rising VCC Threshold
2.85
3
V
Falling VCC Threshold
2.65
2.75
V
Rising PVCC Threshold
2.85
3.05
V
2.65
2.75
POWER-ON RESET
Falling PVCC Threshold
System Soft-Start Delay (Note 3)
tSS_DLY
After PLL, VCC, and PVCC PORs, and
EN(s) above their thresholds
384
V
Cycles
ENABLE
Turn-On Threshold Voltage
Hysteresis Sink Current
IEN_HYS
Undervoltage Lockout Hysteresis (Note 3)
VEN_HYS
Sink Current
IEN_SINK
Sink Impedance
REN_SINK
14
VEN_RTH = 10.6V; VEN_FTH = 9V
RUP = 53.6kΩ, RDOWN = 5.23kΩ
IEN_SINK = 5mA
0.75
0.8
0.86
V
25
30
35
µA
1.5
V
15
mA
65
Ω
FN6763.2
November 11, 2011
ISL8120IR
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are
100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
1500
kHz
406
kHz
OSCILLATOR
Oscillator Frequency Range
150
RFS = 100k, Figure 20
Oscillator Frequency
VCC = 5V; -40°C < TA <+85°C
Total Variation
Peak-to-Peak Ramp Amplitude
Linear Gain of Ramp Over VEN
Ramp Peak Voltage
ΔVRAMP
VCC = 5V, VEN = 0.8V
GRAMP
GRAMP = ΔVRAMP/VEN
VRAMP_PEAK
ΔVRAMP
VEN = VCC = 5.4V, RUP = 2k
Peak-to-Peak Ramp Amplitude
ΔVRAMP
VEN = VCC = 3V; RUP = 2k
Ramp Amplitude Upon Disable
ΔVRAMP
VEN = 0V; VCC = 3.5V to 5.5V
Ramp Amplitude Upon Disable
ΔVRAMP
VEN = 0V; VCC < 3.4V
377
-9
+9
1
%
VP-P
1.25
VEN = VCC
Peak-to-Peak Ramp Amplitude
Ramp DC Offset
344
VRAMP_OS
VCC - 1.4
V
3
VP-P
0.6
VP-P
1
VP-P
VCC - 2.4
VP-P
1
V
FREQUENCY SYNCHRONIZATION AND PHASE LOCK LOOP
Synchronization Frequency
VCC = 5.4V (3V)
PLL Locking Time
VCC = 5.4V (3V); FSW = 400kHz;
Input Signal Duty Cycle Range (Note 3)
150
1500
105
10
kHz
µs
90
%
410
ns
PWM
Minimum PWM OFF Time
310
tMIN_OFF
345
tBLANKING
175
ns
Channel 1 Reference Voltage (Include
Error and Differential Amplifiers’ Offsets)
VREF1
0.6
V
Channel 2 Reference Voltage (Include
Error and Differential Amplifiers’ Offsets)
VREF2
Current Sampling Blanking Time (Note 3)
REFERENCE
-0.7
0.7
0.6
-0.75
%
V
0.95
%
ERROR AMPLIFIER
DC Gain (Note 3)
Unity Gain-Bandwidth (Note 3)
UGBW_EA
RL = 10k, CL = 100p, at COMP Pin
98
dB
RL = 10k, CL = 100p, at COMP Pin
80
MHz
Input Common Mode Range (Note 3)
Output Voltage Swing
VCC = 5V
Slew Rate (Note 3)
SR_EA
Input Current (Note 3)
IFB
-0.2
VCC - 1.8
V
0.85
VCC - 1.0
V
RL = 10k, CL = 100p, at COMP Pin
20
V/µs
Positive direction into the FB pin
100
nA
Output Sink Current
ICOMP
3
mA
Output Source Current
ICOMP
6
mA
Disable Threshold (Note 3)
VVSEN-
VCC - 0.4
V
DIFFERENTIAL AMPLIFIER
DC Gain (Note 3)
UG_DA
Unity Gain Bandwidth (Note 3)
Unity Gain Amplifier
UGBW_DA
Negative Input Source Current (Note 3)
IVSEN-
Maximum Source Current for Current
Sharing (Typical Application VIII) (Note 3)
IVSEN1-
Input Impedance
VSEN1- Source Current for Current
Sharing when parallel multiple modules
each of which has its own voltage loop
RVSEN+_to
0
dB
5
MHz
100
nA
350
µA
1
MΩ
_VSEN-
Output Voltage Swing (Note 3)
Input Common Mode Range (Note 3)
15
0
VCC - 1.8
V
-0.2
VCC - 1.8
V
FN6763.2
November 11, 2011
ISL8120IR
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are
100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested. (Continued)
PARAMETER
SYMBOL
Disable Threshold (Note3)
TEST CONDITIONS
VVSEN-
VMON1,2 = Tri-State
Upper Drive Source Resistance
RUGATE
Upper Drive Sink Resistance
Lower Drive Source Resistance
Lower Drive Sink Resistance
MIN
TYP
MAX
UNITS
VCC - 0.4
V
45mA Source Current
1.0
Ω
RUGATE
45mA Sink Current
1.0
Ω
RLGATE
45mA Source Current
1.0
Ω
RLGATE
45mA Sink Current
0.4
Ω
Channel Overcurrent Limit (Note 3)
ISOURCE
VCC = 3V to 5.6V
Channel Overcurrent Limit
ISOURCE
VCC = 5V
VOC_SET
VCC = 3V to 5.6V
(comparator offset included)
GATE DRIVERS
OVERCURRENT PROTECTION
Share Pin OC Threshold
Share Pin OC Hysteresis (Note 3)
108
µA
89
108
122
µA
1.16
1.20
1.22
V
VOC_SET_HYS VCC = 3V to 5.6V
(comparator offset included)
50
mV
CURRENT SHARE
Internal Balance Accuracy (Note 3)
VCC = 3V and 3.6V, 1% Resistor
Sense, 10mV Signal
±5
%
Internal Balance Accuracy (Note 3)
VCC = 4.5V and 5.6V, 1% Resistor
Sense, 10mV Signal
±5
%
External Current Share Accuracy (Note 3)
VCC = 3V and 5.6V, 1% Resistor
Sense, 10mV Signal
±5
%
POWER GOOD MONITOR
Undervoltage Falling Trip Point
VUVF
Undervoltage Rising Hysteresis
VUVR_HYS
Overvoltage Rising Trip Point
VOVR
Overvoltage Falling Hysteresis
VOVF_HYS
Percentage Below Reference Point
-15
Percentage Above UV Trip Point
Percentage Above Reference Point
-13
-11
4
11
Percentage below OV Trip Point
13
%
%
15
4
%
%
PGOOD Low Output Voltage
IPGOOD = 2mA
0.35
V
Sinking Impedance
IPGOOD = 2mA
70
Ω
Maximum Sinking Current (Note 3)
VPGOOD < 0.8V
10
mA
OVERVOLTAGE PROTECTION
OV Latching Up Trip Point
EN/FF= UGATE = LATCH Low,
LGATE = High
118
120
122
%
OV Non-Latching Up Trip Point (Note 3)
EN/FF = Low, UGATE = Low,
LGATE = High
113
%
LGATE Release Trip Point
EN/FF = Low/HIGH, UGATE = Low,
LGATE = Low
87
%
Over-Temperature Trip (Note 3)
150
°C
Over-Temperature Release Threshold
(Note 3)
125
°C
OVER-TEMPERATURE PROTECTION
16
FN6763.2
November 11, 2011
ISL8120IR
Functional Pin Description
GND (Pin 33, Signal and Power Ground Pad)
All voltage levels are referenced to this pad.This pad
provides a return path for the low-side MOSFET drives and
internal power circuitries as well as all analog signals.
Connect this pad to the circuit ground using the shortest
possible path (more than 5 to 6 via to the internal ground
plane, placed on the soldering pad are recommended).
VIN (Pin 16, Internal Linear Regulator Input)
This pin should be tied directly to the input rail when using
the internal linear regulator. It provides power to the internal
linear drive circuitry. When used with an external 5V supply,
this pin should be tied directly to PVCC. The internal linear
device is protected against reverse bias generated by the
remaining charge of the decoupling capacitor at PVCC when
losing the input rail.
VCC (Pin 26, Analog Circuit Bias)
This pin provides power for the analog circuitry. A RC filter is
recommended between the connection of this pin to a 3V to
5.6V bias (typically PVCC). R is suggested to be a 5Ω
resistor. And in 3.3V applications, the R could be shorted to
allow the low end input in concerns of the VCC falling
threshold. The VCC decoupling cap C is strongly
recommended to be as large as 10µF ceramic capacitor.
This pin can be powered either by the internal linear
regulator or by an external voltage source.
will lock to an external frequency source if this pin is
connected to a switching square pulse waveform, typically
the CLKOUT input signal from another ISL8120IRZEC or an
external clock. The internal oscillator synchronizes with the
leading edge of the input signal.
EN/FF1, 2 (Pins 4, 6)
These are triple function pins. The input voltages to these
pins are compared with a precision 0.8V reference and
enable their digital soft-starts. By pulling this pin to voltage
lower than the threshold, the corresponding channel can be
disabled independently. Connecting these pins to input bus
through a voltage resistor divider can monitor the input
voltage. The undervoltage lockout and its hysteresis levels
can be programmed by setting the values of the resistor
dividers. The voltages on these pins are also fed into
controller to be used to adjust the amplitude of each
individual sawtooth independently.
Furthermore, during fault (such as overvoltage, overcurrent,
and over-temperature) conditions, these pins (EN/FF_) are
used to communicate the information to other cascaded ICs
by pulling low.
PGOOD (Pin 8)
Provides an open drain Power-Good signal when both
channels are within 9% of nominal output regulation point
with 4% hysteresis (13%/9%) and soft-start is complete.
PGOOD monitors the outputs (VMON1/2) of the internal
differential amplifiers.
BOOT1, 2 (Pins 25, 17)
ISEN1A, 2A (Pins 27, 15)
This pin provides the bootstrap bias for the high-side driver.
Internal bootstrap diodes connected to the PVCC pin provide
the necessary bootstrap charge. Its typical operational
voltage range is 2.5V to 5.6V.
These pins are the positive inputs of the current sensing
amplifier. Together with ISEN1B,2B, these pins provide
rDS(ON), DCR, or precision resistor current sensing.
ISEN1B, 2B (Pins 28, 14)
UGATE1, 2 (Pin 24, 8)
These pins provide the drive for the high-side devices and
should be connected to the MOSFETs’ gates.
PHASE1, 2 (Pins 23,19)
Connect these pins to the source of the high-side MOSFETs
and the drain of the low-side MOSFETs. These pins
represent the return path for the high-side gate drives.
PVCC (Pin 21, Driver Bias Voltage)
This pin is the output of the internal series linear regulator. It
provides the bias for both low-side and high-side drives. Its
operational voltage range is 3V to 5.6V. The decoupling
ceramic capacitor in the PVCC pin is 10µF.
LGATE1, 2 (Pins 22, 20)
These pins provide the drive for the low-side devices and
should be connected to the MOSFETs’ gates.
FSYNC (Pin 5)
These pins are the negative inputs of the current sensing
amplifier. Together with the ISEN1A, 2A pins they provide
rDS(ON), DCR, or precision resistor current sensing. Refer to
“Typical Application III (2-Phase Operation with rDS(ON)
Sensing and Voltage Trimming)” on page 7 for rDS(ON)
sensing set up and “Typical Application V (4 Phase
Operation with DCR Sensing)” on page 9 for DCR sensing
set-up.
ISET (Pin 2)
This pin sources an 15µA offset current plus the average
current of both channels in multiphase mode or only
Channel 1’s current in independent mode. The voltage
(VISET) set by an external resistor (RISET) represents the
average current level of the local active channel(s). VISET is
compared with a 1V threshold for average overcurrent
protections. For full-scale current, RISET should be
1V/120µA = 8.33kΩ. Typically 10kΩ is used for RSET.
The oscillator switching frequency is adjusted by placing a
resistor (RFS) from this pin to GND. The internal oscillator
17
FN6763.2
November 11, 2011
ISL8120IR
ISHARE (Pin 3)
This pin is used for current sharing purposes and is
configured to current share bus representing all modules’
average current. It sources 15µA offset current plus the
average current of both channels in multiphase mode or
Channel 1’s current in independent mode. The share bus
(ISHARE pins connected together) voltage (VISHARE) set by
an external resistor (RISHARE) represents the average
current level of all active channel(s). The ISHARE bus
voltage compares with each reference voltage set by each
RISET and generates current share error signal for current
correction block of each cascaded controller. The share bus
impedance RISHARE should be set as RISET/NCTRL (RISET
divided by number of active current sharing controllers).
CLKOUT/REFIN (Pin 7)
This pin has a dual function depending on the mode in which
the chip is operating. It provides clock signal to synchronize
with other ISL8120(s) with its VSEN2- pulled within 700mV
of VCC for multiphase (3-, 4-, 6-, 8-, 10-, or 12-phase)
operation. When the VSEN2- pin is not within 700mV of
VCC, ISL8120 is in dual mode (dual independent PWM
output). The clockout signal of this pin is not available in this
mode, but the ISL8120 can be synchronized to external
clock. In dual mode, this pin works as the following two
functions:
1. An external reference (0.6V target only) can be in place
of the Channel 2’s internal reference through this pin for
DDR/tracking applications (see “Internal Reference and
System Accuracy” on page 31).
2. The ISL8120IRZEC operates as a dual-PWM controller
for two independent regulators with selectable phase
degree shift, which is programmed by the voltage level on
REFIN (see “DDR and Dual Mode Operation” on
page 30).
FB1, 2 (Pins 32, 10)
These pins are the inverting inputs of the error amplifiers.
These pins should be connected to VMON1, 2 with the
compensation feedback network. No direct connection
between FB and VMON pins is allowed. With VSEN2- pulled
within 700mV of VCC, the corresponding error amplifier is
disabled and the amplifier’s output is high impedance. FB2 is
one of the two pins to determine the relative phase
relationship between the internal clock of both channels and
the CLKOUT signal. See “DDR and Dual Mode Operation”
on page 30.
COMP1, 2 (Pins 1, 9)
These pins are the error amplifier outputs. They should be
connected to FB1, 2 pins through desired compensation
networks when both channels are operating independently.
When VSEN1-, 2- are pulled within 700mV of VCC, the
corresponding error amplifier is disabled and its output
(COMP pin) is high impedance. Thus, in multiphase
operations, all other SLAVE phases’ COMP pins can tie to
18
the MASTER phase’s COMP1 pin (1st phase), which
modulates each phase’s PWM pulse with a single voltage
feedback loop. While the error amplifier is not disabled, an
independent compensation network is required for each
cascaded IC.
VSEN1+, 2+ (Pins 29, 13)
These pins are the positive inputs of the standard unity gain
operational amplifier for differential remote sense for the
corresponding channel (Channel 1 and 2), and should be
connected to the positive rail of the load/processor. These
pins can also provide precision output voltage trimming
capability by pulling a resistor from this pin to the positive rail
of the load (trimming down) or the return (typical
VSEN1-2-pins) of the load (trimming up). The typical input
impedance of VSEN+ with respect to VSEN- is 500kΩ. By
setting the resistor divider connected from the output voltage
to the input of the differential amplifier, the desired output
voltage can be programmed. To minimize the system
accuracy error introduced by the input impedance of the
differential amplifier, a 100Ω or less resistor is recommended
to be used for the lower leg (ROS) of the feedback resistor
divider.
With VSEN2- pulled within 700mV of VCC, the
corresponding error amplifier is disabled and VSEN2+ is one
of the two pins to determine the relative phase relationship
between the internal clock of both channels and the
CLKOUT signal. See “DDR and Dual Mode Operation” on
page 30 for details.
VSEN1-, 2- (Pins 30, 12)
These pins are the negative inputs of standard unity gain
operational amplifier for differential remote sense for the
corresponding regulator (Channel 1 and 2), and should be
connected to the negative rail of the load/processor.
When VSEN1-, 2- are pulled within 700mV of VCC, the
corresponding error amplifier and differential amplifier are
disabled and their outputs are high impedance. Both
VSEN2+ and FB2 input signal levels determine the relative
phases between the internal controllers as well as the
CLKOUT signal. See “DDR and Dual Mode Operation” on
page 30 for details.
When configured as multiple power modules (with
independent voltage loop) operating in parallel, in order to
implement the current sharing control, a resistor needs to be
inserted between VSEN1- pin and output voltage negative
sense point (between VSEN1- and lower voltage sense
resistor), as shown in the “Typical Application VIII (Multiple
Power Modules in Parallel with Current Sharing Control)” on
page 12. This introduces a correction voltage for the
modules with lower load current to keep the current
distribution balanced among modules. The module with the
highest load current will automatically become the master
module. The recommended value for the VSEN1- resistor is
FN6763.2
November 11, 2011
ISL8120IR
100Ω and it should not be large in order to keep the unit gain
amplifier input impedance compatibility.
VMON1, 2 (Pins 31, 11)
These pins are outputs of the unity gain amplifiers. They are
connected internally to the OV/UV/PGOOD comparators.
These pins should be connected to the FB1, 2 pins by a
standard feedback network when both channels operating
independently. When VSEN1-, 2- are pulled within 700mV of
VCC, the corresponding differential amplifier is disabled and
its output (VMON pin) is high impedance. In such an event,
the VMON pin can be used as an additional monitor of the
output voltage with a resistor divider to protect the system
against single point of failure, which occurs in the system
using the same resistor divider for both of the UV/OV
comparator and output voltage feedback.
Modes of Operation
There are 9 typical operation modes depending upon the
signal levels on EN1/FF1, EN2/FF2, VSEN2+, VSEN2-, FB2,
and CLKOUT/REFIN.
MODE 1: The IC is completely disabled when EN1/FF1 and
EN2/FF2 are pulled below 0.8V.
MODE 2: With EN1/FF1 pulled low and EN2/FF2 pulled high
(Mode 2A), or EN1/FF1 pulled high and EN2/FF2 pulled low
(Mode 2B), the ISL8120IRZEC operates as a single phase
regulator. the current sourcing out from the ISHARE pin
represents the first channel current plus 15µA offset current.
MODE 3: When VSEN2- is used as a negative sense line,
both channels’ phase shift depends upon the voltage level of
CLKOUT/REFIN. When the CLKOUT/REFIN pin is within
29% to 45% of VCC, Channel 2 delays 0° over Channel 1
(Mode 3A); when within 45% to 62% of VCC, 90°delay
(Mode 3B); when greater than 62% to VCC, 180° delay
(Mode 3C). Refer to the “DDR and Dual Mode Operation” on
page 30.
MODE 4: When VSEN2- is used as a negative remote sense
line, and CLKOUT/REFIN is connected to a external voltage
ramp lower than the internal soft-start ramp and lower than
0.6V, the external ramp signal will replaces Channel 2’s
internal soft-start ramp to be tracked at start-up, controller
operating in DDR mode. The controller will use the lowest
voltage among the internal 0.6V reference, the external
voltage in CLKOUT/REFIN pin and the soft-start ramp signal.
Channel 1 is delayed 60° behind Channel 2. Refer to the
“DDR and Dual Mode Operation” on page 30.
19
MODE 5: With VSEN2- pulled within 700mV of VCC and
FB2 pulled to ground, the internal channels are 180°
out-of-phase and operate in 2-phase single output mode
(5A). The CLKOUT/REFIN pin (rising edge) also signals out
clock with 60° phase shift relative to the Channel 1’s clock
signal (falling edge of PWM) for 6-phase operation with two
other ISL8120IRZECs (5B). When the share Pins are not
connected to each other for the three ICs in sync, two of
which can operate in Mode 5A (3 independent outputs can
be generated (Mode 5D)) and Modes 3 and 4 (to generate 4
independent outputs (Mode 5C)) respectively.
MODE 6: With VSEN2- pulled within 700mV of VCC, FB2
pulled high and VSEN2+ pulled low, the internal channels
(as 1st and 3rd Phase, respectively) are 240° out-of-phase
and operate in 3-phase single output mode, combined with
another ISL8120IRZEC at MODE 2B. The CLKOUT/REFIN
pin signals out 120° relative phases to the falling edge of
Channel 1’s clock signal to synchronize with the second
ISL8120IRZEC’s Channel 1 (as 2nd Phase).
MODE 7: With VSEN2- pulled within 700mV of VCC and
FB2 and VSEN2+ pulled high, the internal channels is 180°
out-of-phase. The CLKOUT/REFIN pin (rising edge) signals
out 90° relative phase to the Channel 1’s clock signal (falling
edge of PWM) to synchronize with another ISL8120IRZEC,
which can operate at Mode 3, 4, 5A, or 7A. A 4-phase single
output converter can be constructed with two
ISL8120IRZECs operating in Mode 5A or 7A (Mode 7A). If
the share bus is not connected between ICs, each IC could
generate an independent output (Mode 7B). When the
second ISL8120IRZEC operates as two independent
regulators (Mode 3) or in DDR mode (Mode 4), then three
independent output system is generated (Mode 7C). Both
ICs can also be constructed as a 3-phase converter (0°, 90°,
and 180°, not a equal phase shift for 3-phase) with a single
phase regulator (270°).
MODE 8: The output CLKOUT signal allows expansion for
12-phase operation with the cascaded sequencing as shown
in Table 1. No external clock is required in this mode for the
desired phase shift.
MODE 9: With an external clock, the part can be expanded
for 5, 7, 8, 9 10 and 11 phase single output operation with the
desired phase shift.
FN6763.2
November 11, 2011
ISL8120IR
TABLE 1.
1ST IC (I = INPUT; O = OUTPUT; I/O = INPUT AND OUTPUT, Bi-DIRECTION)
EN1/ EN2/
FF1 FF2 VSEN2(I)
(I)
FB2 (I)
(I)
MODE
-
-
ISHARE (I/O)
REPRESENTS
WHICH
CHANNEL(S)
CURRENT
MODES OF OPERATION
2ND CHANNEL OPERATION OPERATION OUTPUT (See
WRT 1ST (O)
MODE
MODE
Description
(Note)
of 3RD IC
of 2ND IC
for Details)
VSEN2
+ (I)
CLKOUT/REFIN
WRT 1ST
(I or O)
-
-
-
-
-
-
DISABLED
-
N/A
VMON1 =
VMON2 to Keep
PGOOD Valid
-
-
SINGLE
PHASE
-
1ST CHANNEL
VMON1 =
VMON2 to Keep
PGOOD Valid
-
-
SINGLE
PHASE
1
0
0
2A
0
1
2B
1
0
3A
-
-
<VCC - ACTIVE ACTIVE 29% to 45% of
0.7V
VCC (I)
1ST CHANNEL
0°
-
-
DUAL
REGULATOR
3B
-
-
<VCC - ACTIVE ACTIVE 45% to 62% of
0.7V
VCC (I)
1ST CHANNEL
90°
-
-
DUAL
REGULATOR
3C
-
-
<VCC - ACTIVE ACTIVE > 62% of VCC (I)
0.7V
1ST CHANNEL
180°
-
-
DUAL
REGULATOR
4
-
-
<VCC0.7V
1ST CHANNEL
-60°
-
-
DDR MODE
5A
-
-
VCC
GND
-
60°
BOTH CHANNELS
180°
-
-
2-PHASE
ACTIVE ACTIVE ACTIVE
-
-
-
ACTIVE ACTIVE < 29% of VCC (I)
5B
-
-
VCC
GND
-
60°
BOTH CHANNELS
180°
5A
5A or 7A
6-PHASE
5C
-
-
VCC
GND
-
60°
BOTH CHANNELS
180°
5A
5A or 7A
3 OUTPUTs
5D
-
-
VCC
GND
-
60°
BOTH CHANNELS
180°
5A
3 or 4
4 OUTPUTs
6
-
-
VCC
VCC
GND
120°
BOTH CHANNELS
240°
2B
-
3-PHASE
7A
-
-
VCC
VCC
VCC
90°
BOTH CHANNELS
180°
5A or 7A
-
4-PHASE
7B
-
-
VCC
VCC
VCC
90°
BOTH CHANNELS
180°
5A or 7A
-
2 OUTPUTs
(1st IC in Mode
7A)
7C
-
-
VCC
VCC
VCC
90°
BOTH CHANNELS
180°
3, 4
-
3 OUTPUTs
(1st IC in Mode
7A)
8
Cascaded IC Operation MODEs 5A+5A+7A+5A+5A+5A/7A, No External Clock Required
12-PHASE
9
External Clock or External Logic Circuits Required for Equal Phase Interval
5, 7, 8, 9, 10,
11, or (PHASE
>12)
NOTE: “2ND CHANNEL WRT 1ST” is referred to as “channel 2 lag channel 1 by the degrees specified by the number in the corresponding table cells”.
For example, 90° with 2ND CHANNEL WRT 1ST means channel 2 lags channel 1 by 90°; -60° with 2ND CHANNEL WRT 1ST means channel 2 leads
channel 1 by 60°.
20
FN6763.2
November 11, 2011
ISL8120IR
CH1 UG (1ST IC)
D
1-D
180°
CH2 UG (1ST IC)
D
90°
50%
CLKOUT (1ST IC)
90°
D
CH1 UG (2ND IC)
180°
CH2 UG (2ND IC)
D
4-PHASE TIMING DIAGRAM (MODE 7A)
CH1 UG (1ST IC)
D
1-D
240°
D
CH2 UG (1ST IC)
120°
CLKOUT (1ST IC)
50%
120°
CH1 UG (2ND IC)
1-D
D
CH2 UG(2ND IC, OFF, EN2/FF2 = 0)
3-PHASE TIMING DIAGRAM (MODE 6)
VCC
VSEN2- VSEN2+
VMON2
FB2
COMP2
CLKOUT/REFIN
700mV
DIFF
AMP2
UV/OV
COMP2
ERROR
AMP2
VREF2 = VREF
CLOCK GENERATOR
AND
RELATIVE PHASES CONTROL
CHANNEL 1
PWM CONTROL
BLOCK
CHANNEL 2
PWM CONTROL
BLOCK
FIGURE 3. SIMPLIFIED RELATIVE PHASES CONTROL
21
FN6763.2
November 11, 2011
ISL8120IR
Functional Description
.
Voltage Feed-forward
Initialization
Other than used as a voltage monitor described in previous
section, the voltages applied to the EN/FF pins are also fed
to adjust the amplitude of each channel’s individual
sawtooth. The amplitude of each channel’s sawtooth is set to
1.25 times of the corresponding EN/FF voltage upon its
enable (above 0.8V). This helps to maintain a constant gain
( G M = VIN ⋅ D MAX ⁄ ΔV RAMP ) contributed by the modulator
and the input voltage to achieve optimum loop response
over a wide input voltage range. The sawtooth ramp offset
voltage is 1V (equal to 0.8V*1.25), and the peak of the
sawtooth is limited to VCC - 1.4V. With VCC = 5.4V, the
ramp has a maximum peak-to-peak amplitude of VCC - 2.4V
(equal to 3V); So the feed-forward voltage effective range is
typically 3x as the ramp amplitude ranges from 1V to 3V.
Initially, the ISL8120IRZEC Power-On Reset (POR) circuits
continually monitor the bias voltages (PVCC and VCC) and
the voltage at EN pin. The POR function initiates soft-start
operation 384 clock cycles after the EN pin voltage is pulled
to be above 0.8V, all input supplies exceed their POR
thresholds and the PLL locking time expires, as shown in
Figure 4. The enable pin can be used as a voltage monitor
and to set desired hysteresis with an internal 30µA sinking
current going through an external resistor divider. The
sinking current is disengaged after the system is enabled.
This feature is especially designed for applications that
require higher input rail POR for better undervoltage
protection. For example, in 12V applications, RUP = 53.6k
and RDOWN = 5.23k will set the turn-on threshold
(VEN_RTH) to 10.6V and turn-off threshold (VEN_FTH) to 9V,
with 1.6V hysteresis (VEN_HYS).
A 384 cycle delay is added after the system reaches its
rising POR and prior to the soft-start. The RC timing at the
EN/FF pin should be sufficiently small to ensure that the
input bus reaches its static state and the internal ramp
circuitry stabilizes before soft-start. A large RC could cause
the internal ramp amplitude not to synchronize with the input
bus voltage during output start-up or when recovering from
faults. It is recommended to use open drain or open collector
to gate this pin for any system delay, as shown in Figure 5.
During shutdown or fault conditions, the soft-start is reset
quickly while UGATE and LGATE changes states immediately
(<100ns) upon the input drops below falling POR.
HIGH = ABOVE POR; LOW = BELOW POR
VCC POR
PVCC POR
EN1/FF1 POR
384
CYCLES
AND
SOFT-START
OF CHANNEL 1
The multiphase system can immediately turn off all ICs
under fault conditions of one or more phases by pulling all
EN/FF pins low. Thus, no bouncing occurs among channels
at fault and no single phase could carry all current and be
over stressed.
PLL LOCKING
VCC POR
PVCC POR
384
CYCLES
AND
SOFT-START
OF CHANNEL 2
EN2/FF2 POR
FIGURE 4. SOFT-START INITIALIZATION LOGIC
V EN_HYS
R UP = ----------------------------I EN_HYS
R
•V
UP
EN_REF
R DOWN = --------------------------------------------------------------V EN_FTH – V EN_REF
VCC
GRAMP = 1.25
V EN_FTH = V EN_RTH – V EN_HYS
VCC - 1.4V
ΔV RAMP = LIMIT(V CC_FF × G RAMP , VCC - 1.4V - V RAMP_OFFSET )
∑
0.8V
VCC_FF
UPPER LIMIT
LIMITER
SAWTOOTH
AMPLITUDE
(ΔVRAMP)
VIN
VRAMP_OFFSET = 1.0V
LOWER LIMIT
(RAMP OFFSET)
0.8V
RUP
SYSTEM DELAY
RDOWN
EN/FF
384 CLOCK
CYCLES
SOFT-START
IEN_HYS = 30µA
OV, OT, OC, AND PLL LOCKING FAULTS (ONLY FOR EN/FF1)
FIGURE 5. SIMPLIFIED ENABLE AND VOLTAGE FEEDFORWARD CIRCUIT
22
FN6763.2
November 11, 2011
ISL8120IR
SS SETTLING AT VREF + 100mV
FIRST PWM PULSE
VIN
VOUT
ISL8120IRZEC
2-PHASE
R
RUP
ISL8120IRZEC
2-PHASE
EN/FF1
EN/FF1
EN/FF2
EN/FF2
0.0V
1280
t SS = ------------F SW
-100mV
RDOWN
V
EN_HYS
= ---------------------------------------------------------UP
I
⋅N
EN_HYS
PHASE
384
t SS_DLY ≈ -----------F SW
FIGURE 6. TYPICAL 4-PHASE WITH FAULT HANDSHAKE
FIGURE 7. SOFT-START WITH VOUT = 0V
While EN/FF is pulled to ground, a constant voltage (0.8V) is
fed into the ramp generator to maintain a minimum
peak-to-peak ramp.
Since the EN/FF pins are pulled down under fault conditions,
the pull-up resistor (RUP) should be scaled to sink no more
than 5mA current from EN/FF pin. Essentially, the EN/FF
pins cannot be directly connected to VCC.
Soft-start
FIRST PWM PULSE
SS SETTLING AT VREF + 100mV
VOUT
UV
-100mV
The ISL8120IRZEC has two independent digital pre-charged
soft-start circuitry, which has a rise time inversely
proportional to the switching frequency and is determined by
an digital counter that increments with every pulse of the
phase clock. Refer to Figure 7. The full soft-start time from
0V to 0.6V can be estimated by Equation 1.
1280
t SS = ------------f SW
FIGURE 8. SOFT-START WITH VOUT = UV
OV = 113%
FIRST PWM PULSE
(EQ. 1)
The ISL8120IRZEC has the ability to work under a
pre-charged output (see Figure 8). The output voltage would
not be yanked down during pre-charged start-up. If the precharged output voltage is greater than the final target level
but prior to 113% setpoint, the switching will not start until the
output voltage reduces to the target voltage and the first
PWM pulse is generated (see Figure 9). The maximum
allowable pre-charged level is 113%. If the pre-charged level
is above 113% but below 120%, the output will hiccup
between 113% (LGATE turns on) and 87% (LGATE turns off)
while EN/FF is pulled low. If the pre-charged load voltage is
above 120% of the targeted output voltage, then the
controller will be latched off and not be able to power-up.
See “PRE-POR Overvoltage Protection (PRE-POR-OVP)”
on page 24 for details.
VOUT TARGET VOLTAGE
FIGURE 9. SOFT-START WITH VOUT BELOW OV BUT
ABOVE FINAL TARGET VOLTAGE
Power-Good
CHANNEL 1 UV/OV
CHANNEL 2 UV/OV
END OF SS1
END OF SS2
AND
PGOOD
OR
+20%
VMON1, 2
< +20%
+13%
+9%
VREF
For above target pre-charged start-up, the output voltage
would not change until the end of the soft-start. If the initial
dip is below the UV level, the LGATE could be turned off. In
such an event, the body-diode drop of the low-side FET will
be sensed and could potentiality cause an OCP event for
rDS(ON) current sensing applications.
-9%
-13%
GOOD
UV
GOOD
PRE-OV (NO LATCH)
UV
FIGURE 10. POWER-GOOD THRESHOLD WINDOW
23
FN6763.2
November 11, 2011
ISL8120IR
VMON1
113%
87%
OR
FORCE
LGATE1
HIGH
AND
EN/FF1
VMON1>120%
OR
AND
multiphase
MODE = HIGH
VMON2
113%
87%
AND
OR
EN/FF2
FORCE
LGATE2
HIGH
To protect the overall power trains in case of only one
channel of a multiphase system detecting OV, the low-side
MOSFET always turns on at the conditions of EN/FF = LOW
and the output voltage above 113% (all VMON pins and EN
pins are tied together) and turns off after the output drops
below 87%. Thus, in a high phase count application
(Multiphase Mode), all cascaded ICs can latch off
simultaneously via EN pins, and each IC shares the same
sink current to reduce the stress and eliminate the bouncing
among phases.
120%
VOUT
3 CYCLES
VMON2>120%
FIGURE 11. FORCE LGATE HIGH LOGIC
PGOOD
Both channels share the same PGOOD output. Either of the
channels indicating out-of-regulation will pull-down the
PGOOD pin. The Power-Good comparators monitor the
voltage on the VMON pins. The trip points are shown in
Figure 10. PGOOD will not be asserted until after the
completion of the soft-start cycle of both channels. If
Channels 1 or 2 are not used, the Power-Good can stay in
operation by connecting 2 channels’ VMON pins together.
The PGOOD pulls low upon both EN/FF’s disabling it if one
of the VMON pins’ voltage is out of the threshold window.
PGOOD will not pull low until the fault presents for three
consecutive clock cycles. In Dual/DDR application, if the
turn-off channel pre-charges its VMON within the PGOOD
threshold window, it could indicate Power-Good, however,
the PGOOD signal can pull low with an external PNP or
PMOS transistor via the EN/FF of the corresponding off
channel.
Undervoltage and Overvoltage Protection
The Undervoltage (UV) and Overvoltage (OV) protection
circuitry monitor the voltage on the VMON pins. The UV
functionality is not enabled until the end of soft-start. An OV
condition (>120%) during soft-start would latch IC off.
In an UV event, if the output drops below -13% (-9% is the
hysteresis level) due to some reasons other than OV, OC,
OT, and PLL faults (EN/FF is not pulled low) of the target
level at the output voltage falling edge, the lower MOSFETs
will turn off to avoid any negative voltage ringing.
An OV event (VOUT > 120%) causes the high-side MOSFET
to latch off permanently, while the low-side MOSFET turns
on and then turns off after the output voltage drops below
87%. At the same time, the EN/FF and PGOOD are also
latched low. The latch condition can be reset only by
recycling VCC. In Dual/DDR mode, each channel is
responsible for its own OV event with the corresponding
VMON as the monitor. In multiphase mode, both channels
respond simultaneously when either triggers an OV event.
24
3 CYCLES
UV
OV LATCH
UGATE AND EN/FF LATCH LOW
FIGURE 12. UV AND OV TIMING DIAGRAM
PRE-POR Overvoltage Protection (PRE-POR-OVP)
When both the VCC and PVCC are below PORs (not include
EN POR), the UGATE is low and LGATE is floating (high
impedance). EN/FF has no control on LGATE when below
PORs. When above PORs, the LGATE would not be floating
but toggling with its PWM pulses. An external 10Ω resistor,
connected in between Phase and LGATE nodes, enables
the PRE-POR-OVP circuit. The output of the converter that
is equal to phase node voltage via output inductors is then
effectively clamped to the low-side MOSFET’s gate
threshold voltage, which provides some protection to the
microprocessor if the upper MOSFET(s) is shorted during
start-up, shutdown, or normal operations. For complete
protection, the low-side MOSFET should have a gate
threshold that is much smaller than the maximum voltage
rating of the load.
The PRE-POR-OVP works against pre-biased start-up when
pre-charged output voltage is higher than the threshold of
the low-side MOSFET, however, it can be disabled by
placing a 2k resistor from LGATE to ground.
Over-Temperature Protection (OTP)
When the junction temperature of the IC is greater than
+150°C (typically), both EN/FF pins pull low to inform other
cascaded channels via their EN/FF pins. All connected
EN/FFs stay low and release after the IC’s junction
temperature drops below +125°C (typically), with a +25°C
hysteresis (typical).
FN6763.2
November 11, 2011
ISL8120IR
Current Loop
where IL is the inductor DC current, and DCR is its DC
resistance.
When the ISL8120IRZEC operates in 2-phase mode, the
current control loop keeps the channel’s current in balance.
After 175ns blanking period with respect to the falling edge
of the PWM pulse of each channel, the voltage developed
across the DCR of the inductor, rDS(ON) of the low-side
MOSFETs, or a precision resistor, is filtered and sampled for
175ns. The current (ICS1/ICS2) is scaled by the RISEN
resistor and provides feedback proportional to the average
output current of each channel.
For low-side MOSFET rDS(ON) sensing, the ICS can be
derived from Equation 3:
IL • rDS ( ON )
ICS = ---------------------------------RISEN
In multiphase mode (VSEN2- pulled high), the scaled output
currents from both active channels are combined to create
an average current reference (IAVG) which represents
average current of both channel outputs as calculated in
Equation 4.
For DCR sensing, the ICS can be derived from Equation 2:
IL • DCR
ICS = ------------------------RISEN
(EQ. 2)
ICS1 + ICS2
IAVG = ----------------------------------2
DCR SENSING
IOUT1
IOUT1
VOUT
L1
C
IOUT2
PHASE1
L1
DCR1
(EQ. 4)
rDS(ON) SENSING
VOUT
PHASE1
(EQ. 3)
VOUT
PHASE2
DCR2
DCR1
R
R
L2
C
RISEN1
RISEN2
RISEN1
ISEN1B
ISEN1A
ISEN2A
ISEN1A
ISEN1B
VCC
ISEN2B
DCR2
AMP
DCR1
AMP
ICS2
ICS1
700mV
VSEN2-
CHANNEL 1
PWM CONTROL
BLOCK
VSEN2+
E/A
-
IAVG_CS +15µA
ISHARE
CHANNEL 1
CURRENT
CORRECTION
BLOCK
+
+
-
∑
∑
2
+
IAVG
+
-
ICSH_ERR
CURRENT
SHARE
BLOCK
CHANNEL 2
CURRENT
CORRECTION
BLOCK
CHANNEL 2
PWM CONTROL
BLOCK
7 CYCLES
DELAY
CHANNEL 2
SOFT-START AND
FAULT LOGIC
IAVG_CS
ISET
CHANNEL 1
SOFT-START AND
IAVG_CS +15µA
RISET
1.2V
AVG_OC
COMP
ITRIP=105µA
FAULT LOGIC
OC2
COMP
VISHARE
7 CYCLES
DELAY
IAVG = (ICS1 + ICS2)/2
ITRIP = 105µA
OC1
COMP
IAVG_CS = IAVG or ICS1
ICSH_ERR = (VISARE - VISET)/GCS
FIGURE 13. SIMPLIFIED CURRENT SAMPLING AND OVERCURRENT PROTECTION
25
FN6763.2
November 11, 2011
ISL8120IR
typically set to 0.1µF or higher, while R is calculated with
Equation 5.
The signal IAVG is then subtracted from the individual
channel’s scaled current (ICS1 or ICS2) to produce a current
correction signal for each channel. The current correction
signal keeps each channel’s output current contribution
balanced relative to the other active channel.
L
R = -----------------------C • DCR
(EQ. 5)
Figure 13 shows a simple and flexible configuration for both
rDS(ON) and DCR sensing.
For multiphase operation, the share bus (VISHARE)
represents the average current of all active channels and
compares with each IC’s average current (IAVG_CS equals to
IAVG or ICS1 depending upon the configuration, represented
by VISET) to generate current share error signal (ICS_ERR)
for each individual channel. Each current correction signal is
then subtracted from the error amplifier output and fed to the
individual channel PWM circuits.
Current Share Control in Multiphase Single Output
The IAVG_CS is the average current of both channels (IAVG,
2-phase mode) or only Channel 1 (ICS1, any other modes).
ISHARE and ISET pins source a copy of IAVG_CS with 15µA
offset, for example, the full-scale will be 120µA. If one single
external resistor is used as RISHARE connecting the
ISHARE bus to ground for all the ICs in parallel, RISHARE
should be set equal to RISET/NCTRL (where NCNTL is the
number of the ISL8120IRZEC controllers in parallel or
multiphase operations), and the share bus voltage
(VISHARE) set by the RISHARE represents the average
current of all active channels. Another way to set RISHARE is
to put one resistor in each IC’s ISHARE pin and use the
same value with RISET (RISHARE = RISET), in which case
the total equivalent resistance value is also RISET/NCTRL.
The voltage (VISET) set by RISET represents the average
current of the corresponding device and compared with the
share bus (VISHARE). The current share error signal
(ICSH_ERR) is then fed into the current correction block to
adjust each channel’s PWM pulse accordingly.
When both channels operate independently, the average
function is disabled and generates zero average current
(IAVG = 0), and current correction block of Channel 2 is also
disabled. The IAVG_CS is the Channel 1 current ICS1. The
channel 1 makes any necessary current correction by
comparing its channel current (represented by VISET) with
the share bus (VISHARE). When the share bus does not
connect to other ICs, the ISET and ISHARE pins can be
shorted together and grounded via a single resistor to
ensure zero share error.
Note that the common mode input voltage range of the
current sense amplifiers is VCC - 1.8V. Therefore, the
rDS(ON) sensing should be used for applications with output
voltage greater than VCC - 1.8V. For example, application of
3.3V output is suggested to use rDS(ON) sensing.
The current share function provides at least 10% overall
accuracy between ICs, 5% within the IC when using a 1%
resistor to sense a 10mV signal. The current share bus
works for up to 12-phase.
In addition, the R-C network components (for DCR sensing)
are selected such that the RC time constant matches the
inductor L/DCR time constant. Otherwise, it could cause
undershoot/overshoot during load transient and start-up. C is
For multiphase implementation, one single error amplifier
should be used for the voltage loop. Therefore, all other
ERROR
AMP 1
ERROR
AMP 2
ICS1
IAVG_CS
CURRENT
MIRROR
BLOCK
SHARE BUS
ISHARE
RISHARE
-
∑
-
+
+
- ∑
VERROR1 ICS2
IAVG_CS
ICSH_ERR
CURRENT
MIRROR
BLOCK
∑
+
-
+
- ∑
VERROR2
ICSH_ERR
VCC
700mV
IAVG = (ICS1 + ICS2) / 2
IAVG_CS = IAVG or ICS1
ISET
VSEN2-
IDROOP + 15µA = IAVG_CS + 15µA = ISET = ISHARE
RISET
RISHARE = RISET/NCTRL
FIGURE 14. SIMPLIFIED CURRENT SHARE AND INTERNAL BALANCE IMPLEMENTATION
26
FN6763.2
November 11, 2011
ISL8120IR
channels’ error amplifiers should be disabled with their
corresponding VSEN- pulled to VCC, as shown in Figure 15.
precision 1.2V threshold (±1%, 50mV hysteresis); while the
105µA OCP comparator with 7-cycle delay is also activated.
Current Share Control Loop in Multi-Module with
Independent Voltage Loop
In multiphase operation, the VISHARE represents the
average current of all active channels and compares with a
precision 1.2V threshold (±1%, 50mV hysteresis) to
determine the overcurrent condition, while each channel has
additional overcurrent trip point at 105µA with 7-cycle delay.
This scheme helps protect against loss of channel(s) in
multi-phase mode so that no single channel could carry
more than 105µA in such event. See Figure 13. Note that it
is not necessary for the RISHARE to be scaled to trip at the
same level as the 105µA OCP comparator if the application
allows. For instance, when Channel 1 operates
independently, the OC trip set by 1.2V comparator can be
lower than 105µA trip point as shown in Equation 6.
The power module controlled by ISL8120IRZEC with its own
voltage loop can be paralleled to supply one common output
load with its integrated Master-Slave current sharing control,
as shown in “Typical Application VIII (Multiple Power
Modules in Parallel with Current Sharing Control)” on
page 12. A resistor RCSR needs to be inserted between
VSEN1- pin and the lower resistor of the voltage sense
resistor divider for each module. With this resistor, the
correction current sourcing from VSEN1- pin will create a
voltage offset to maintain even current sharing among
modules. The recommended value for the VSEN1- resistor
RCSR is 100Ω and it should not be large in order to keep the
unity gain amplifier input pin impedance compatibility. The
maximum source current from VSEN1- pin is 350µA, which
is combined with RCSR to determine the current sharing
regulation range. The generated correction voltage on RCSR
is suggested to be within 5% of VREF (0.6V) to avoid fault
trigging of UV/OV and PGOOD during dynamic events.
⎛ I OC V OUT ⎛ 1 – D
⎞
⎜ ---------- + ---------------- • ⎝ ---------------- – t MIN_OFF⎞⎠ ⎟ • DCR
N
L
2F
⎝
⎠
SW
R ISEN1 = ---------------------------------------------------------------------------------------------------------------------I TRIP
1V
R ISHARE = --------------I TRIP
(EQ. 6)
R ISET = R ISHARE ⋅ N CNTL
where N is the number of phases; NCNTL is the number of
the ISL8120IRZEC controllers in parallel or multiphase
operations; ITRIP = 105µA; IOC is the load overcurrent trip
point; tMIN_OFF is the minimum Ugate turn off time that is
350ns; RISHARE in Equation 6 represents the total
equivalent resistance in ISHARE pin bus of all ICs in
multiphase or module parallel operation.
To attain good current balance in system start up preventing
single module from overcurrent, the paralleled modules are
recommended to be synchronized and the enable pins (EN/FF)
should be tied together to initial start-up at the same instant.
Overcurrent Protection
The OCP function is enabled at start-up. When both
channels operate independently, the average function is
disabled and generates zero average current (IAVG = 0). The
Channel 2 current (ICS2) is compared with ITRIP (105µA)
and has its own independent overcurrent protection; while
the 7 clock cycles delay is bypassed. The Channel 1’s
current (ICS1) plus 15µA offset forms a voltage (VISHARE)
with an external resistor RISHARE and compares with a
The overcurrent trip current source is trimmed to 105µA
±10% for both channels, while the overcurrent threshold
(represented by VISHARE) for multiphase operation (or
Channel 1 depending upon configuration) is a precision 1.2V
±1% with 50mV hysteresis.
For the RISEN chosen for OCP setting, the final value is
usually higher than the number calculated from Equation 6.
VCC
VSEN1/2- COM1/2
VSEN2-
ISET
ISL8120IRZEC1
ISET
ISL8120IRZEC2
VSEN1/2- COM1/2
COM1/2
VSEN1+
ISET
ISL8120IRZEC3
VSEN1RISET1
ISHARE
RISET2
RISHARE1
ISHARE
ISHARE
RISHARE2
RISET3
RISHARE3
SHARE BUS
RISHARE_ = RISET_
FIGURE 15. SIMPLIFIED 6-PHASE SINGLE OUTPUT IMPLEMENTATION
27
FN6763.2
November 11, 2011
ISL8120IR
The reason of which is practical especially for low DCR
applications the PCB and inductor pad soldering resistance
would have large effects in total impedance affecting the
DCR voltage to be sensed.
2.65V TO 5.6V
2Ω
3V TO 26.4V
10µF
1µF
When OCP is triggered, the controller pulls EN/FF low
immediately to turn off UGATE and LGATE. However, if the
output overshoot is greater than 113% at EN/FF = LOW,
LGATE turns ON until the output voltage drops below 87%.
A delay time, equal to 3 soft-start intervals, is entered to
allow the disturbance to clear. After the delay time, the
controller then initiates a soft-start interval. If the output
voltage comes up and returns to the regulation, PGOOD
transitions high. If the OC trip is exceeded during the
soft-start interval, the controller pulls EN/VFF low again. The
PGOOD signal will remain low and the soft-start interval will
be allowed to expire. Another soft-start interval will be
initiated after the delay interval. If an overcurrent trip occurs
again, this same cycle repeats until the fault is removed.
There is a100ns delay to prevent any fault triggering during
start-up or load transient. For a hard short of the output, the
overcurrent protection reduces the regulator RMS output
current much less than 60% of the full load current by putting
the controller into hiccup mode.
PVCC
VCC
VIN
Z1
Z2
5V
FIGURE 16. INTERNAL REGULATOR IMPLEMENTATION
The LDO is capable to supply 250mA with regulated 5.4V
output. In 3.3V input applications, when the VIN pin voltage
is 3V, the LDO still can supply 150mA while maintaining LDO
output voltage higher than VCC falling threshold to keep IC
operating. Figure 17 shows the LDO voltage drop under
different load current. However, its thermal capability should
not be exceeded. The power dissipation inside the IC could
be estimated with Equation 7.
6.0
5.5
The VIN pin is connected to PVCC with an internal series
linear regulator (1W Typical), which is internally
compensated. The PVCC and VIN pins should have the
recommended bypasses connected to GND for proper
operation. The internal series linear regulator’s input (VIN)
can range between 3V to 22V. The internal linear regulator is
to provide power for both the internal MOSFET drivers
through the PVCC pin and the analog circuitry through the
VCC pin. The VCC pin should be connected to the PVCC pin
with an RC filter to prevent high frequency driver switching
noise from entering the analog circuitry. When VIN drops
below 5.0V, the pass element will saturate; PVCC will track
VIN, minus the dropout of the linear regulator. When used
with an external 5V supply, VIN pin is recommended to be
tied directly to PVCC.
5.0
PVCC (V)
Internal Series Linear and Power Dissipation
PVCC @ 250mA + Iq
PVCC @ 100mA + Iq
4.5
4.0
PVCC @ 140mA + Iq
3.5
3.0
2.5
2.0
2.5
Iq IS AROUND 15mA
3.0
3.5
4.0
4.5
5.0
5.5
VIN PIN VOLTAGE (V)
6.0
6.5
7.0
FIGURE 17. PVCC vs VIN VOLTAGE
P IC = ( VIN – PVCC ) ⋅ I VIN + P DR
(EQ. 7)
⎛ Q G1 • N Q1 Q G2 • N Q2⎞
I VIN = ⎜ ------------------------------ + ------------------------------⎟ • PVCC • F SW + I Q_VIN
V GS2 ⎠
⎝ V GS1
28
FN6763.2
November 11, 2011
ISL8120IR
(EQ. 8)
P DR = P DR_UP + P DR_LOW
R LO1
R HI1
⎛
⎞ P Qg_Q1
P DR_UP = ⎜ -------------------------------------- + ----------------------------------------⎟ • --------------------2
⎝ R HI1 + R EXT1 R LO1 + R EXT1⎠
R LO2
R HI2
⎛
⎞ P Qg_Q2
P DR_LOW = ⎜ -------------------------------------- + ----------------------------------------⎟ • --------------------R
+
R
R
+
R
2
⎝ HI2
EXT2
LO2
EXT2⎠
Oscillator
The Oscillator is a sawtooth waveform, providing for leading
edge modulation with 350ns minimum dead time. The
oscillator (Sawtooth) waveform has a DC offset of 1.0V.
Each channel’s peak-to-peak of the ramp amplitude is set to
proportional the voltage applied to its corresponding EN/FF
pin. See “Voltage Feed-forward” on page 22.
Q G2 • PVCC 2
P Qg_Q2 = --------------------------------------- • F SW • N Q2
V GS2
R GI2
R EXT2 = R G2 + ------------N
R GI1
R EXT2 = R G1 + ------------N
Q2
Q1
where the gate charge (QG1 and QG2) is defined at a
particular gate to source voltage (VGS1and VGS2) in the
corresponding MOSFET datasheet; IQ_VIN is the driver’s
total quiescent current with no load at drive outputs; NQ1 and
NQ2 are number of upper and lower MOSFETs, respectively.
To keep the IC within its operating temperature range, an
external power resistor could be used in series with VIN pin
to bring the heat out of the IC, or and external LDO could be
used when necessary.
PVCC
BOOT
D
CGD
RHI1
RLO1
G
UGATE
RG1
CDS
RGI1
CGS
Q1
S
PHASE
FIGURE 18. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
D
CGD
RHI2
LGATE
RLO2
G
RG2
CDS
RGI2
CGS
Q2
S
GND
SWITCHING FREQUENCY (kHz)
1,600
Q G1 • PVCC 2
P Qg_Q1 = --------------------------------------- • F SW • N Q1
V GS1
1,400
1,200
1,000
800
600
400
200
0
20 40
60 80 100 120 140 160 180 200 220 240 260
R_FS (kΩ )
FIGURE 20. RFS vs SWITCHING FREQUENCY
Frequency Synchronization and Phase Lock Loop
The FSYNC pin has two primary capabilities: fixed frequency
operation and synchronized frequency operation. By tying a
resistor (RFSYNC) to GND from FSYNC pin, the switching
frequency can be set at any frequency between 150kHz and
1.5MHz. Frequency setting curve shown in Figure 20 are
provided to assist in selecting the correct value for RFSYNC.
By connecting the FSYNC pin to an external square pulse
waveform (such as the CLOCK signal, typically 50% duty
cycle from another ISL8120IRZEC), the ISL8120IRZEC will
synchronize its switching frequency to the fundamental
frequency of the input waveform. The maximum voltage to
FSYNC pin is VCC + 0.3V. The Frequency Synchronization
feature will synchronize the leading edge of CLKOUT signal
with the falling edge of Channel 1’s PWM clock signal. The
CLKOUT is not available until the PLL locks.
The locking time is typically 130µs for FSW = 500kHz.
EN/VFF1 is released for a soft-start cycle until the FSYNC
stabilized and the PLL is in locking. The PLL circuits control
only EN/FF1, and control Channel 2’s soft-start instead of
EN/FF2. Therefore, it is recommended to connect all EN/FF
pins together in multiphase configuration.
The loss of a synchronization signal for 13 clock cycles, the
IC is disabled until the PLL returns locking, at which point a
soft-start cycle is initiated and normal operation resumes.
Holding FSYNC low will disable the IC.
FIGURE 19. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
29
FN6763.2
November 11, 2011
ISL8120IR
VOUT
RFB
RFB
ROS
ROS
ZCOMP
VCC
GND
VSEN-
VSEN+
PGOOD
VMON
FB
COMP
700mV
GAIN=1
VREF
OV/UV
COMP
ERROR AMP
PGOOD
FIGURE 22. DUAL OUTPUT VOLTAGE SENSE FOR SINGLE POINT OF FAILURE PROTECTION
Differential Amplifier for Remote Sense
VSEN+
20k
RDIF = 500k
20k
VSEN-
20k
20k
FIGURE 21. EQUIVALENT DIFFERENTIAL AMPLIFER
The differential remote sense buffer has a precision unity
gain resistor matching network, which has a ultra low offset
of 1mV. This true remote sensing scheme helps compensate
the droop due to load on the positive and negative rails and
maintain the high system accuracy of ±0.6%.
The output of the remote sense buffer is connected directly
to the internal OV/UV comparator. As a result, a resistor
divider should be placed on the input of the buffer for proper
regulation, as shown in Figure 24. The VMON pin should be
connected to the FB pin by a standard feedback network.
Since the input impedance of VSEN+ pin in respect to
VSEN- pin is about 500kΩ, it is highly recommended to
include this impedance into calculation and use 100Ω or less
for the lower leg (ROS) of the feedback resistor divider to
optimize system accuracy. Note that any RC filter at the
inputs of differential amplifier will contribute as a pole to the
overall loop compensation.
As some applications will not need the differential remote
sense, the output of the remote sense buffer can be disabled
and be placed in high impedance by pulling VSEN- within
700mV of VCC. In such an event, the VMON pin can be
30
used as an additional monitor of the output voltage with a
resistor divider to protect the system against single point of
failure, which occurs in the system using the same resistor
divider for the UV/OV comparator and the output regulation.
The resistor divider ratio should be the same as the one for
the output regulation so that the correct voltage information
is provided to the OV/UV comparator. Figure 22 shows the
differential sense amplifier can directly used as a monitor
without pulling VSEN- high.
DDR and Dual Mode Operation
If the CLKOUT/REFIN is less than 800mV, an external
soft-start ramp (0.6V) can be in parallel with the Channel 2’s
internal soft-start ramp for DDR/tracking applications (DDR
Mode). The output voltage (typical VTT output) of Channel 2
tracks with the input voltage (typical VDDQ*(1 + k) from
Channel 1) at the CLKOUT/REFIN pin. As for the external
input signal and internal reference signal (ramp and 0.6V), the
one with the lowest voltage will be the one to be used as the
reference comparing with FB signal. Since the UV/OV
comparator uses the same internal reference 0.6V, to
guarantee UV/OV and Pre-charged start-up functions of
Channel 2, the target voltage derived from Channel 1 (VDDQ)
should be scaled close to 0.6V, and it is suggested to be
slightly above (+2%) 0.6V with an external resistor divider,
which will have the Channel 2 use the internal 0.6V reference
after soft-start. Any capacitive load at REFIN pin should not
slow down the ramping of this input 150mV lower than the
Channel 2 internal ramp. Otherwise, the UV protection could
be fault triggered prior to the end of the soft-start. The start-up
of Channel 2 can be delayed to avoid such situation
happening, if high capacitive load presents at REFIN pin for
noise decoupling. During shutdown, Channel 2 will follow
Channel 1 until both channels drops below 87%, at which both
channels enter UV protection zone. Depending on the
FN6763.2
November 11, 2011
ISL8120IR
VOS_DA should set to zero when the differential amplifier is
in the loop, the differential amplifier’s input impedance
(RDIF) is typically 500kΩ with a tolerance of 20% (RDIF%)
and can be neglected when ROS is less than 100Ω. To set a
precision setpoint, ROS can be scaled by two paralleled
resistors.
loading, Channel 1 might drop faster than Channel 2. To solve
this race condition, Channel 2 can either power up from
Channel 1 or bridge the Channel 1 with a high current
Schottky diode. If the system requires to shutdown both
channels when either has a fault, tying EN/FF1 and EN/FF2
will do the job. In DDR mode, Channel 1 delays 60° over
Channel 2.
VCC
In Dual mode, depending upon the resistor divider level of
REFIN from VCC, the ISL8120IRZEC operates as a dual
PWM controller for two independent regulators with a phase
shift as shown in Table 2. The phase shift is latched as VCC
raises above POR and cannot be changed on-the-fly.
VSEN2-
PHASE-SHIFTED
CLOCK
VDDQ
ISL8120IRZEC
STATE
MACHINE
k*R
CLKOUT/REFIN
TABLE 2.
MODE
DECODING
REFIN RANGE
PHASE for CHANNEL
2 WRT CHANNEL 1
REQUIRED
REFIN
DDR
<29% of VCC
-60°
0.6V
Dual
29% to 45% of
VCC
0°
37% VCC
Dual
45% to 62% of
VCC
90°
53% VCC
Dual
62% to VCC
180°
VCC
700mV
R
VDDQ
k = ------------------ – 1
0.6V
INTERNAL SS
0.6V
FB2
E/A2
FIGURE 23. SIMPLIFIED DDR IMPLEMENTAION
Internal Reference and System Accuracy
The internal reference is set to 0.6V. Including bandgap
variation and offset of differential and error amplifiers, it has
an accuracy of 0.9% over industrial temperature range.
While the remote sense is not used, its offset (VOS_DA)
should be included in the tolerance calculation. Equations 9
and 10 show the worst case of system accuracy calculation.
VSENSE- (REMOTE)
10Ω
VOUT (LOCAL)
GND (LOCAL)
VSENSE+ (REMOTE)
CSEN
10Ω
RFB
ROS
ZFB
VSEN-
VCC
VSEN+
ZCOMP
PGOOD
VMON
FB
COMP
700mV
GAIN=1
VREF
OV/UV
COMP
ERROR AMP
PGOOD
FIGURE 24. SIMPLIFIED REMOTE SENSING IMPLEMENTATION
31
FN6763.2
November 11, 2011
ISL8120IR
R FB ⋅ ( 1 – R% )⎞
⎛
%min = ( Vref ⋅ ( 1 – Ref% ) – V OS_DA ) ⋅ ⎜ 1 + ----------------------------------------⎟
R OSMAX ⎠
⎝
(EQ. 9)
1
R OSMAX = ----------------------------------------------------------------------------------------------------1
1
----------------------------------------+ ---------------------------------------------------R OS ⋅ ( 1 + R% ) R DIF ⋅ ( 1 + R DIF % )
R FB ⋅ ( 1 – R% )⎞
⎛
%max = ( Vref ⋅ ( 1 – Ref% ) – V OS_DA ) ⋅ ⎜ 1 + ----------------------------------------⎟
R OSMIN ⎠
⎝
(EQ. 10)
1
R OSMIN = ----------------------------------------------------------------------------------------------1
1
--------------------------------------- + ------------------------------------------------R OS ⋅ ( 1 – R % ) R DIF ⋅ ( 1 – R DIF % )
2.5
R% = 1%
2.0
1.5
OUTPUT REGULATION (%)
Figure 25 shows the tolerance of various output voltage
regulation for 1%, 0.5%, and 0.1% feedback resistor
dividers. Note that the farther the output voltage setpoint
away from the internal reference voltage, the larger the
tolerance; the lower the resistor tolerance (R%), the tighter
the regulation.
0.5%
1.0
0.1%
0.5
0.0
-0.5
0.1%
-1.0
0.5%
-1.5
-2.0
-2.5
0.5
1%
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT VOLTAGE (V)
FIGURE 25. OUTPUT REGULATION WITH DIFFERENT
RESISTOR TOLERANCE FOR REF% = ±0.6%
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
32
FN6763.2
November 11, 2011
ISL8120IR
Package Outline Drawing
L32.5x5B
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 11/07
4X 3.5
5.00
28X 0.50
A
B
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
32
25
1
5.00
24
3 .30 ± 0 . 15
17
(4X)
8
0.15
9
16
0.10 M C A B
+ 0.07
32X 0.40 ± 0.10
TOP VIEW
4 32X 0.23 - 0.05
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 ± 0.1
C
BASE PLANE
SEATING PLANE
0.08 C
( 4. 80 TYP )
( 28X 0 . 5 )
SIDE VIEW
(
3. 30 )
(32X 0 . 23 )
C
0 . 2 REF
5
( 32X 0 . 60)
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
33
FN6763.2
November 11, 2011
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