DATASHEET

Single-Phase PWM Regulator for IMVP-6.5™ Mobile
CPUs and GPUs
ISL62881, ISL62881B
Features
The ISL62881 is a single-phase PWM buck regulator for
miroprocessor or graphics processor core power supply. It uses an
integrated gate driver to provide a complete solution. The PWM
modulator of ISL62881 is based on Intersil's Robust Ripple
Regulator (R3) technology™. Compared with traditional modulators,
the R3™ modulator commands variable switching frequency during
load transients, achieving faster transient response. With the same
modulator, the switching frequency is reduced at light load,
increasing the regulator efficiency.
• Precision Core Voltage Regulation
- 0.5% System Accuracy Over-Temperature
- Enhanced Load Line Accuracy
The ISL62881 can be configured as CPU or graphics Vcore controller
and is fully compliant with IMVP-6.5™ specifications. It responds to
DPRSLPVR signals by entering/exiting diode emulation mode. It
reports the regulator output current through the IMON pin. It senses
the current by using either discrete resistor or inductor DCR
whose variation over-temperature can be thermally
compensated by a single NTC thermistor. It uses differential
remote voltage sensing to accurately regulate the processor die
voltage. The adaptive body diode conduction time reduction
function minimizes the body diode conduction loss in diode
emulation mode. User-selectable overshoot reduction function
offers an option to aggressively reduce the output capacitors as
well as the option to disable it for users concerned about
increased system thermal stress.
Maintaining all the ISL62881 functions, the ISL62881B offers
VR_TT# function for thermal throttling control. It also offers the
split LGATE function to further improve light load efficiency.
• Voltage Identification Input
- 7-Bit VID Input, 0V to 1.500V in 12.5mV Steps
- Supports VID Changes On-The-Fly
• Supports Multiple Current Sensing Methods
- Lossless Inductor DCR Current Sensing
- Precision Resistor Current Sensing
• Superior Noise Immunity and Transient Response
• Current Monitor
• Differential Remote Voltage Sensing
• High Efficiency Across Entire Load Range
• Integrated Gate Driver
• Split LGATE Driver to Increase Light-Load Efficiency (for
ISL62881B)
• Adaptive Body Diode Conduction Time Reduction
• User-selectable Overshoot Reduction Function
• Capable of Disabling the Droop Function
• Audio-filtering for GPU Application
• Small Footprint 28 Ld 4x4 TQFN Package
• Pb-Free (RoHS Compliant)
Applications
• Notebook Computers
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL62881HRTZ
628 81HRTZ
-10 to +100
28 Ld 4x4 TQFN
L28.4x4
ISL62881BHRTZ
62881B HRTZ
-10 to +100
32 Ld 5x5 TQFN
L32.5x5E
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL62881, ISL62881B. For more information on MSL please see techbrief
TB363.
June 16, 2011
FN6924.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2009-2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL62881, ISL62881B
Pin Configurations
VID2
VID2
VID3
VID3
22
VID4
VID4
23
VID5
VID5
24
VID6
VID6
26 25
DPRSLPVR
VR_ON
27
CLK_EN#
DPRSLPVR
28
VR_ON
ISL62881B
(32 LD TQFN)
TOP VIEW
ISL62881
(28 LD TQFN)
TOP VIEW
32 31 30 29 28 27 26 25
CLK_EN# 1
21 VID1
PGOOD 1
24 VID1
PGOOD 2
20 VID0
RBIAS 2
23 VID0
VR_TT# 3
22 VCCP
RBIAS
3
VW
4
19 VCCP
GND PAD
(BOTTOM)
COMP 5
18 LGATE
NTC 4
17 VSSP
GND 5
21 LGATEb
GND PAD
(BOTTOM)
20 LGATEa
18 PHASE
FB 8
17 UGATE
BOOT
IMON
9 10 11 12 13 14 15 16
VIN
14
VDD
13
ISUM+
12
ISUM-
11
RTN
10
19 VSSP
VSEN
9
BOOT
COMP 7
8
IMON
15 UGATE
VIN
7
VDD
VW 6
VSEN
ISUM+
16 PHASE
RTN
6
ISUM-
FB
Pin Function Descriptions
COMP
GND (Bottom Pad)
Signal common of the IC. Unless otherwise stated, signals are
referenced to the GND pin.
This pin is the output of the error amplifier. Also, a resistor across this
pin and GND adjusts the overcurrent threshold.
FB
CLK_EN#
Open drain output to enable system PLL clock; goes active 13
switching cycles after Vcore is within 10% of Vboot.
This pin is the inverting input of the error amplifier.
VSEN
PGOOD
Remote core voltage sense input. Connect to microprocessor die.
Power-Good open-drain output indicating when the regulator is
able to supply regulated voltage. Pull-up externally with a 680Ω
resistor to VCCP or 1.9kΩ to 3.3V.
RTN
RBIAS
A resistor to GND sets internal current reference. A 147kΩ
resistor sets the controller for CPU core application and a 47kΩ
resistor sets the controller for GPU core application.
Remote voltage sensing return. Connect to ground at
microprocessor die.
ISUM- and ISUM+
Droop current sense input.
VDD
VR_TT#
5V bias power.
Thermal overload output indicator.
VIN
NTC
Battery supply voltage, used for feed-forward.
Thermistor input to VR_TT# circuit.
IMON
VW
An analog output. IMON outputs a current proportional to the
regulator output current.
A resistor from this pin to COMP programs the switching
frequency (8kΩ gives approximately 300kHz).
BOOT
Connect an MLCC capacitor across the BOOT and the PHASE
pins. The boot capacitor is charged through an internal boot
2
FN6924.3
June 16, 2011
ISL62881, ISL62881B
diode connected from the VCCP pin to the BOOT pin, each time
the PHASE pin drops below VCCP minus the voltage dropped
across the internal boot diode.
UGATE
Output of the high-side MOSFET gate driver. Connect the UGATE
pin to the gate of the high-side MOSFET.
PHASE
Current return path for the high-side MOSFET gate driver. Connect
the PHASE pin to the node consisting of the high-side MOSFET
source, the low-side MOSFET drain and the output inductor.
LGATEb (For ISL62881B)
Another output of the low-side MOSFET gate driver. This gate
driver will be pulled low when the DPRSLPVR pin logic is high.
Connect the LGATEb pin to the gate of the low-side MOSFET that
is idle in deeper sleep mode.
VCCP
Input voltage bias for the internal gate drivers. Connect +5V to
the VCCP pin. Decouple with at least 1µF of an MLCC capacitor to
VSSP1 and VSSP2 pins respectively.
VID0, VID1, VID2, VID3, VID4, VID5, VID6
VSSP
VID input with VID0 = LSB and VID6 = MSB.
Current return path for the low-side MOSFET gate driver. Connect
the VSSP pin to the source of the low-side MOSFET through a low
impedance path, preferably in parallel with the trace connecting
the LGATE pin to the gate of the low-side MOSFET.
VR_ON
Voltage regulator enable input. A high level logic signal on this
pin enables the regulator.
DPRSLPVR
LGATE (for ISL62881)
Output of the low-side MOSFET gate driver. Connect the LGATE
pin to the gate of the low-side MOSFET.
LGATEa (for ISL62881B)
Output of the low-side MOSFET gate driver that is always active.
Connect the LGATEa pin to the gate of the low-side MOSFET that
is active all the time.
3
A high level logic signal on this pin puts the ISL62881 in 1-phase
diode emulation mode. If RBIAS = 47kΩ (GPU VR application), this
pin also controls Vcore slew rate. Vcore slews at 5mV/µs for
DPRSLPVR = 0 and 10mV/µs for DPRSLPVR = 1. If RBIAS = 147kΩ
(CPU VR application), this pin doesn’t control Vcore slew rate.
FN6924.3
June 16, 2011
ISL62881, ISL62881B
Block Diagram
VIN VSEN
PGOOD
VR_ON
6µA 54µA
PGOOD AND
CLK_EN#
LOGIC
MODE
CONTROL
VDD
CLK_EN#
1.20V
VR_TT#
1.24V
DPRSLPVR
NTC
RBIAS
FLT
PROTECTION
VID0
ISL62881B
ONLY
VID1
VID2
VID3
WOC OC
VIN
DAC
AND
SOFT
START
CLOCK
VDAC
COMP
VID4
VW
VID5
BOOT
Σ
RTN
E/A
FB
VIN
COMP
VW
VDAC
MODULATOR
Idroop
WOC
Imon
IMON
2.5X
ISUM+
CURRENT
SENSE
ISUM-
DRIVER
UGATE
PHASE
SHOOT
THROUGH
PROTECTION
VCCP
DRIVER
LGATEA
COMP
CURRENT
COMPARATORS
VSSP
ISL62881 ONLY
60µA
DRIVER
LGATEB
OC
Σ
4
PWM CONTROL LOGIC
VID6
ADJ. OCP
THRESHOLD
COMP
ISL62881B
ONLY
GND
FN6924.3
June 16, 2011
ISL62881, ISL62881B
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V
Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
Boot to Phase Voltage (BOOT-PHASE) . . . . . . . . . . . . . . . . -0.3V to +7V(DC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V(<10ns)
Phase Voltage (PHASE) . . . . . . . . . . . . . . . . -7V (<20ns Pulse Width, 10µJ)
UGATE Voltage (UGATE) . . . . . . . . . . . . . . . . . . . . PHASE-0.3V (DC) to BOOT
. . . . . . . . . . . . . . . . . . . . . PHASE-5V (<20ns Pulse Width, 10µJ) to BOOT
LGATE Voltage (LGATE). . . . . . . . . . . . . . . . . . . . . . -0.3V (DC) to VDD + 0.3V
. . . . . . . . . . . . . . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD + 0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V)
Open Drain Outputs, PGOOD, VR_TT#, CLK_EN# . . . . . . . . . . . . . . -0.3V to +7V
Thermal Resistance (Typical, Notes 4, 5)
θJA (°C/W) θJC (°C/W)
28 Ld TQFN Package . . . . . . . . . . . . . . . . . .
40
3
32 Ld TQFN Package . . . . . . . . . . . . . . . . . .
32
3
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to 25V
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Operating Conditions: VDD = 5V, TA = -10°C to +100°C, fSW = 300kHz, unless otherwise noted. Boldface
limits apply over the operating temperature range, -10°C to +100°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6) UNITS
INPUT POWER SUPPLY
+5V Supply Current
IVDD
VR_ON = 1V
4.0
mA
VR_ON = 0V
3.2
1
µA
1
µA
Battery Supply Current
IVIN
VR_ON = 0V
VIN Input Resistance
RVIN
VR_ON = 1V
900
Power-On-Reset Threshold
PORr
VDD rising
4.35
PORf
VDD falling
4.00
No load; closed loop, active mode range
VID = 0.75V to 1.50V
-0.5
kΩ
4.5
4.15
V
V
SYSTEM AND REFERENCES
System Accuracy
%Error (VCC_CORE)
%
VID = 0.5V to 0.7375V
-8
+8
mV
VID = 0.3V to 0.4875V
-15
+15
mV
VBOOT
Maximum Output Voltage
VCC_CORE(max)
VID = [0000000]
Minimum Output Voltage
VCC_CORE(min)
VID = [1111111]
RBIAS Voltage
+0.5
1.0945 1.100 1.1055
V
1.500
V
0
V
RBIAS = 147kΩ
1.45
1.47
1.49
V
RFSET = 7kΩ, VCOMP = 1V
295
310
325
kHz
200
500
kHz
-0.15
+0.15
mV
CHANNEL FREQUENCY
Nominal Channel Frequency
fSW(nom)
Adjustment Range
AMPLIFIERS
IFB = 0A
Current-Sense Amplifier Input
Offset
Error Amp DC Gain
Av0
Error Amp Gain-Bandwidth
Product
GBW
5
CL = 20pF
90
dB
18
MHz
FN6924.3
June 16, 2011
ISL62881, ISL62881B
Electrical Specifications Operating Conditions: VDD = 5V, TA = -10°C to +100°C, fSW = 300kHz, unless otherwise noted. Boldface
limits apply over the operating temperature range, -10°C to +100°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6) UNITS
POWER GOOD AND PROTECTION MONITORS
PGOOD Low Voltage
VOL
IPGOOD = 4mA
PGOOD Leakage Current
IOH
PGOOD = 3.3V
-1
PGOOD Delay
tpgd
CLK_ENABLE# LOW to PGOOD HIGH
6.3
0.26
0.4
V
1
µA
7.6
8.9
ms
1.5
Ω
UGATE DRIVER
UGATE Pull-Up Resistance
RUGPU
200mA Source Current
1.0
UGATE Source Current
IUGSRC
BOOT - UGATE = 2.5V
2.0
UGATE Sink Resistance
RUGPD
250mA Sink Current
1.0
UGATE Sink Current
IUGSNK
UGATE - PHASE = 2.5V
2.0
LGATE Pull-Up Resistance
RLGPU
250mA Source Current
1.0
LGATE Source Current
ILGSRC
VCCP - LGATE = 2.5V
2.0
LGATE Sink Resistance
RLGPD
250mA Sink Current
0.5
A
1.5
Ω
A
LGATE DRIVER For ISL62881
1.5
Ω
A
0.9
Ω
LGATE Sink Current
ILGSNK
LGATE - VSSP = 2.5V
4.0
A
UGATE to LGATE Deadtime
tUGFLGR
UGATE falling to LGATE rising, no load
23
ns
LGATE to UGATE Deadtime
tLGFUGR
LGATE falling to UGATE rising, no load
28
ns
LGATE DRIVERS For ISL62881B
LGATEa and b Pull-Up Resistance
RLGPU
250mA Source Current
2.0
1.0
3
Ω
1.8
Ω
LGATEa and b Source Current
ILGSRC
VCCP - LGATEa and b = 2.5V
LGATEa and b Sink Resistance
RLGPD
250mA Sink Current
LGATEa and b Sink Current
ILGSNK
LGATEa and b - VSSP = 2.5V
2.0
A
UGATE to LGATEa and b
Deadtime
tUGFLGR
UGATE falling to LGATEa and b rising, no load
23
ns
LGATEa and b to UGATE
Deadtime
tLGFUGR
LGATEa and b falling to UGATE rising, no load
28
ns
1
A
BOOTSTRAP DIODE
Forward Voltage
VF
PVCC = 5V, IF = 2mA
0.58
V
Reverse Leakage
IR
VR = 25V
0.2
µA
PROTECTION
Overvoltage Threshold
OVH
VSEN rising above setpoint for >1ms
Severe Overvoltage Threshold
OVHS
VSEN rising for >2µs
OC Threshold Offset
Undervoltage Threshold
UVf
150
200
240
mV
1.525
1.55
1.575
V
ISUM- pin current
8.2
10.1
12
µA
VSEN falling below setpoint for >1.2ms
-355
-295
-235
mV
0.3
V
0.3
V
LOGIC THRESHOLDS
VR_ON Input Low
VIL(1.0V)
VR_ON Input High
VIH(1.0V)
VID0-VID6 and DPRSLPVR Input
Low
VIL(1.0V)
VID0-VID6 and DPRSLPVR Input
High
VIH(1.0V)
0.7
V
0.7
V
THERMAL MONITOR (For ISL62881B)
NTC Source Current
NTC = 1.3V
6
53
60
67
µA
FN6924.3
June 16, 2011
ISL62881, ISL62881B
Electrical Specifications Operating Conditions: VDD = 5V, TA = -10°C to +100°C, fSW = 300kHz, unless otherwise noted. Boldface
limits apply over the operating temperature range, -10°C to +100°C. (Continued)
PARAMETER
SYMBOL
Over-Temperature Threshold
TEST CONDITIONS
V (NTC) falling
VR_TT# Low Output Resistance
RTT
I = 20mA
CLK_EN# Low Output Voltage
VOL
I = 4mA
CLK_EN# Leakage Current
IOH
CLK_EN# = 3.3V
MIN
(Note 6)
TYP
MAX
(Note 6) UNITS
1.18
1.2
1.22
V
6.5
9
Ω
0.26
0.4
V
1
µA
CLK_EN# OUTPUT LEVELS
-1
CURRENT MONITOR
IMON Output Current
IIMON
IMON Clamp Voltage
ISUM- pin current = 20µA
108
120
132
µA
ISUM- pin current = 10µA
51
60
69
µA
ISUM- pin current = 5µA
22
30
37.5
µA
1.1
1.15
V
VIMONCLAMP
Current Sinking Capability
275
µA
-1
0
µA
-1
0
INPUTS
VR_ON Leakage Current
IVR_ON
VR_ON = 0V
VR_ON = 1V
VIDx Leakage Current
IVIDx
VIDx = 0V
0
VIDx = 1V
DPRSLPVR Leakage Current
IDPRSLPVR
DPRSLPVR = 0V
0.45
-1
DPRSLPVR = 1V
1
1
0
0.45
µA
µA
µA
µA
1
µA
6.5
mV/µs
SLEW RATE
Slew Rate (For VID Change)
SR
5
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7
FN6924.3
June 16, 2011
ISL62881, ISL62881B
Gate Driver Timing Diagram
PWM
tLGFUGR
tFU
tRU
1V
UGATE
1V
LGATE
tRL
tFL
tUGFLGR
Simplified Application Circuits
V+5
VD D
R B IA S
V+5
VIN
VC C P
VIN
R B IA S
PG O O D
C LK_EN #
VID <0:6>
D PR SLPVR
VR _O N
PG O O D
C LK _EN #
VID S
D PR SLPVR
VR _O N
VW
ISL 62881
BOOT
RFSET
V IN
U G A TE
L
PH A SE
VO
COMP
FB
LG A TE
VSSP
R SUM
R DROOP
VSEN
ISU M +
CN
R TN
°C
CIS
R IM O N
IM O N
RN
RIS
VC C S EN SE
VSS S EN SE
RI
IM O N
ISU M (B O TTO M PA D )
VSS
FIGURE 1. ISL62881 TYPICAL APPLICATION CIRCUIT USING DCR SENSING
8
FN6924.3
June 16, 2011
ISL62881, ISL62881B
Simplified Application Circuits (Continued)
V+5
VDD
R BIAS
V+5
VIN
VCCP
VIN
RBIAS
PGOOD
CLK_EN#
VIDS
DPRSLPVR
VR_ON
PGOOD
CLK_EN#
VID<0:6>
DPRSLPVR
VR_ON
VW
ISL62881
BOOT
RFSET
VIN
UGATE
L
PHASE
RSEN
VO
COMP
FB
LGATE
VSSP
R DROOP
VSEN
R SUM
ISUM+
RIS
VCC SENSE
VSS SENSE
CIS
R IMON
IMON
CN
RTN
RI
IMON
ISUM(BOTTOM PAD)
VSS
FIGURE 2. ISL62881 TYPICAL APPLICATION CIRCUIT USING RESISTOR SENSING
9
FN6924.3
June 16, 2011
ISL62881, ISL62881B
Simplified Application Circuits (Continued)
R B IA S
V+5
V +5
V IN
V DD
R BIA S
VC C P
V IN
N TC
OC
V R _TT#
PGOOD
C LK _EN #
V ID <0:6>
D P R S L PV R
V R _O N
V R _TT#
PGOOD
C LK _E N #
V ID S
D PR S LP VR
V R _O N
VW
IS L62881B
V IN
BOOT
RFSET
UGATE
COMP
FB
L
PHASE
LG A TE B
LG A TE A
V SS P
VO
R SU M
R DR O O P
V SE N
IS U M +
CN
R TN
OC
CIS
R IM O N
IM O N
RN
RIS
V C C S EN S E
V SS S EN S E
RI
IM O N
IS U M GND
FIGURE 3. ISL62881B TYPICAL APPLICATION CIRCUIT USING DCR SENSING
10
FN6924.3
June 16, 2011
ISL62881, ISL62881B
Simplified Application Circuits (Continued)
R BIAS
V+5
V+5
VIN
V DD
R BIAS
VCCP
VIN
NTC
OC
VR_TT#
PGOOD
CLK_EN#
VID<0:6>
DPRSLPVR
VR_ON
VR_TT#
PGOOD
CLK_EN#
VIDS
DPRSLPVR
VR_ON
VW
ISL62881B
VIN
BOOT
RFSET
UGATE
COMP
FB
L
PHASE
LGATEB
LGATEA
VSSP
RSEN
VO
R DROOP
VSEN
RSUM
ISUM+
RIS
VCC SENSE
VSS SENSE
CN
RTN
CIS
R IMON
IMON
RI
IMON
ISUMVSS
FIGURE 4. ISL62881B TYPICAL APPLICATION CIRCUIT USING RESISTOR SENSING
11
FN6924.3
June 16, 2011
ISL62881, ISL62881B
The ISL62881 is a single-phase regulator implementing Intel®
IMVP-6.5™ protocol. It uses Intersil patented R3™(Robust Ripple
Regulator™) modulator. The R3™ modulator combines the best
features of fixed frequency PWM and hysteretic PWM while
eliminating many of their shortcomings. Figure 5 conceptually
shows the ISL62881 R3™ modulator circuit, and Figure 6 shows
the operation principles.
Theory of Operation
Multiphase R3™ Modulator
MASTER CLOCK CIRCUIT
VW
COMP
VCRM
MASTER
CLOCK
CLOCK
A current source flows from the VW pin to the COMP pin, creating
a voltage window set by the resistor between between the two
pins. This voltage window is called VW window in the following
discussion.
CRM
GMVO
SLAVE CIRCUIT
VW
CLOCK
VCRS
S PWM
Q
R
PHASE
L
IL
VO
CO
GM
CRS
FIGURE 5. R3™ MODULATOR CIRCUIT
VW
H YS T ER E TIC
W IN D O W
VCRM
COMP
Inside the IC, the modulator uses the master clock circuit to
generate the clocks for the slave circuit. The modulator
discharges the ripple capacitor Crm with a current source equal
to gmVo, where gm is a gain factor. Crm voltage Vcrm is a
sawtooth waveform traversing between the VW and COMP
voltages. It resets to VW when it hits COMP, and generates a
one-shot clock signal.
The slave circuit has its own ripple capacitor Crs, whose voltage
mimics the inductor ripple current. A gm amplifier converts the
inductor voltage into a current source to charge and discharge
Crs. The slave circuit turns on its PWM pulse upon receiving the
clock signal, and the current source charges Crs. When Crs
voltage VCrs hits VW, the slave circuit turns off the PWM pulse,
and the current source discharges Crs.
Since the ISL62881 works with Vcrs, which is large-amplitude
and noise-free synthesized signal, the ISL62881 achieves lower
phase jitter than conventional hysteretic mode and fixed PWM
mode controllers. Unlike conventional hysteretic mode
converters, the ISL62881 has an error amplifier that allows the
controller to maintain a 0.5% output voltage accuracy.
C LO C K
PW M
VW
VCRS
FIGURE 6. R3™ MODULATOR OPERATION PRINCIPLES IN STEADY
STATE
VW
COMP
VCRM
Figure 7 shows the operation principles during load insertion
response. The COMP voltage rises during load insertion,
generating the clock signal more quickly, so the PWM pulse turns
on earlier, increasing the effective switching frequency, which
allows for higher control loop bandwidth than conventional fixed
frequency PWM controllers. The VW voltage rises as the COMP
voltage rises, making the PWM pulse wider. During load release
response, the COMP voltage falls. It takes the master clock
circuit longer to generate the next clock signal so the PWM pulse
is held off until needed. The VW voltage falls as the VW voltage
falls, reducing the current PWM pulse width. This kind of
behavior gives the ISL62881 excellent response speed.
CLOCK
PWM
VW
VCRS
FIGURE 7. R3™ MODULATOR OPERATION PRINCIPLES IN LOAD
INSERTION RESPONSE
12
FN6924.3
June 16, 2011
ISL62881, ISL62881B
Diode Emulation and Period Stretching
PHASE
UGATE
window size, therefore is the same, making the inductor current
triangle the same in the three cases. The ISL62881 clamps the
ripple capacitor voltage Vcrs in DE mode to make it mimic the
inductor current. It takes the COMP voltage longer to hit Vcrs,
naturally stretching the switching period. The inductor current
triangles move further apart from each other such that the inductor
current average value is equal to the load current. The reduced
switching frequency helps increase light load efficiency.
Start-up Timing
LGATE
With the controller's VDD voltage above the POR threshold, the
start-up sequence begins when VR_ON exceeds the 3.3V logic
high threshold.
IL
FIGURE 8. DIODE EMULATION
ISL62881 can operate in diode emulation (DE) mode to improve
light load efficiency. In DE mode, the low-side MOSFET conducts
when the current is flowing from source to drain and doesn’t not
allow reverse current, emulating a diode. As shown in Figure 8,
when LGATE is on, the low-side MOSFET carries current, creating
negative voltage on the phase node due to the voltage drop
across the ON-resistance. The ISL62881 monitors the current
through monitoring the phase node voltage. It turns off LGATE
when the phase node voltage reaches zero to prevent the
inductor current from reversing the direction and creating
unnecessary power loss.
If the load current is light enough, as Figure 9 shows, the inductor
current will reach and stay at zero before the next phase node
pulse, and the regulator is in discontinuous conduction mode
(DCM). If the load current is heavy enough, the inductor current
will never reach 0A, and the regulator is in CCM although the
controller is in DE mode.
CCM/DCM BOUNDARY
VW
Figure 10 shows the typical start-up timing when the ISL62881 is
configured for CPU VR application. The ISL62881 uses digital
soft-start to ramp up DAC to the boot voltage of 1.1V at about
2.5mV/µs. Once the output voltage is within 10% of the boot voltage
for 13 PWM cycles (43µs for frequency = 300kHz), CLK_EN# is
pulled low and DAC slews at 5mV/µs to the voltage set by the VID
pins. PGOOD is asserted high in approximately 7ms. Similar results
occur if VR_ON is tied to VDD, with the soft-start sequence starting
120µs after VDD crosses the POR threshold.
Figure 11 shows the typical start-up timing when the ISL62881 is
configured for GPU VR application. The ISL62881 uses digital
soft-start to ramp-up DAC to the voltage set by the VID pins at
5mV/µs. Once the output voltage is within 10% of the target voltage
for 13 PWM cycles (43µs for frequency = 300kHz), CLK_EN# is
pulled low. PGOOD is asserted high in approximately 7ms. Similar
results occur if VR_ON is tied to VDD, with the soft-start sequence
starting 120µs after VDD crosses the POR threshold.
VDD
5mV/µs
VR_ON
2.5mV/µs
90% VBOOT
VCRS
800µs
VID
COMMAND
VOLTAGE
DAC
13 SWITCHING CYCLES
IL
CLK_EN#
VW
LIGHT DCM
~7ms
PGOOD
VCRS
FIGURE 10. SOFT-START WAVEFORMS FOR CPU VR APPLICATION
IL
DEEP DCM
VDD
VW
VR_ON
VCRS
5mV/µs
90%
120µs
VID COMMAND VOLTAGE
DAC
IL
13 SWITCHING CYCLES
FIGURE 9. PERIOD STRETCHING
Figure 9 shows the operation principle in diode emulation mode at
light load. The load gets incrementally lighter in the three cases
from top to bottom. The PWM on-time is determined by the VW
13
CLK_EN#
~7ms
PGOOD
FIGURE 11. SOFT-START WAVEFORMS FOR GPU VR APPLICATION
FN6924.3
June 16, 2011
ISL62881, ISL62881B
Voltage Regulation and Load Line
Implementation
TABLE 1. VID TABLE (Continued)
After the start sequence, the ISL62881 regulates the output
voltage to the value set by the VID inputs per Table 1. The
ISL62881 will control the no-load output voltage to an accuracy of
±0.5% over the range of 0.75V to 1.5V. A differential amplifier
allows voltage sensing for precise voltage regulation at the
microprocessor die.
TABLE 1. VID TABLE
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VO
(V)
0
1
0
0
0
1
1
1.0625
0
1
0
0
1
0
0
1.0500
0
1
0
0
1
0
1
1.0375
0
1
0
0
1
1
0
1.0250
0
1
0
0
1
1
1
1.0125
1
0
1
0
0
0
1.0000
VID5
VID4
VID3
VID2
VID1
VID0
VO
(V)
0
VID6
0
1
0
1
0
0
1
0.9875
0
0
0
0
0
0
0
1.5000
0
1
0
1
0
1
0
0.9750
0
0
0
0
0
0
1
1.4875
0
1
0
1
0
1
1
0.9625
0
0
0
0
0
1
0
1.4750
0
1
0
1
1
0
0
0.9500
0
0
0
0
0
1
1
1.4625
0
1
0
1
1
0
1
0.9375
0
0
0
0
1
0
0
1.4500
0
1
0
1
1
1
0
0.9250
0
0
0
0
1
0
1
1.4375
0
1
0
1
1
1
1
0.9125
0
0
0
0
1
1
0
1.4250
0
1
1
0
0
0
0
0.9000
0
0
0
0
1
1
1
1.4125
0
1
1
0
0
0
1
0.8875
0
0
0
1
0
0
0
1.4000
0
1
1
0
0
1
0
0.8750
0
0
0
1
0
0
1
1.3875
0
1
1
0
0
1
1
0.8625
0
0
0
1
0
1
0
1.3750
0
1
1
0
1
0
0
0.8500
0
0
0
1
0
1
1
1.3625
0
1
1
0
1
0
1
0.8375
0
0
0
1
1
0
0
1.3500
0
1
1
0
1
1
0
0.8250
0
0
0
1
1
0
1
1.3375
0
1
1
0
1
1
1
0.8125
0
0
0
1
1
1
0
1.3250
0
1
1
1
0
0
0
0.8000
0
0
0
1
1
1
1
1.3125
0
1
1
1
0
0
1
0.7875
0
0
1
0
0
0
0
1.3000
0
1
1
1
0
1
0
0.7750
0
0
1
0
0
0
1
1.2875
0
1
1
1
0
1
1
0.7625
0
0
1
0
0
1
0
1.2750
0
1
1
1
1
0
0
0.7500
0
0
1
0
0
1
1
1.2625
0
1
1
1
1
0
1
0.7375
0
0
1
0
1
0
0
1.2500
0
1
1
1
1
1
0
0.7250
0
0
1
0
1
0
1
1.2375
0
1
1
1
1
1
1
0.7125
0
0
1
0
1
1
0
1.2250
1
0
0
0
0
0
0
0.7000
0
0
1
0
1
1
1
1.2125
1
0
0
0
0
0
1
0.6875
0
0
1
1
0
0
0
1.2000
1
0
0
0
0
1
0
0.6750
0
0
1
1
0
0
1
1.1875
1
0
0
0
0
1
1
0.6625
0
0
1
1
0
1
0
1.1750
1
0
0
0
1
0
0
0.6500
0
0
1
1
0
1
1
1.1625
1
0
0
0
1
0
1
0.6375
0
0
1
1
1
0
0
1.1500
1
0
0
0
1
1
0
0.6250
0
0
1
1
1
0
1
1.1375
1
0
0
0
1
1
1
0.6125
0
0
1
1
1
1
0
1.1250
1
0
0
1
0
0
0
0.6000
0
0
1
1
1
1
1
1.1125
1
0
0
1
0
0
1
0.5875
0
1
0
0
0
0
0
1.1000
1
0
0
1
0
1
0
0.5750
0
1
0
0
0
0
1
1.0875
1
0
0
1
0
1
1
0.5625
0
1
0
0
0
1
0
1.0750
1
0
0
1
1
0
0
0.5500
14
FN6924.3
June 16, 2011
ISL62881, ISL62881B
TABLE 1. VID TABLE (Continued)
TABLE 1. VID TABLE (Continued)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VO
(V)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VO
(V)
1
0
0
1
1
0
1
0.5375
1
1
1
0
1
1
1
0.0125
1
0
0
1
1
1
0
0.5250
1
1
1
1
0
0
0
0.0000
1
0
0
1
1
1
1
0.5125
1
1
1
1
0
0
1
0.0000
1
0
1
0
0
0
0
0.5000
1
1
1
1
0
1
0
0.0000
1
0
1
0
0
0
1
0.4875
1
1
1
1
0
1
1
0.0000
1
0
1
0
0
1
0
0.4750
1
1
1
1
1
0
0
0.0000
1
0
1
0
0
1
1
0.4625
1
1
1
1
1
0
1
0.0000
1
0
1
0
1
0
0
0.4500
1
1
1
1
1
1
0
0.0000
1
0
1
0
1
0
1
0.4375
1
1
1
1
1
1
1
0.0000
1
0
1
0
1
1
0
0.4250
1
0
1
0
1
1
1
0.4125
1
0
1
1
0
0
0
0.4000
1
0
1
1
0
0
1
0.3875
1
0
1
1
0
1
0
RDROOP
VCC SENSE
FB
0.3750
1
0
1
1
0
1
1
0.3625
1
0
1
1
1
0
0
0.3500
1
0
1
1
1
0
1
0.3375
1
0
1
1
1
1
0
0.3250
1
0
1
1
1
1
1
0.3125
V DROOP
IDROOP
E/A
COMP
Σ
VR LOCAL VO
“CATCH” RESISTOR
VIDS
VID<0:6>
DAC
VDAC
RTN
VSSSENSE
INTERNAL TO IC
X1
VSS
1
1
0
0
0
0
0
0.3000
1
1
0
0
0
0
1
0.2875
1
1
0
0
0
1
0
0.2750
1
1
0
0
0
1
1
0.2625
1
1
0
0
1
0
0
0.2500
1
1
0
0
1
0
1
0.2375
1
1
0
0
1
1
0
0.2250
1
1
0
0
1
1
1
0.2125
1
1
0
1
0
0
0
0.2000
1
1
0
1
0
0
1
0.1875
1
1
0
1
0
1
0
0.1750
1
1
0
1
0
1
1
0.1625
1
1
0
1
1
0
0
0.1500
1
1
0
1
1
0
1
0.1375
1
1
0
1
1
1
0
0.1250
1
1
0
1
1
1
1
0.1125
1
1
1
0
0
0
0
0.1000
1
1
1
0
0
0
1
0.0875
1
1
1
0
0
1
0
0.0750
1
1
1
0
0
1
1
0.0625
1
1
1
0
1
0
0
0.0500
1
1
1
0
1
0
1
0.0375
Idroop flows through resistor Rdroop and creates a voltage drop,
as shown in Equation 2.
1
1
1
0
1
1
0
0.0250
V droop = R droop × I droop
15
“CATCH”
RESISTOR
FIGURE 12. DIFFERENTIAL SENSING AND LOAD LINE
IMPLEMENTATION
As the load current increases from zero, the output voltage will
droop from the VID table value by an amount proportional to the
load current to achieve the load line. The ISL62881 can sense
the inductor current through the intrinsic DC Resistance (DCR)
resistance of the inductors as shown in Figure 1 or through
resistors in series with the inductors as shown in Figure 2. In both
methods, capacitor Cn voltage represents the inductor total
currents. A droop amplifier converts Cn voltage into an internal
current source with the gain set by resistor Ri. The current source
is used for load line implementation, current monitor and
overcurrent protection.
Figure 12 shows the load line implementation. The ISL62881
drives a current source Idroop out of the FB pin, described by
Equation 1.
2xV Cn
I droop = ---------------Ri
(EQ. 1)
When using inductor DCR current sensing, a single NTC element
is used to compensate the positive temperature coefficient of the
copper winding thus sustaining the load line accuracy with
reduced cost.
(EQ. 2)
FN6924.3
June 16, 2011
ISL62881, ISL62881B
Vdroop is the droop voltage required to implement load line.
Changing Rdroop or scaling Idroop can both change the load line
slope. Since Idroop also sets the overcurrent protection level, it is
recommended to first scale Idroop based on OCP requirement,
then select an appropriate Rdroop value to obtain the desired
load line slope.
Modes of Operation
TABLE 2. ISL62881 MODES OF OPERATION
CONFIGURATION
CPU VR Application
Differential Sensing
Figure 12 also shows the differential voltage sensing scheme.
VCCSENSE and VSSSENSE are the remote voltage sensing signals
from the processor die. A unity gain differential amplifier senses
the VSSSENSE voltage and adds it to the DAC output. The error
amplifier regulates the inverting and the non-inverting input
voltages to be equal, therefore:
VCC SENSE + V
droop
= V DAC + VSS SENSE
(EQ. 3)
Rewriting Equation 3 and substituting Equation 2 gives:
VCC SENSE – VSS SENSE = V DAC – R droop × I droop
(EQ. 4)
The VCCSENSE and VSSSENSE signals come from the processor
die. The feedback will be open circuit in the absence of the
processor. As shown in Figure 12, it is recommended to add a
“catch” resistor to feed the VR local output voltage back to the
compensator, and add another “catch” resistor to connect the VR
local output ground to the RTN pin. These resistors, typically
10Ω~100Ω, will provide voltage feedback if the system is
powered up without a processor installed.
CCM Switching Frequency
The RFSET resistor between the COMP and the VW pins sets the
VW windows size, which therefore sets the switching frequency.
When the ISL62881 is in continuous conduction mode (CCM), the
switching frequency is not absolutely constant due to the nature
of the R3™ modulator. As explained in “Multiphase R3™
Modulator” on page 12, the effective switching frequency will
increase during load insertion and will decrease during load
release to achieve fast response. On the other hand, the
switching frequency is relatively constant at steady state.
Variation is expected when the power stage condition, such as
input voltage, output voltage, load, etc. changes. The variation is
usually less than 15% and doesn’t have any significant effect on
output voltage ripple magnitude. Equation 5 gives an estimate of
the frequency-setting resistor Rfset value. 8kΩ RFSET gives
approximately 300kHz switching frequency. Lower resistance
gives higher switching frequency.
16
OPERATIONAL
MODE
VOLTAGE
SLEW RATE
5mV/µs
0
1-phase CCM
1
1-phase DE
0
1-phase CCM
5mV/µs
1
1-phase DE
10mV/µs
Table 2 shows the ISL62881 operational modes, programmed by
the logic status of the DPRSLPVR pin. The ISL62881 enters
1-phase DE mode when there is DPRSLPVR = 1.
When the ISL62881 is configured for GPU VR application,
DPRSLPVR logic status also controls the output voltage slew
rate. The slew rate is 5mV/µs for DPRSLPVR = 0 and is 10mV/µs
for DPRSLPVR = 1.
Dynamic Operation
Equation 4 is the exact equation required for load line
implementation.
R FSET ( kΩ ) = ( Period ( μs ) – 0.29 ) × 2.65
GPU VR Application
DPRSLPVR
(EQ. 5)
When the ISL62881 is configured for CPU VR application, it
responds to VID changes by slewing to the new voltage at
5mV/µs slew rate. As the output approaches the VID command
voltage, the dv/dt moderates to prevent overshoot. Geyserville-III
transitions commands one LSB VID step (12.5mV) every 2.5µs,
controlling the effective dv/dt at 5mv/µs. The ISL62881 is
capable of 5mV/µs slew rate.
When the ISL62881 is configured for GPU VR application, it
responds to VID changes by slewing to the new voltage at a slew
rate set by the logic status on the DPRSLPVR pin. The slew rate is
5mV/µs when DPRSLPVR = 0 and is 10mV/µs when
DPRSLPVR = 1.
When the ISL62881 is in DE mode, it will actively drive the output
voltage up when the VID changes to a higher value. It’ll resume
DE mode operation after reaching the new voltage level. If the
load is light enough to warrant DCM, it will enter DCM after the
inductor current has crossed zero for four consecutive cycles. The
ISL62881 will remain in DE mode when the VID changes to a
lower value. The output voltage will decay to the new value and
the load will determine the slew rate.
The R3™ modulator intrinsically has voltage feed forward. The
output voltage is insensitive to a fast slew rate input voltage change.
Protections
The ISL62881 provides overcurrent, undervoltage, and overvoltage
protections.
The ISL62881 determines overcurrent protection (OCP) by
comparing the average value of the droop current Idroop with an
internal current source threshold. It declares OCP when Idroop is
above the threshold for 120µs. A resistor Rcomp from the COMP
pin to GND programs the OCP current source threshold, as well as
the overshoot reduction function (to be discussed in later sections),
as Table 3 shows. It is recommended to use the nominal Rcomp
value. The ISL62881 detects the Rcomp value at the beginning of
start-up, and sets the internal OCP threshold accordingly. It
remembers the Rcomp value until the VR_ON signal drops below
the POR threshold.
FN6924.3
June 16, 2011
ISL62881, ISL62881B
TABLE 3. ISL62881 OCP THRESHOLD AND OVERSHOOT REDUCTION
FUNCTION
Rcomp
NOMINAL
(kΩ)
MAX
(kΩ)
OCP
THRESHOLD
(µA)
OVERSHOOT
REDUCTION
FUNCTION
none
none
20
Disabled
305
400
410
22.67
205
235
240
20.67
155
165
170
18
104
120
130
20
78
85
90
22.67
62
66
68
20.67
45
50
55
18
MIN
(kΩ)
Enabled
The default OCP threshold is the value when Rcomp is not
populated. It is recommended to scale the droop current Idroop
such that the default OCP threshold gives approximately the
desired OCP level, then use Rcomp to fine tune the OCP level if
necessary.
For overcurrent condition above 2.5x the OCP level, the PWM
output will immediately shut off and PGOOD will go low to
maximize protection. This protection is also referred to as
way-overcurrent protection or fast-overcurrent protection, for
short-circuit protections.
The ISL62881 will declare undervoltage (UV) fault and latch-off if
the output voltage is less than the VID set value by 300mV or
more for 1ms. It’ll turn off the PWM output and de-assert
PGOOD.
The ISL62881 has two levels of overvoltage protections. The first
level of overvoltage protection is referred to as PGOOD
overvoltage protection. If the output voltage exceeds the VID set
value by +200mV for 1ms, the ISL62881 will declare a fault and
de-assert PGOOD.
The ISL62881 takes the same actions for all of the above fault
protections: de-assertion of PGOOD and turn-off of the high-side
and low-side power MOSFETs. Any residual inductor current will
decay through the MOSFET body diodes. These fault conditions
can be reset by bringing VR_ON low or by bringing VDD below the
POR threshold. When VR_ON and VDD return to their high
operating levels, a soft-start will occur.
The second level of overvoltage protection is different. If the
output voltage exceeds 1.55V, the ISL62881 will immediately
declare an OV fault, de-assert PGOOD, and turn on the low-side
power MOSFETs. The low-side power MOSFETs remain on until
the output voltage is pulled down below 0.85V when all power
MOSFETs are turned off. If the output voltage rises above 1.55V
again, the protection process is repeated. This behavior provides
the maximum amount of protection against shorted high-side
power MOSFETs while preventing output ringing below ground.
Resetting VR_ON cannot clear the 1.55V OVP. Only resetting VDD
will clear it. The 1.55V OVP is active all the time when the
controller is enabled, even if one of the other faults have been
declared. This ensures that the processor is protected against
high-side power MOSFET leakage while the MOSFETs are
commanded off.
17
Table 4 summarizes the fault protections.
TABLE 4. FAULT PROTECTION SUMMARY
FAULT TYPE
FAULT DURATION
BEFORE
PROTECTION
Overcurrent
120µs
Way-Overcurrent
(2.5xOC)
<2µs
Overvoltage +200mV
1ms
PROTECTION
ACTION
FAULT
RESET
PWM tri-state, VR_ON
toggle or
PGOOD
VDD toggle
latched low
Undervoltage -300mV
Overvoltage 1.55V
Immediately
Low-side
VDD toggle
MOSFET on
until Vcore
<0.85V, then
PWM tri-state,
PGOOD
latched low.
Current Monitor
The ISL62881 provides the current monitor function. The IMON
pin outputs a high-speed analog current source that is 3 times of
the droop current flowing out of the FB pin. Thus as shown by
Equation 6.
I IMON = 3 × I droop
(EQ. 6)
As Figures 1 and 2 show, a resistor Rimon is connected to the
IMON pin to convert the IMON pin current to voltage. A capacitor
can be paralleled with Rimon to filter the voltage information. The
IMVP-6.5™ specification requires that the IMON voltage
information be referenced to VSSSENSE.
The IMON pin voltage range is 0V to 1.1V. A clamp circuit
prevents the IMON pin voltage from going above 1.1V.
Adaptive Body Diode Conduction Time
Reduction
In DCM, the controller turns off the low-side MOSFET when the
inductor current approaches zero. During on-time of the low-side
MOSFET, phase voltage is negative and the amount is the
MOSFET RDS(ON) voltage drop, which is proportional to the
inductor current. A phase comparator inside the controller
monitors the phase voltage during on-time of the low-side
MOSFET and compares it with a threshold to determine the
zero-crossing point of the inductor current. If the inductor current
has not reached zero when the low-side MOSFET turns off, it’ll
flow through the low-side MOSFET body diode, causing the phase
node to have a larger voltage drop until it decays to zero. If the
inductor current has crossed zero and reversed the direction
when the low-side MOSFET turns off, it’ll flow through the
high-side MOSFET body diode, causing the phase node to have a
spike until it decays to zero. The controller continues monitoring
the phase voltage after turning off the low-side MOSFET and adjusts
the phase comparator threshold voltage accordingly in iterative steps
such that the low-side MOSFET body diode conducts for
approximately 40ns to minimize the body diode-related loss.
FN6924.3
June 16, 2011
ISL62881, ISL62881B
Overshoot Reduction Function
The ISL62881 has an optional overshoot reduction function,
enabled or disabled by the resistor from the COMP pin to GND, as
shown in Table 3.
When a load release occurs, the energy stored in the inductors
will dump to the output capacitor, causing output voltage
overshoot. The inductor current freewheels through the low-side
MOSFET during this period of time. The overshoot reduction
function turns off the low-side MOSFET during the output voltage
overshoot, forcing the inductor current to freewheel through the
low-side MOSFET body diode. Since the body diode voltage drop
is much higher than MOSFET RDS(ON) voltage drop, more energy
is dissipated on the low-side MOSFET therefore the output
voltage overshoot is lower.
If the overshoot reduction function is enabled, the ISL62881
monitors the COMP pin voltage to determine the output voltage
overshoot condition. The COMP voltage will fall and hit the clamp
voltage when the output voltage overshoots. The ISL62881 will
turn off LGATE when COMP is being clamped. The low-side
MOSFET in the power stage will be turned off. When the output
voltage has reached its peak and starts to come down, the COMP
voltage starts to rise and is no longer clamped. The ISL62881 will
resume normal PWM operation.
While the overshoot reduction function reduces the output
voltage overshoot, energy is dissipated on the low-side MOSFET,
causing additional power loss. The more frequent the transient
event, the more power loss is dissipated on the low-side MOSFET.
The MOSFET may face severe thermal stress when transient
events happen at a high repetitive rate. User discretion is advised
when this function is enabled.
Key Component Selection
RBIAS
The ISL62881 uses a resistor (1% or better tolerance is
recommended) from the RBIAS pin to GND to establish highly
accurate reference current sources inside the IC. Using
RBIAS = 147kΩ sets the controller for CPU core application and
using RBIAS = 47kΩ sets the controller for GPU core application.
Do not connect any other components to this pin. Do not connect
any capacitor to the RBIAS pin as it will create instability.
Care should be taken in layout that the resistor is placed very
close to the RBIAS pin and that a good quality signal ground is
connected to the opposite side of the RBIAS resistor.
Ris and Cis
As Figures 1 and 2 show, the ISL62881 needs the
Ris - Cis network across the ISUM+ and the ISUM- pins to stabilize
the droop amplifier. The preferred values are Ris = 82.5Ω and
Cis = 0.01µF. Slight deviations from the recommended values are
acceptable. Large deviations may result in instability.
18
Inductor DCR Current-Sensing Network
PHASE
ISUM+
RSUM
L
RNTCS
RP
DCR
+
CN VCN
-
RNTC
RI
ISUM-
IO
FIGURE 13. DCR CURRENT-SENSING NETWORK
Figure 13 shows the inductor DCR current-sensing network for a
2-phase solution. An inductor current flows through the DCR and
creates a voltage drop. The inductor has a resistors in Rsum
connected to the phase-node-side pad and a PCB trace
connected to the output-side pad to accurately sense the
inductor current by sensing the DCR voltage drop. The sensed
current information is fed to the NTC network (consisting of
Rntcs, Rntc and Rp) and capacitor Cn. Rntc is a negative
temperature coefficient (NTC) thermistor, used to
temperature-compensate the inductor DCR change. The inductor
current information is presented to the capacitor Cn. Equations 7
through 11 describe the frequency-domain relationship between
inductor total current Io(s) and Cn voltage VCn(s):
R ntcnet
⎛
⎞
V Cn ( s ) = ⎜ ----------------------------------------- × DCR⎟ × I o ( s ) × A cs ( s )
R
+
R
⎝ ntcnet
⎠
sum
( R ntcs + R ntc ) × R p
R ntcnet = --------------------------------------------------R ntcs + R ntc + R p
s
1 + -----ωL
A cs ( s ) = ---------------------s
1 + -----------ω sns
(EQ. 7)
(EQ. 8)
(EQ. 9)
DCR
ω L = -----------L
(EQ. 10)
1
ω sns = -----------------------------------------------------R ntcnet × R sum
----------------------------------------- × C n
R ntcnet + R sum
(EQ. 11)
Transfer function Acs(s) always has unity gain at DC. The inductor
DCR value increases as the winding temperature increases,
giving higher reading of the inductor DC current. The NTC Rntc
values decreases as its temperature decreases. Proper
selections of Rsum, Rntcs, Rp and Rntc parameters ensure that
VCn represents the inductor total DC current over the
temperature range of interest.
FN6924.3
June 16, 2011
ISL62881, ISL62881B
There are many sets of parameters that can properly
temperature-compensate the DCR change. Since the NTC
network and the Rsum resistors form a voltage divider, Vcn is
always a fraction of the inductor DCR voltage. It is recommended
to have a higher ratio of Vcn to the inductor DCR voltage, so the
droop circuit has higher signal level to work with.
A typical set of parameters that provide good temperature
compensation are: Rsum = 3.65kΩ, Rp = 11kΩ, Rntcs = 2.61kΩ
and Rntc = 10kΩ (ERT-J1VR103J). The NTC network parameters
may need to be fine tuned on actual boards. One can apply full
load DC current and record the output voltage reading
immediately; then record the output voltage reading again when
the board has reached the thermal steady state. A good NTC
network can limit the output voltage drift to within 2mV. It is
recommended to follow the Intersil evaluation board layout and
current-sensing network parameters to minimize engineering
time.
For example, given Rsum = 3.65kΩ, Rp = 11kΩ, Rntcs = 2.61kΩ,
Rntc = 10kΩ, DCR = 1.1mΩ and L = 0.45µH, Equation 12 gives
Cn = 0.18µF.
Assuming the compensator design is correct, Figure 14 shows
the expected load transient response waveforms if Cn is correctly
selected. When the load current Icore has a square change, the
output voltage Vcore also has a square response.
If Cn value is too large or too small, VCn(s) will not accurately
represent real-time Io(s) and will worsen the transient response.
Figure 15 shows the load transient response when Cn is too
small. Vcore will sag excessively upon load insertion and may
create a system failure. Figure 16 shows the transient response
when Cn is too large. Vcore is sluggish in drooping to its final
value. There will be excessive overshoot if load insertion occurs
during this time, which may potentially hurt the CPU reliability.
iO
VCn(s) also needs to represent real-time Io(s) for the controller to
achieve good transient response. Transfer function Acs(s) has a
pole ωsns and a zero ωL. One needs to match ωL and ωsns so
Acs(s) is unity gain at all frequencies. By forcing ωL equal to ωsns
and solving for the solution, Equation 12 gives Cn value.
L
C n = -----------------------------------------------------------R ntcnet × R sum
----------------------------------------- × DCR
R ntcnet + R sum
iL
VO
(EQ. 12)
RING
BACK
FIGURE 17. OUTPUT VOLTAGE RING BACK PROBLEM
io
Vo
ISUM+
Rntcs
Cn.1
Rp
FIGURE 14. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS
Rntc
Rn
OPTIONAL
+
Cn.2 Vcn
-
Ri
ISUM-
io
Rip
Vo
Cip
OPTIONAL
FIGURE 18. OPTIONAL CIRCUITS FOR RING BACK REDUCTION
FIGURE 15. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO SMALL
io
Vo
FIGURE 16. LOAD TRANSIENT RESPONSE WHEN C n IS TOO LARGE
19
Figure 17 shows the output voltage ring back problem during
load transient response. The load current io has a fast step
change, but the inductor current iL cannot accurately follow.
Instead, iL responds in first order system fashion due to the
nature of current loop. The ESR and ESL effect of the output
capacitors makes the output voltage Vo dip quickly upon load
current change. However, the controller regulates Vo according to
the droop current idroop, which is a real-time representation of iL;
therefore it pulls Vo back to the level dictated by iL, causing the
ring back problem. This phenomenon is not observed when the
output capacitors have very low ESR and ESL, such as all ceramic
capacitors.
FN6924.3
June 16, 2011
ISL62881, ISL62881B
Figure 18 shows two optional circuits for reduction of the ring
back. Rip and Cip form an R-C branch in parallel with Ri, providing
a lower impedance path than Ri at the beginning of io change.
Rip and Cip do not have any effect at steady state. Through
proper selection of Rip and Cip values, idroop can resemble io
rather than iL, and Vo will not ring back. The recommended value
for Rip is 100W. Cip should be determined through tuning the
load transient response waveforms on an actual board. The
recommended range for Cip is 100pF~2000pF.
Figure 19 shows the resistor current-sensing network. The
inductor has a series current-sensing resistor Rsen. Rsum and is
connected to the Rsen pad to accurately capture the inductor
current information. The Rsum feeds the sensed information to
capacitor Cn. Rsum and Cn form a a filter for noise attenuation.
Equations 13 through 15 gives VCn(s) expressions:
V Cn ( s ) = R sen × I o ( s ) × A Rsen ( s )
(EQ. 13)
Cn is the capacitor used to match the inductor time constant. It
usually takes the parallel of two (or more) capacitors to get the
desired value. Figure 18 shows that two capacitors Cn.1 and Cn.2
are in parallel. Resistor Rn is an optional component to reduce
the Vo ring back. At steady state, Cn.1 + Cn.2 provides the desired
Cn capacitance. At the beginning of io change, the effective
capacitance is less because Rn increases the impedance of the
Cn.1 branch. As Figure 15 explains, Vo tends to dip when Cn is too
small, and this effect will reduce the Vo ring back. This effect is
more pronounced when Cn.1 is much larger than Cn.2. It is also
more pronounced when Rn is bigger. However, the presence of
Rn increases the ripple of the Vn signal if Cn.2 is too small. It is
recommended to keep Cn.2 greater than 2200pF. Rn value
usually is a few ohms. Cn.1, Cn.2 and Rn values should be
determined through tuning the load transient response
waveforms on an actual board.
1
A Rsen ( s ) = ---------------------s
1 + -----------ω sns
(EQ. 14)
1
ω Rsen = --------------------------R sum × C n
(EQ. 15)
Rip and Cip form an R-C branch in parallel with Ri, providing a
lower impedance path than Ri at the beginning of io change. Rip
and Cip do not have any effect at steady state. Through proper
selection of Rip and Cip values, idroop can resemble io rather than
iL, and Vo will not ring back. The recommended value for Rip is
100Ω. Cip should be determined through tuning the load
transient response waveforms on an actual board. The
recommended range for Cip is 100pF~2000pF. However, it
should be noted that the Rip -Cip branch may distort the idroop
waveform. Instead of being triangular as the real inductor
current, idroop may have sharp spikes, which may adversely
affect idroop average value detection and therefore may affect
OCP accuracy. User discretion is advised.
Resistor Current-Sensing Network
Transfer function ARsen(s) always has unity gain at DC.
Current-sensing resistor Rsen value will not have significant
variation over-temperature, so there is no need for the NTC
network.
The recommended values are Rsum = 1kΩ and Cn = 5600pF.
Overcurrent Protection
Referring to Equation 1 and Figures 12, 13 and 19, resistor Ri
sets the droop current Idroop. Table 3 shows the internal OCP
threshold. It is recommended to design Idroop without using the
Rcomp resistor.
For example, the OCP threshold is 20µA. We will design Idroop to
be 14µA at full load, so the OCP trip level is 1.43x of the full load
current.
For inductor DCR sensing, Equation 16 gives the DC relationship
of Vcn(s) and Io(s).
R ntcnet
⎛
⎞
V Cn = ⎜ ----------------------------------------- × DCR⎟ × I o
R
+
R
⎝ ntcnet
⎠
sum
(EQ. 16)
Substitution of Equation 16 into Equation 1 gives:
R ntcnet
2
I droop = ----- × ----------------------------------------- × DCR × I o
R i R ntcnet + R sum
(EQ. 17)
PHASE
Therefore:
2R ntcnet × DCR × I o
R i = --------------------------------------------------------------------( R ntcnet + R sum ) × I droop
L
Substitution of Equation 8 and application of the OCP condition
in Equation 18 gives:
DCR
ISUM+
RSUM
RSEN
(EQ. 18)
Vcn
Cn
Ri
ISUM-
( R ntcs + R ntc ) × R p
2 × --------------------------------------------------- × DCR × I omax
R ntcs + R ntc + R p
R i = --------------------------------------------------------------------------------------------------------------⎛ ( R ntcs + R ntc ) × R p
⎞
⎜ --------------------------------------------------- + R sum⎟ × I droopmax
+
R
+
R
R
⎝ ntcs
⎠
ntc
p
(EQ. 19)
where Iomax is the full load current, Idroopmax is the corresponding
droop current. For example, given Rsum = 3.65kΩ, Rp = 11kΩ, Rntcs
= 2.61kΩ, Rntc = 10kΩ, DCR = 1.1mΩ, Iomax = 14A and
Idroopmax = 14µA, Equation 19 gives Ri = 1.36kΩ.
Io
FIGURE 19. RESISTOR CURRENT-SENSING NETWORK
20
For resistor sensing, Equation 20 gives the DC relationship of
Vcn(s) and Io(s).
FN6924.3
June 16, 2011
ISL62881, ISL62881B
V Cn = R sen × I o
(EQ. 20)
Substitution of Equation 20 into Equation 1 gives Equation 21:
2
I droop = ----- × R sen × I o
Ri
(EQ. 21)
Therefore:
V Rimon = 3 × I droop × R imon
(EQ. 27)
Rewriting Equation 26 gives Equation 28:
Io
I droop = ------------------ × LL
R droop
(EQ. 28)
Substitution of Equation 28 into Equation 27 gives Equation 29:
2R sen × I o
R i = --------------------------I droop
(EQ. 22)
Substitution of Equation 22 and application of the OCP condition
in Equation 18 gives:
2R sen × I omax
R i = -------------------------------------I droopmax
(EQ. 23)
where Iomax is the full load current, Idroopmax is the
corresponding droop current. For example, given Rsen = 1mΩ,
Iomax = 14A and Idroopmax = 14µA, Equation 23 gives Ri = 2kΩ.
3I o × LL
V Rimon = --------------------- × R imon
R droop
(EQ. 29)
Rewriting Equation 29 and application of full load condition gives
Equation 30:
V Rimon × R droop
R imon = -------------------------------------------3I o × LL
(EQ. 30)
For example, given LL = 7mΩ, Rdroop = 7kΩ, VRimon = 963mV at
Iomax = 14A, Equation 30 gives Rimon = 22.9kΩ.
A resistor from COMP to GND can adjust the internal OCP
threshold, providing another dimension of fine-tune flexibility.
Table 3 shows the detail. It is recommended to scale Idroop such
that the default OCP threshold gives approximately the desired
OCP level, then use Rcomp to fine tune the OCP level if necessary.
A capacitor Cimon can be paralleled with Rimon to filter the IMON
pin voltage. The RimonCimon time constant is the user’s choice. It
is recommended to have a time constant long enough such that
switching frequency ripples are removed.
Load Line Slope
Figure 14 shows the desired load transient response waveforms.
Figure 20 shows the equivalent circuit of a voltage regulator (VR)
with the droop function. A VR is equivalent to a voltage source
(= VID) and output impedance Zout(s). If Zout(s) is equal to the
load line slope LL, i.e. constant output impedance, in the entire
frequency range, Vo will have square response when Io has a
square change.
Refer to Figure 12.
For inductor DCR sensing, substitution of Equation 17 into
Equation 2 gives the load line slope expression in Equation 24.
2R droop
R ntcnet
V droop
LL = ------------------ = ---------------------- × ----------------------------------------- × DCR
Io
Ri
R ntcnet + R sum
(EQ. 24)
Compensator
Zout(s) = LL
For resistor sensing, substitution of Equation 21 into Equation 2
gives the load line slope expression in Equation 25:
2R sen × R droop
V droop
LL = ------------------ = ----------------------------------------Io
Ri
(EQ. 25)
Substitution of Equation 18 and rewriting Equation 24, or
substitution of Equation 22 and rewriting Equation 25 gives the
same result in Equation 26:
Io
R droop = ---------------- × LL
I droop
(EQ. 26)
One can use the full load condition to calculate Rdroop. For
example, given Iomax = 14A, Idroopmax = 14µA and LL = 7mΩ,
Equation 26 gives Rdroop = 7kΩ.
It is recommended to start with the Rdroop value calculated by
Equation 26, and fine tune it on the actual board to get accurate
load line slope. One should record the output voltage readings at
no load and at full load for load line slope calculation. Reading
the output voltage at lighter load instead of full load will increase
the measurement error.
Current Monitor
Referring to Equation 6 for the IMON pin current expression.
Refer to Figures 1 and 2, the IMON pin current flows through
Rimon. The voltage across Rimon is shown in Equation 27:
21
VID
VR
iO
LOAD
+
VO
-
FIGURE 20. VOLTAGE REGULATOR EQUIVALENT CIRCUIT
A VR with active droop function is a dual-loop system consisting
of a voltage loop and a droop loop which is a current loop.
However, neither loop alone is sufficient to describe the entire
system. The spreadsheet shows two loop gain transfer functions,
T1(s) and T2(s), that describe the entire system. Figure 21
conceptually shows T1(s) measurement set-up and Figure 22
conceptually shows T2(s) measurement set-up. The VR senses
the inductor current, multiplies it by a gain of the load line slope,
then adds it on top of the sensed output voltage and feeds it to
the compensator. T(1) is measured after the summing node, and
T2(s) is measured in the voltage loop before the summing node.
The spreadsheet gives both T1(s) and T2(s) plots. However, only
T2(s) can be actually measured on an ISL62881 regulator.
T1(s) is the total loop gain of the voltage loop and the droop loop.
It always has a higher crossover frequency than T2(s) and has
more meaning of system stability.
FN6924.3
June 16, 2011
ISL62881, ISL62881B
T2(s) is the voltage loop gain with closed droop loop. It has more
meaning of output voltage response.
Optional Slew Rate Compensation Circuit For
1-Tick VID Transition
Design the compensator to get stable T1(s) and T2(s) with
sufficient phase margin, and output impedance equal or smaller
than the load line slope.
L
Rdroop
Rvid
Q1
VIN
Vcore
VO
GATE Q2
DRIVER
OPTIONAL
IO
COUT
Cvid
FB
Ivid
Idroop_vid
LOAD LINE SLOPE
MOD
EA
+
COMP
+
20Ω
E/A
VIDs
Σ VDACDAC
RTN
VID
ISOLATION
TRANSFORMER
CHANNEL B
LOOP GAIN =
COMP
+
INTERNAL TO
IC
X1
VID<0:6>
VSSSENSE
VSS
CHANNEL A
CHANNEL A
CHANNEL B
NETWORK
ANALYZER
VID<0:6>
EXCITATION OUTPUT
FIGURE 21. LOOP GAIN T1(s) MEASUREMENT SET-UP
Vfb
Ivid
L
VO
Q1
VIN
IO
COUT
GATE Q2
DRIVER
Vcore
Idroop_vid
LOAD LINE SLOPE
+
MOD
COMP
LOOP GAIN =
+
EA
+
VID
CHANNEL B
20Ω
FIGURE 23. OPTIONAL SLEW RATE COMPENSATION CIRCUIT
FOR1-TICK VID TRANSITION
ISOLATION
TRANSFORMER
During a large VID transition, the DAC steps through the VIDs at a
controlled slew rate of 2.5µs or 1.25µs per tick (12.5mV), controlling
output voltage Vcore slew rate at 5mV/µs or 10mV/µs.
CHANNEL B
Figure 23 shows the waveforms of 1-tick VID transition. During
1-tick VID transition, the DAC output changes at approximately
15mV/µs slew rate, but the DAC cannot step through multiple
VIDs to control the slew rate. Instead, the control loop response
speed determines Vcore slew rate. Ideally, Vcore will follow the FB
pin voltage slew rate. However, the controller senses the inductor
current increase during the up transition, as the Idroop_vid
waveform shows, and will droop the output voltage Vcore
accordingly, making Vcore slew rate slow. Similar behavior occurs
during the down transition.
CHANNEL A
CHANNEL A
NETWORK
ANALYZER
EXCITATION OUTPUT
FIGURE 22. LOOP GAIN T2(s) MEASUREMENT SET-UP
To control Vcore slew rate during 1-tick VID transition, one can
add the Rvid-Cvid branch, whose current Ivid cancels Idroop_vid.
When Vcore increases, the time domain expression of the
induced Idroop change is as shown in Equation 31:
–t
-------------------------⎞
C out × LL dV core ⎛
C
× LL⎟
I droop ( t ) = ------------------------ × ------------------ × ⎜ 1 – e out
⎜
⎟
dt
R droop
⎝
⎠
22
(EQ. 31)
FN6924.3
June 16, 2011
ISL62881, ISL62881B
where Cout is the total output capacitance.
In the meantime, the Rvid-Cvid branch current Ivid time domain
expression is as shown in Equation 32:
–t
------------------------------⎞
dVfb ⎛
R
×C
I vid ( t ) = C vid × ------------ × ⎜ 1 – e vid vid⎟
⎜
⎟
dt
⎝
⎠
(EQ. 32)
It is desired to let Ivid(t) cancel Idroop_vid(t). So there are:
dV fb
C out × LL dV core
C vid × ------------ = ------------------------ × -----------------dt
dt
R droop
(EQ. 33)
and:
R vid × C vid = C out × LL
(EQ. 34)
The result is:
R vid = R droop
(EQ. 35)
and:
dV core
C out × LL ----------------dt
C vid = ------------------------ × -----------------R droop
dV fb
-----------dt
(EQ. 36)
For example: given LL = 3mΩ, Rdroop = 4.22kΩ, Cout = 1320µF,
dVcore/dt = 5mV/µs and dVfb/dt = 15mV/µs, Equation 35 gives
Rvid = 4.22kΩ and Equation 36 gives Cvid = 227pF.
It’s recommended to select the calculated Rvid value and start
with the calculated Cvid value and tweak it on the actual board to
get the best performance.
During normal transient response, the FB pin voltage is held
constant, therefore is virtual ground in small signal sense. The
Rvid-Cvid network is between the virtual ground and the real
ground, and hence has no affect on transient response.
Voltage Regulator Thermal Throttling
Figure 24 shows the thermal throttling feature with hysteresis.
An NTC network is connected between the NTC pin and GND. At
low temperature, SW1 is on and SW2 connects to the 1.20V side.
The total current flowing out of the NTC pin is 60µA. The voltage
on NTC pin is higher than the threshold voltage of 1.20V and the
comparator output is low. VR_TT# is pulled up by the external
resistor.
54µA
When temperature increases, the NTC thermistor resistance
decreases so the NTC pin voltage drops. When the NTC pin
voltage drops below 1.20V, the comparator changes polarity and
turns SW1 off and throws SW2 to 1.24V. This pulls VR_TT# low
and sends the signal to start thermal throttle. There is a 6µA
current reduction on NTC pin and 40mV voltage increase on
threshold voltage of the comparator in this state. The VR_TT#
signal will be used to change the CPU operation and decrease
the power consumption. When the temperature drops down, the
NTC thermistor voltage will go up. If NTC voltage increases to
above 1.24V, the comparator will flip back. The external
resistance difference in these two conditions is shown in
Equation 37:
1.24V 1.20V
--------------- – --------------- = 2.96k
54μA 60μA
(EQ. 37)
One needs to properly select the NTC thermistor value such that
the required temperature hysteresis correlates to 2.96kΩ
resistance change. A regular resistor may need to be in series
with the NTC thermistor to meet the threshold voltage values.
For example, given Panasonic NTC thermistor with B = 4700, the
resistance will drop to 0.03322 of its nominal at +105°C, and
drop to 0.03956 of its nominal at +100°C. If the required
temperature hysteresis is +105°C to +100°C, the required
resistance of NTC will be as shown in Equation 38:
2.96kΩ
------------------------------------------------------- = 467kΩ
( 0.03956 – 0.03322 )
(EQ. 38)
Therefore, a larger value thermistor such as 470k NTC should be
used.
At +105°C, 470kΩ NTC resistance becomes
(0.03322 × 470kΩ) = 15.6kΩ. With 60µA on the NTC pin, the
voltage is only (15.6kΩ × 60µA) = 0.937V. This value is much
lower than the threshold voltage of 1.20V. Therefore, a regular
resistor needs to be in series with the NTC. The required
resistance can be calculated by Equation 39:
1.20V
--------------- – 15.6kΩ = 4.4kΩ
60μA
(EQ. 39)
4.42k is a standard resistor value. Therefore, the NTC branch should
have a 470k NTC and 4.42k resistor in series. The part number for
the NTC thermistor is ERTJ0EV474J. It is a 0402 package. NTC
thermistor will be placed in the hot spot of the board.
Layout Guidelines
64µA
VR_TT#
SW1
Table 5 shows the layout considerations. The designators refer
to the reference designs shown in Figures 25 and 26.
NTC
+
VNTC
+
RNTC
Rs
1.24V
SW2
1.20V
INTERNAL TO
ISL62881
FIGURE 24. CIRCUITRY ASSOCIATED WITH THE THERMAL
THROTTLING FEATURE OF THE ISL62881
23
FN6924.3
June 16, 2011
ISL62881, ISL62881B
TABLE 5. LAYOUT CONSIDERATIONS
NAME
LAYOUT CONSIDERATION
GND
Create analog ground plane underneath the controller and the analog signal processing components. Don’t let the power ground plane
overlap with the analog ground plane. Avoid noisy planes/traces (e.g.: phase node) from crossing over/overlapping with the analog plane.
CLK_EN#
No special consideration.
PGOOD
No special consideration.
RBIAS
Place the RBIAS resistor (R16) in general proximity of the controller. Low impedance connection to the analog ground plane.
VR_TT#
No special consideration.
NTC
The NTC thermistor (R9) needs to be placed close to the thermal source that is monitor to determine thermal throttling. Usually it’s placed
close to phase-1 high-side MOSFET.
VW
Place capacitor (C4) across VW and COMP in close proximity of the controller.
COMP
Place compensator components (C3, C5, C6 R7, R11, R10 and C11) in general proximity of the controller.
FB
VSEN
Place the VSEN/RTN filter (C12, C13) in close proximity of the controller for good decoupling.
RTN
VDD
A capacitor (C16) decouples it to GND. Place it in close proximity of the controller.
IMON
Place the filter capacitor (C21) close to the CPU.
ISUM-
Place the current sensing circuit in general proximity of the controller.
Place C82 very close to the controller.
Place NTC thermistors R42 next to inductor (L1) so it senses the inductor temperature correctly.
The power stage sends a pair of VSUM+ and VSUM- signals to the controller. Run these two signal traces in parallel fashion with decent
width (>20mil).
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads.
Route R63 to the phase-node side pad of inductor L1. Route the other current sensing trace to the output side pad of inductor L1.
If possible, route the traces on a different layer from the inductor pad layer and use vias to connect the traces to the center of the pads.
If no via is allowed on the pad, consider routing the traces into the pads from the inside of the inductor. The following drawings show the
two preferred ways of routing current sensing traces.
ISUM+
INDUCTOR
INDUCTOR
VIAS
CURRENTSENSING TRACES
VIN
CURRENTSENSING TRACES
A capacitor (C17) decouples it to GND. Place it in close proximity of the controller.
BOOT
Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
UGATE
Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting
close. Recommend routing PHASE trace to the high-side MOSFET (Q2 and Q8) source pins instead of general phase node copper.
PHASE
VSSP
Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting
close. Recommend routing VSSP to the low-side MOSFET (Q3 and Q9) source pins instead of general power ground plane for better
LGATE
performance.
or
LGATEa and
LGATEb
VCCP
A capacitor (C22) decouples it to GND. Place it in close proximity of the controller.
VID0~6
No special consideration.
VR_ON
No special consideration.
DPRSLPVR
No special consideration.
Phase Node Minimize phase node copper area. Don’t let the phase node copper overlap with/getting close to other sensitive traces. Cut the power
ground plane to avoid overlapping with phase node copper.
Minimize the loop consisting of input capacitor, high-side MOSFETs and low-side MOSFETs (e.g.: C27, C33, Q2, Q8, Q3 and Q9).
24
FN6924.3
June 16, 2011
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VR_ON
DPRSLPVR
IN
IN
IN
IN
IN
IN
IN
IN
IN
UGATE
10UF
C27
C21
OUT
IMON
IN
VSSSENSE
C22
10K 2.61K
NTC
R41
11K
-----> R42
0.15UF
R38
0.1UF
----
C20
C15
----
DNP DNP
-----------OPTIONAL
C54
10UF
C55
3900PF
22.6K
R50
+5V
VIN
R30
3.01K
-----------C81 R109
VCORE
15
IN
0
10UF
C56
10UF
C40
10UF
C41
10UF
C59
10UF
C60
10UF
OUT
10UF
C52
Q3
C61
0.22UF
0.88UH
470UF
0
IRF7832
16
R63
R26
10
C30
17
IN
R40
0.22UF
R18
1
C18
IN
R37
----
0.056UF
VSSSENSE
+5V
IN
18
0
1UF
C17
IN
R20
19
R56
1UF
VSEN
EP
C82
VCCSENSE
10UF
C33
C24
28
27
26
25
24
23
22
PHASE
C16
10
VSSP
ISL62881HRZ
0.01UF 82.5
R17
VCCP
LGATE
FB
R11
6.98K
OPTIONAL
----
U6
20
RTN
ISUMISUM+
VDD
VIN
IMON
BOOT
R7
422K
----C12
---- 100PF
VCORE IN
VID0
COMP
29
2.37K 270PF
PGOOD
21
8
9
10
11
12
13
14
15PF
VID1
VW
7
C11
C13
C3
R10
VR_ON
VID6
VID5
VID4
VID3
VID2
DPRSLPVR
TBD
1.91K
R23
R19
C4
C6
L1
CLK_EN#
RBIAS
4
5
1000PF 330PF
-----
C83 R110
3
IRF7821
Q2
3.65K
PLACE NEAR L1
FIGURE 25. GPU APPLICATION REFERENCE DESIGN
LAYOUT
NOTE:
ROUTE UGATE TRACE IN PARALLEL
WITH THE PHASE TRACE GOING TO
THE SOURCE OF Q2
ROUTE LGATE TRACE IN PARALLEL
WITH THE VSSP TRACE GOING TO
THE SOURCE OF Q3
ISL62881, ISL62881B
DNP
DNP
--------
R16
47K
2
6
OPTIONAL
----
--------
1
1000PF
----
OUT
10K
DNP
------R6
25
------R4
PGOOD
OPTIONAL
----
IN
IN
56UF
VIN
+3.3V
FN6924.3
June 16, 2011
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VR_ON
DPRSLPVR
IN
IN
IN
IN
IN
IN
IN
+3.3V
IN
IN
IN
10UF
C27
10UF
C33
56UF
C24
VR_ON
VID6
VID5
VID4
VID3
VID2
C56
VCORE
10UF
C40
10UF
C41
10UF
C59
10UF
C60
10UF
10UF
C61
C70
10UF
10UF
10UF
C71
10UF
10UF
10UF
C74
10UF
10UF
10UF
C75
10UF
10UF
10UF
C54
10UF
10UF
10UF
C55
10UF
C43
10K 2.61K
NTC
R41
11K
-----> R42
3.65K
PLACE NEAR L1
FIGURE 26. CPU APPLICATION REFERENCE DESIGN
LAYOUT
C47
C63
C49
C50
C42
C48
C64
VSSSENSE
C65
IN
C66
IMON
C67
C22
R38
0.1UF
----
10UF
C21
OUT
2700PF
34K
R50
+5V
VIN
0.15UF
C15
----
DNP DNP
----------OPTIONAL
C68
15
R30
1.91K
----------C81 R109
OUT
10UF
16
IN
0
C52
Q9
0.45UH
330UF
0.22UF
Q3
IRF7832
C39
0
IRF7832
330UF
C30
1UF
DPRSLPVR
28
27
26
25
24
23
22
R56
17
R63
R26
10
+5V
IN
18
C20
R18
----
0.22UF
IN
19
IN
R40
1
C18
VSSSENSE
R37
OPTIONAL
0.022UF
IN
20
0
1UF
C17
VCCSENSE
UGATE
C82
10
VSEN
EP
R20
----
VSSP
ISL62881HRZ
PHASE
R11
4.22K
VCCP
FB
C16
100PF 422K
---R17
VCORE IN
U6
LGATE
COMP
29
4.87K 470PF
VID0
0.01UF 82.5
R7
PGOOD
21
RTN
ISUMISUM+
VDD
VIN
IMON
BOOT
27PF
VID1
VW
7
C11
----C12
C3
R10
C13
C6
L1
CLK_EN#
RBIAS
4
5
1000PF 330PF
-----
C83 R110
3
IRF7821
Q2
NOTE:
ROUTE UGATE TRACE IN PARALLEL
WITH THE PHASE TRACE GOING TO
THE SOURCE OF Q2 AND Q8
ROUTE LGATE TRACE IN PARALLEL
WITH THE VSSP TRACE GOING TO
THE SOURCE OF Q3 AND Q9
ISL62881, ISL62881B
DNP DNP
--------
147K
2
6
OPTIONAL
----
--------
R16
IN
8
9
10
11
12
13
14
C4
----
1
1000PF
7.32K
R4
DNP
------R6
26
-------
CLK_EN# OUT
PGOOD OUT
OPTIONAL
----
1.91K
10K
R23
R19
VIN
FN6924.3
June 16, 2011
ISL62881, ISL62881B
CPU Application Reference Design Bill of Materials
QTY
REFERENCE
VALUE
DESCRIPTION
1
C11
470pF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00471-16V10
SM0603
1
C12
330pF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00331-16V10
SM0603
1
C13
1000pF Multilayer Cap, 16V, 10%
GENERIC
H1045-00102-16V10
SM0603
1
C15
0.01µF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00103-16V10
SM0603
2
C16, C22
1µF
Multilayer Cap, 16V, 20%
GENERIC
H1045-00105-16V20
SM0603
1
C18
0.15µF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00154-16V10
SM0603
1
C20
0.1µF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00104-16V10
SM0603
1
C21
2700pF Multilayer Cap, 16V, 10%
GENERIC
H1045-00272-16V10
SM0603
2
C17, C30
0.22µF
GENERIC
H1045-00224-25V10
SM0603
1
C24
56µF
Radial SP Series Cap, 25V, 20%
25SP56M
CASE-CC
2
C27, C33
10µF
Multilayer Cap, 25V, 20%
GENERIC
H1065-00106-25V20
SM1206
1
C3
100pF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00101-16V10
SM0603
2
C39, C52
330µF
SPCAP, 2V, 4MΩ
Multilayer Cap, 25V, 10%
POLYMER CAP, 2.5V, 4.5MΩ
1000pF Multilayer Cap, 16V, 10%
MANUFACTURER
SANYO
PANASONIC
KEMET
1
C4
30
C40-C43,
C47-C50,
C53-C56, C59,
C75, C78
10µF
1
C6
27pF
1
C82
0
C81, C83
1
L1
0.45µH Inductor, Inductance 20%, DCR 7%
NEC-TOKIN
1
Q2
N-Channel Power MOSFET
2
Q3, Q9
N-Channel Power MOSFET
1
R10
4.87k
Thick Film Chip Resistor, 1%
1
R11
4.22k
1
R16
2
Multilayer Cap, 6.3V, 20%
PART NUMBER
PACKAGE
EEXSX0D331E4
T520V337M2R5A(1)E4R5-6666
GENERIC
H1045-00102-16V10
SM0603
MURATA
GRM21BR61C106KE15L
SM0805
TDK
C2012X5R0J106K
Multilayer Cap, 16V, 10%
GENERIC
H1045-00270-16V10
SM0603
0.022µF Multilayer Cap, 16V, 10%
GENERIC
H1045-00223-16V10
SM0603
MPCG1040LR45
10mmx10mm
IR
IRF7821
PWRPAKSO8
IR
IRF7832
PWRPAKSO8
GENERIC
H2511-04871-1/16W1
SM0603
Thick Film Chip Resistor, 1%
GENERIC
H2511-04221-1/16W1
SM0603
147k
Thick Film Chip Resistor, 1%
GENERIC
H2511-01473-1/16W1
SM0603
R17, R18
10
Thick Film Chip Resistor, 1%
GENERIC
H2511-00100-1/16W1
SM0603
1
R19
1.91k
Thick Film Chip Resistor, 1%
GENERIC
H2511-01911-1/16W1
SM0603
1
R26
82.5
Thick Film Chip Resistor, 1%
GENERIC
H2511-082R5-1/16W1
SM0603
3
R20, R40, R56
0
Thick Film Chip Resistor, 1%
GENERIC
H2511-00R00-1/16W1
SM0603
1
R30
1.91k
Thick Film Chip Resistor, 1%
GENERIC
H2511-01911-1/16W1
SM0603
1
R37
1
Thick Film Chip Resistor, 1%
GENERIC
H2511-01R00-1/16W1
SM0603
1
R38
11k
Thick Film Chip Resistor, 1%
GENERIC
H2511-01102-1/16W1
SM0603
1
R41
2.61k
Thick Film Chip Resistor, 1%
GENERIC
H2511-02611-1/16W1
SM0603
1
R42
ERT-J1VR103J
SM0603
1
R50
H2511-03402-1/16W1
SM0603
DNP
10k NTC Thermistor, 10k NTC
34k
Thick Film Chip Resistor, 1%
27
PANASONIC
GENERIC
FN6924.3
June 16, 2011
ISL62881, ISL62881B
CPU Application Reference Design Bill of Materials (Continued)
QTY
REFERENCE
VALUE
DESCRIPTION
MANUFACTURER
PART NUMBER
PACKAGE
1
R6
7.32k
Thick Film Chip Resistor, 1%
GENERIC
H2511-07321-1/16W1
SM0603
1
R63
3.65k
Thick Film Chip Resistor, 1%
GENERIC
H2511-03651-1/16W1
SM0805
1
R7
422k
Thick Film Chip Resistor, 1%
GENERIC
H2511-04223-1/16W1
SM0603
0
R109, R110,
R4, R8, R9
DNP
1
U6
IMVP-6.5 PWM Controller
INTERSIL
ISL62881HRTZ
QFN-28
GPU Application Reference Design Bill of Materials
QTY
REFERENCE
VALUE
DESCRIPTION
1
C11
270pF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00271-16V10
SM0603
1
C12
330pF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00331-16V10
SM0603
1
C13
1000pF Multilayer Cap, 16V, 10%
GENERIC
H1045-00102-16V10
SM0603
1
C15
0.01µF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00103-16V10
SM0603
2
C16, C22
1µF
Multilayer Cap, 16V, 20%
GENERIC
H1045-00105-16V20
SM0603
1
C18
0.15µF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00154-16V10
SM0603
1
C20
0.1µF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00104-16V10
SM0603
2
C17, C30
0.22µF
Multilayer Cap, 25V, 10%
GENERIC
H1045-00224-25V10
SM0603
1
C21
3900pF Multilayer Cap, 16V, 10%
GENERIC
H1045-00392-16V10
SM0603
1
C24
56µF
Radial SP Series Cap, 25V, 20%
25SP56M
CASE-CC
2
C27, C33
10µF
Multilayer Cap, 25V, 20%
GENERIC
H1065-00106-25V20
SM1206
1
C3
100pF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00101-16V10
SM0603
1
C52
470µF
SPCAP, 2V, 4MΩ
POLYMER CAP, 2.5V, 4.5MΩ
1000pF Multilayer Cap, 16V, 10%
MANUFACTURER
SANYO
PANASONIC
KEMET
PART NUMBER
PACKAGE
EEXSX0D471E4
T520V477M2R5A(1)E4R5-6666
1
C4
8
C40, C41,
C54-C56,
C59-C61
10µF
1
C6
15pF
1
C82
0
C81, C83
1
L1
0.88µH Inductor, Inductance 20%, DCR 7%
NEC-TOKIN
1
Q2
N-Channel Power MOSFET
2
Q3, Q9
N-Channel Power MOSFET
1
R10
2.37k
Thick Film Chip Resistor, 1%
GENERIC
H2511-02371-1/16W1
SM0603
1
R11
6.98k
Thick Film Chip Resistor, 1%
GENERIC
H2511-06981-1/16W1
SM0603
1
R16
47.5k
Thick Film Chip Resistor, 1%
GENERIC
H2511-04752-1/16W1
SM0603
2
R17, R18
10
Thick Film Chip Resistor, 1%
GENERIC
H2511-00100-1/16W1
SM0603
1
R19
1.91k
Thick Film Chip Resistor, 1%
GENERIC
H2511-01911-1/16W1
SM0603
1
R26
82.5
Thick Film Chip Resistor, 1%
GENERIC
H2511-082R5-1/16W1
SM0603
Multilayer Cap, 6.3V, 20%
GENERIC
H1045-00102-16V10
SM0603
MURATA
GRM21BR61C106KE15L
SM0805
TDK
C2012X5R0J106K
Multilayer Cap, 16V, 10%
GENERIC
H1045-00150-16V10
SM0603
0.056µF Multilayer Cap, 16V, 10%
GENERIC
H1045-00563-16V10
SM0603
DNP
28
MPC1040LR88
10mmx10mm
IR
IRF7821
PWRPAKSO8
IR
IRF7832
PWRPAKSO8
FN6924.3
June 16, 2011
ISL62881, ISL62881B
GPU Application Reference Design Bill of Materials (Continued)
QTY
REFERENCE
VALUE
DESCRIPTION
3
R20, R40, R56
0
Thick Film Chip Resistor, 1%
GENERIC
H2511-00R00-1/16W1
SM0603
1
R30
3.01k
Thick Film Chip Resistor, 1%
GENERIC
H2511-03011-1/16W1
SM0603
1
R37
1
Thick Film Chip Resistor, 1%
GENERIC
H2511-01R00-1/16W1
SM0603
1
R38
11k
Thick Film Chip Resistor, 1%
GENERIC
H2511-01102-1/16W1
SM0603
1
R41
2.61k
Thick Film Chip Resistor, 1%
GENERIC
H2511-02611-1/16W1
SM0603
1
R42
ERT-J1VR103J
SM0603
1
R50
22.6k
Thick Film Chip Resistor, 1%
GENERIC
H2511-02262-1/16W1
SM0603
1
R6
10k
Thick Film Chip Resistor, 1%
GENERIC
H2511-01002-1/16W1
SM0603
1
R63
3.65k
Thick Film Chip Resistor, 1%
GENERIC
H2511-03651-1/16W1
SM0805
1
R7
412k
Thick Film Chip Resistor, 1%
GENERIC
H2511-04123-1/16W1
SM0603
0
R109, R110,
R4, R8, R9
DNP
1
U6
IMVP-6.5 PWM Controller
INTERSIL
ISL62881HRTZ
QFN-28
10k NTC Thermistor, 10k NTC
29
MANUFACTURER
PANASONIC
PART NUMBER
PACKAGE
FN6924.3
June 16, 2011
ISL62881, ISL62881B
90
88
88
86
86
84
84
EFFICIENCY (%)
EFFICIENCY (%)
Typical Performance
VIN = 12V
82
VIN = 8V
80
VIN = 19V
78
76
74
80
78
76
VIN = 12V
VIN = 19V
VIN = 8V
74
72
72
70
82
0
2
4
6
8
10 12
IOUT (A)
14
16
18
20
22
FIGURE 27. CPU APPLICATION CCM EFFICIENCY, VID = 0.9V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
0.91
70
0.1
1.0
IOUT (A)
10.0
FIGURE 28. CPU APPLICATION DCM EFFICIENCY, VID = 0.9V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
VIN = 19V
0.90
0.89
VOUT (V)
0.88
0.87
0.86
0.85
0.84
0.83
VIN = 12V
0.82
VIN = 8V
0.81
0.80
0
2
4
6
8
10 12
IOUT (A)
14
16
18
20
22
FIGURE 29. CPU APPLICATION CCM LOAD LINE, VID = 0.9V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 30. CPU MODE CLK_EN# DELAY, VIN = 19V, IO = 0A,
VID = 1.2V, Ch1: PHASE1, Ch2: VO, Ch4: CLK_EN#
FIGURE 31. CPU MODE SOFT-START, VIN = 19V, IO = 0A,
VID = 1.2V, Ch1: PHASE, Ch2: VO
FIGURE 32. GPU MODE SOFT-START, VIN = 19V, IO = 0A,
VID = 1.2V, Ch1: PHASE, Ch2: VO
30
FN6924.3
June 16, 2011
ISL62881, ISL62881B
Typical Performance (Continued)
FIGURE 33. CPU MODE SHUT DOWN, VIN = 19V, IO = 0A,
VID = 1.2V, Ch1: PHASE, Ch2: VO
FIGURE 34. GPU MODE SHUT DOWN, VIN = 19V, IO = 0A,
VID = 1.2V, Ch1: PHASE, Ch2: VO
FIGURE 35. CCM STEADY STATE, CPU MODE, VIN = 8V, IO = 1A,
VID = 1.2375V, Ch1: PHASE, Ch2: VO
FIGURE 36. DCM STEADY STATE, CPU MODE, VIN = 12V, IO = 1A,
VID = 1.075V, Ch1: PHASE1, Ch2: VO, Ch3: COMP,
Ch4: LGATE
1000
900
Phase Margin
Gain
IMON-VSSSENSE (mV)
800
700
600
500
IMON
400
300
200
100
0
FIGURE 37. GPU MODE REFERENCE DESIGN LOOP GAIN T2(s)
MEASUREMENT RESULT
31
TARGET
0
2
4
6
8
10
12
IOUT (A)
14
16
18
20
22
FIGURE 38. IMON, VID = 1.2375
FN6924.3
June 16, 2011
ISL62881, ISL62881B
Typical Performance (Continued)
FIGURE 39. LOAD TRANSIENT RESPONSE WITH OVERSHOOT
REDUCTION FUNCTION DISABLED, GPU MODE,
VIN = 12V, VID = 0.9V, IO = 12A/22A,
di/dt = “FASTEST”
FIGURE 40. LOAD TRANSIENT RESPONSE WITH OVERSHOOT
REDUCTION FUNCTION DISABLED, GPU MODE,
VIN = 12V, VID = 0.9V, IO = 12A/22A,
di/dt = “FASTEST”
FIGURE 41. LOAD TRANSIENT RESPONSE WITH OVERSHOOT
REDUCTION FUNCTION DISABLED, GPU MODE,
VIN = 12V, VID = 0.9V, IO = 12A/22A,
di/dt = “FASTEST”
FIGURE 42. LOAD TRANSIENT RESPONSE WITH OVERSHOOT
REDUCTION FUNCTION DISABLED, GPU MODE,
VIN = 12V, VID = 0.9V, IO = 12A/22A,
di/dt = “FASTEST”
FIGURE 43. CPU MODE VID TRANSITION, DPRSLPVR = 0, IO = 2A,
VID = 1.2375V/1.0375V, Ch2: VO, Ch3: VID4
FIGURE 44. GPU MODE VID TRANSITION, DPRSLPVR = 0, IO = 2A,
VID = 1.2375V/1.0375V, Ch2: VO, Ch3: VID4
32
FN6924.3
June 16, 2011
ISL62881, ISL62881B
Typical Performance (Continued)
FIGURE 45. CPU MODE VID TRANSITION, DPRSLPVR = 1, IO = 2A,
VID = 1.2375V/1.0375V, Ch2: VO, Ch3: VID4
FIGURE 46. GPU MODE VID TRANSITION, DPRSLPVR = 1, IO = 2A,
VID = 1.2375V/1.0375V, Ch2: VO, Ch3: VID4
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in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
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33
FN6924.3
June 16, 2011
ISL62881, ISL62881B
Package Outline Drawing
L28.4x4
28 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 9/06
A
4 . 00
2 . 50
PIN #1 INDEX AREA
CHAMFER 0 . 400 X 45°
0 . 40
22
28
1
0 . 40
15
3 . 20
2 . 50
4 . 00
21
0 . 4 x 6 = 2.40 REF
B
PIN 1
INDEX AREA
7
0 . 10
2X
14
8
0 . 20 ±0 . 05
0 . 10 M C A B
0 . 4 x 6 = 2 . 40 REF
TOP VIEW
3 . 20
BOTTOM VIEW
SEE DETAIL X''
0 . 10 C
(3 . 20)
C
PACKAGE BOUNDARY
MAX. 0 . 80
SEATING PLANE
(28X 0 . 20)
0 . 00 - 0 . 05
0 . 08 C
0 . 20 REF
(3 . 20)
(2 . 50)
SIDE VIEW
(0 . 40)
C
(0 . 40)
0 . 20 REF
5
0 ~ 0 . 05
(2 . 50)
(28X 0 . 60)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Controlling dimensions are in mm.
Dimensions in ( ) for reference only.
2. Unless otherwise specified, tolerance : Decimal ±0.05
Angular ±2°
3. Dimensioning and tolerancing conform to AMSE Y14.5M-1994.
4. Bottom side Pin#1 ID is diepad chamfer as shown.
5. Tiebar shown (if present) is a non-functional feature.
34
FN6924.3
June 16, 2011
ISL62881, ISL62881B
Package Outline Drawing
L32.5x5E
32 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 03/09
3.50
5.00
28X 0.50
A
B
6
6
PIN 1
INDEX AREA
24
1
3.50
5.00
3.70
Exp. DAP
8
17
(4X)
PIN #1 INDEX AREA
32
25
0.15
32X 0.25 4
0.10 M C A B
9
16
3.70
Exp. DAP
SIDE VIEW
TOP VIEW
32X 0.40
BOTTOM VIEW
SEE DETAIL "X"
( 4.80 )
( 3.50)
0.10 C
Max 0.80
( 28X 0.50)
C
SEATING PLANE
0.08 C
SIDE VIEW
( 4.80 )
(3.70
)
( 3.50)
(32X 0.25)
C
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
( 32 X 0.60)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
35
FN6924.3
June 16, 2011
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