an1341

ISL6752EVAL1Z Evaluation Board
with Synchronous Rectifiers
®
Application Note
September 13, 2007
AN1341.0
Author: Richard Garcia
Introduction
The ISL6752EVAL1Z board utilizes Intersil’s zero voltage
switching (ZVS) topology. In addition to the ZVS function,
this board also incorporates N-Channel FETs as secondary
side rectifiers, also known as synchronous rectifiers (SR).
Power dissipation of the secondary side rectifiers is reduced
because the conduction losses of SRs can be significantly
less than the conduction losses of PN or Schottky diodes.
Scope
This application note will cover the implementation of
synchronous rectifiers (SRs) and their associated drive
circuits as used on the ISL6752EVAL1Z board. The various
implications of using SRs are covered. The implementation
of the primary side ZVS controller, based on the ISL6752, is
covered extensively in Intersil application note AN1262,
“Designing with the ISL6752, ISL6753 Full-Bridge
Controllers”.
At the end of this application note, the schematic, the bill of
materials and the printed circuit board layout are included for
reference.
TABLE 1. SPECIFICATIONS
Max Input Voltage
Operating Input Voltage
450VDC
325V to 425VDC
Max Input Current
2.5ADC
Rated Output Current
50ADC
Current Limit
60A±5%
Output Voltage
12V±5%
Circuit Elements
The evalualtion board is composed of several distinct circuit
elements. Please reference the schematic at the end of this
application note.
Also covered is the performance of this evaluation board.
Measured waveforms are compared to the theoretical
waveforms. Efficiency and regulation is also measured.
FIGURE 1. ISL6752EVAL1Z EVALUATION BOARD
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Application Note 1341
Primary Side Control
High Voltage Protection
The ISL6752 ZVS controller, U1, is located on the primary
side, eliminating the need for two AC line isolating gate drive
transformers to drive the primary side bridge FETs. Instead,
the low side FETs are driven direcly by MOSFET drivers and
the high side FETs are driven by a gate drive transformer
that only requires operational insulation. Primary side control
also simplifies the design of the current sensing transformers
because they also do not have to be AC line isolating.
Because a failure of the bridge can cause catastrophic
damage to the primary side control elements, a voltage
crowbar, F1 and D3, and a voltage blocking diode, D4, are
incorporated. D3 clamps the bias voltage to a safe level. If
400V is applied to the VDD bias node, F1 opens shortly after
D3 conducts current. D4 provides additional protection by
blocking high voltage from being applied to the 13V lab
supply. Note that a fully debugged power supply does not
need these additional components. These parts are left on
the eval board to minimize damage should the user
accidently introduce a fault while evaluating the circuits. The
designer may want to keep F1 in the final design to prevent a
loud bang should the bridge fail.
F1
U1
FIGURE 2. PRIMARY SIDE CONTROL CIRCUIT
D3
D4
FIGURE 4. HIGH VOLTAGE PROTECTION CIRCUIT
Primary Side Current Sensing
ZVS Full Bridge
The low side FETs, Q3 and Q4, are driven directly by
MOSFET drivers, U4. The two high side FETs, Q1 and Q2,
are also driven by a MOSFET driver, U5, but are coupled
with one gate drive transformer, T3, that has complementary
outputs. The design of the gate drive transformer is
simplified because it only needs 400V operational insulation
and it is always driven with a symmetrical square wave.
Q2
The primary side bridge has 2 current sensing transformers
(CT), one on each leg. Using two transformers allows each
CT to reset during alternate half cycles. Alternative methods
of current sensing using only one CT will also be covered.
Q1
T4
T2
T3
Q3
Q4
FIGURE 5. PRIMARY SIDE CURRENT SENSING CIRCUIT
Synchronous Rectifier Drive Circuit
U5
U6
FIGURE 3. ZVS FULL BRIDGE CIRCUIT
2
Two banks of SRs, Q107 through Q110 and Q111 through
Q114, are driven by MOSFET drivers, U108 and U109. An
RCD network on the inputs to the drivers delay the turn-on of
the SRs relative to the turn-off of the primary side bridge
AN1341.0
September 13, 2007
Application Note 1341
FETs. Pulse transformer, T6, crosses the isolation boundary
to couple the control signals from the ISL6752 to the
MOSFET drivers. Note that this transformer also provides
the secondary side bias voltage to the MOSFET drivers.
Output Voltage Error Amplifier
A line isolation rated opto-coupler, U2, passes the analog
error signal generated by the error amplifier, U102 from the
secondary to the primary.
U102
U2
U109
U108
T6
FIGURE 8. OUTPUT VOLTAGE ERROR AMPLIFIER CIRCUIT
Basic SR Principles
Replacing diodes with MOSFETs has two major advantages:
• dramatically reduces conduction losses
• the applied duty cycle remains virtually constant from no
load to full load.
FIGURE 6. SYNCHRONOUS RECTIFIER DRIVE CIRCUIT
Current Doubler Output
and two significant disadvantages:
• additional complexity and cost
The current doubler output is composed of two banks of
SRs, Q107 through Q110 and Q111 through Q114, inductors
L102 and L103, and output filter capacitors, C132 through
C136. The advantage of this topology is that the output
current is shared by the two inductors reducing conduction
losses. Another advantage is that the secondary winding of
the power transformer does not require a center tap
simplifying the construction of the transformer.
L103
Q107..
Q110
C132...C136
• when paralleling units for redundancy, provisions must be
made to prevent current circulation among the units.
SR Drive Timing Requirements
To emulate a diode, an SR must be driven on when a diode
would be normally conducting. But unlike a diode, if the SR
is on, the current through the SR can reverse if the voltage
on the SR “cathode” becomes positive. The consequence of
this is that if the SR is driven on when the primary side is
sourcing voltage to the secondary, the secondary side will be
shorted by the SR.
Figure 9 illustrates the timing required to drive the SRs. Note
the delays to prevent the overlapping of the drive signals.
When an SR is turned off when current is flowing from
source to drain, the current will divert from the FET channel
to the internal body diode. It is desirable to minimize the
period that the current flows through the body diode to
minimize dissipation.
SR Drive and Bias
OUTLLN and OUTLRN in Figure 10 are control signals from
the ISL6752 that are used to drive the SRs. Because the
ISL6752 is located on the primary side, a pulse transformer,
T6 is used to cross the isolation boundary. The simplified
schematic of Figure 10 illustrates the use of T6 to not only
couple OUTLLN and OUTLRN to the secondary, but also to
generate the bias for the drivers on the secondary.
Q111..
Q114
L102
FIGURE 7. CURRENT DOUBLER OUTPUT CIRCUIT
3
AN1341.0
September 13, 2007
Application Note 1341
When OUTLLN or OUTLRN transition to a logic high, it is
necessary to turn off the SRs quickly. For example, when
OUTLLN is high, V1 is positive relative to ground charging
C125 quickly through CR108. U108 inverts the input and
turns off SR1. In a similar manner, when OUTLLRN is high,
U109 drives SR2 off.
of generating the bias for U108 and U109 in this manner is
that the thresholds for the logic transitions on the inputs of
U108 and U109 are proportional to VBIAS and the voltage to
charge C125 and C124 is also VBIAS. Consequently, the
delays generated by the RC networks are independent of
the absolute value of VBIAS.
When OUTLLN and OUTLRN transition to a logic low, it is
necessary to turn on the SRs after a time delay to prevent
the SRs from shorting the primary side bridge when it is
sourcing current. For example, when OUTLLN transitions to
low, V1 is grounded and CR108 prevents C125 from being
discharged by V1. CR125 discharges instead through R140
delaying the transition of V2 from high to low on the input of
U108. When V2 is low, the output of U108 drives SR1 on. In
a similar manner, the transition of OUTLLRN from high to
low is delayed to drive SR2 on.
Current Doubler
Figure 11 illustrates the current flow in the two inductors of
the current doubler topology. Color coding is used to
correlate the current flow in the circuit with the waveforms.
The green waveform represents the sum of the red and blue
currents through RLOAD. For circuit clarity, the paralleled SRs
and output capacitors of the ISL6752EVAL1Z board are not
shown.
When using diodes (instead of SRs), if the average load
current is less than 1/2 of the ramp current in the output
inductors, the current in the inductors becomes
discontinuous and the duty cycle of the PWM is shortened to
maintain the desired output voltage.
Note that the cathodes of CR108 and CR107 are connected
together to alternately peak charge C123. Because C123 is
large in value, after the initial charging, the voltage does not
change significantly from cycle to cycle. An important aspect
+400V
V PWM 1
V BR1
V SR1
V SR2
V PWM 2
DELAY V PWM 2
RL
V BR2
V SR1
V SR2
V BR1
V PWM 1
DELAY
V PWM 2
DELAY
V BR2
DELAY V PWM1
SRS
400V RTN
FIGURE 9. TIMING REQUIRED TO DRIVE SRs
OUTLLN
V1
V1
V2
ENABLE
V SR1
U108
SR1
OUTLLN
V2
CR108
V sr1
R140
C125
R139
C124
U109
CR107
V3
OUTLRN
SR2
T6
V4
V3
V sr2
V SR2
V4
V BIAS
FIGURE 10. SIMPLIFIED SCHEMATIC
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AN1341.0
September 13, 2007
Application Note 1341
L1
R LO A D
Q1
Q2
L2
UNCHANG ED
DUTY CYCLE
LIGHT LO AD
W ITH SRS
LO AD W ITH EITHER
DIO DES O R SRS
REDUCED
DUTY CYCLE
UNCHANG ED
DUTY CYCLE
LIGHT LO AD
W ITH DIO DES
NO LO AD W HEN
USING SRS
DISCONTINUO US CURRENTS
FIGURE 11. INDUCTOR FLOW IN TWO INDUCTORS OF CURRENT DOUBLER TOPOLOGY
30A LOAD
NO LOAD
50A LOAD
FIGURE 12. INDUCTOR CURRENT WAVEFORMS
When using SRs, the inductor currents in L1 and L2 can
become negative because current can flow in SRs
bidirectionally. Consequently, the duty cycle remains virtually
unchanged. The benefit of this is that the load transient
performance is the same for any load from zero up to current
limit. Another advantage is that for very light loads, the duty
cycle is not reduced to very small duty cycles, pulse skipping
does not occur, and the associated voltage jitter does not
happen.
An important design consideration for the current doubler
topology is that the DC resistance of both halves must be
equal. The pcb layout must be as symmetrical as possible
and the DCRs of the inductors should also be reasonably
equal. If not, the current between the two sides will not split
equally. Because perfect physical pcb symmetry is not
always possible, it is necessary to confirm the current
sharing between the inductors.
5
In Figure 12, the inductor current waveforms are taken from
the ISL6752EVAL1Z board. The balance of currents
between the two inductors was achieved after two board
revisions. Observe how the inductor currents maintain the
same waveform shape even at no load.
Another design consideration when using SRs is the
problem of connecting the outputs of multiple power supplies
in parallel for redundancy or for increased power capacity. A
consequence of negative current flowing in an SR (when a
diode would otherwise be reversed biased and off) is that
power can be transferred from the secondary to the primary
if one of the paralleled outputs has a higher voltage. The
voltage loop of the units with lower set point voltages will
attempt to pull down the voltage by sinking current from the
higher set point units. The primary side bridge capacitor is
charged by the secondary side eventually resulting with
excessive voltage damage. This damage can be avoided by
using or-ing diodes (or FETs) on the paralleled outputs.
Another solution is to turn off the SRs (diode emulation
AN1341.0
September 13, 2007
Application Note 1341
mode) when the current reverses in the SRs but this
eliminates some of the advantages of using SRs. Paralleling
features are not implemented on the ISL6752EVAL1Z board.
+400V
Current Sensing
Current flowing from the secondary to the primary can result
with an unanticipated malfunction of the current sensing
transformer circuit if reverse SR currents are not considered.
Figure 13 is a commonly used primary side current sensing
circuit utilizing one current sensing transformer (CT).
This circuit works well for peak current mode control if power
is always flowing from primary to secondary, as is the case
when diodes are used instead of SRs. Figure 14 illustrates
the performance of the current sensing output when power
always flows from primary to secondary.
NOT
RECOMMENDED
RS
The voltage across RS is as expected. The vertical dashed
lines show when the power cycle is terminated at the
required peak of the current.
Figure 15 illustrates what happens at no load to the sense
voltage across RS.
Notice that the negative components of the primary
transformer current are rectified resulting with two peaks of
current across RS for each half cycle. Under steady state
conditions, the rectified negative component may cause
erratic performance because the cycle can terminate on the
first peak (the inverted peak as indicated by the vertical red
line) instead of the required second peak. This condition can
easily be corrected by having a small load across the output
to insure that the negative peak is always less than the
positive.
However, a minimum load does not correct a more serious
problem that occurs when there is a large load step from a
heavy load to no load. When the load current is interrupted,
the output capacitor charges higher than the regulated
voltage. As the regulation loop is starting to respond by
slewing to a minimum duty cycle, the excessive voltage on
the output capactior starts to discharge back to the primary.
This results with a large negative current at the beginning of
the duty cycle, which causes the duty cycle to be terminated
very early. The imbalance of the applied volt-seconds to the
power transformer may saturate the power transformer and
damage the power bridge.
Another scenario is that the current sensing transformer
itself may saturate, which will also damage the bridge. The
control loop cannot maintain balanced alternate half cycles
applied to the power transformer without valid current sense
information.
There are two solutions to this problem. Figure 16 illustrates
the placements of two current sensing transformers, one on
each drain leg of the bottom FETs.
400V RTN
FIGURE 13. PRIMARY SIDE CURRENT SENSING CIRCUIT
UTILIZING ONE CT
PRIMARY
TRANSFORMER
VOLTAGE
PRIMARY
TRANSFORMER
CURRENT
VOLTAGE
ACROSS RS
FIGURE 14. PERFORMANCE OF CURRENT SENSING
OUTPUT
PRIMARY
TRANSFORMER
VOLTAGE
PRIMARY
TRANSFORMER
CURRENT
VOLTAGE
ACROSS RS
FIGURE 15. NO LOAD TO SENSE VOLTAGE ACROSS RS
6
AN1341.0
September 13, 2007
Application Note 1341
In this configuration, only positive current flowing into the
drains of the bottom FETs are sensed across RS solving the
problem of rectified negative currents being impressed
across RS. An advantage of using two CTs is that there is a
full half cycle available to reset the cores of the CTs. This is
the solution used in the ISL6752EVAL1Z board.
Figure 17 is the current sense waveform as seen on SP1 of
the ISL6752EVAL1Z board with an output load of 60A.
Figure 18 shows a different current sensing implementation
that also solves the problem of Figure 13.
+400V
In this example, both drain currents of the bottom FETs are
sensed by only one CT. But there are some limitations that
must be considered. To reset the core, the minimum time
available is the duration of the selected dead time between
the two FETs on the same side of the bridge. This dead time
can be made longer to accommodate the resetting of the CT
but the consequences of reducing the maximum duty cycle
available for output voltage regulation must be considered.
If the dead time is kept short, then the peak voltage required
for resetting the core will be relatively large. For example,
assume that the dead time is selected to be 2% of the duty
cycle. The worst case reset voltage is then approximately
shown in Equation 1:
(EQ. 1)
( 0.98 ⁄ 0.02 ) • V SMAX = 49V
where VSMAX is 1V (the current limit voltage of the ISL6752).
RS
RR
RR
Notice in Figure 18 that the 400V RTN is slightly more
negative than the signal ground. This is recommended for
applications that directly drive the bottom FETs with
MOSFET drivers. If the 400V RTN and the MOSFET drivers
are grounded, regenerative feedback will be present on the
output of the MOSFET drivers because of the presence of
the CT windings in the gate drive loop.
A variation of the current sense circuit of Figure 18 is to
place the current sensing transformer in the common drain
lead of the two high side FETs, as shown in Figure 19.
400V RTN
FIGURE 16. PLACEMENT OF TWO CURRENT SENSING
TRANSFORMERS
The circuits of Figures 18 and 19 give exactly the same
performance, but the problem associated with the gate
drives (as explained in Figure 18) is avoided. The
disadvantage of placing the CT at this location is that the CT
must be designed with 400VDC operational insulation.
+400V
RS
RR
400V RTN
FIGURE 17. CURRENT SENSE WAVEFORM AT SP1 OF
ISL6752EVAL1Z BOARD
7
FIGURE 18. CURRENT SENSING TRANSFORMERS
AN1341.0
September 13, 2007
Application Note 1341
Setting Up
+400V
Danger
RS
-This evaluation unit should be used and operated
only by persons experienced and knowledgeable in
the design and operation of high voltage power
conversion equipment.
RR
-Use of this evaluation unit constitutes acceptance
of all risk inherent in the operation of equipment
having accessible hazardous voltage. Careless
operation may result in serious injury or death.
-Use safety glasses or other suitable eye protection.
Lab equipment required:
• DC lab power supply, 13VDC @ 200mA minimum
• 400VDC regulated lab power supply, 2.5ADC min with
current limit
• Fan to cool heatsinks
• Oscilloscope, digital preferred with 4 channels, 20MHz
minimum bandwidth
400V RTN
FIGURE 19. CURRENT SENSING TRANSFORMERS IN THE
COMMON DRAIN LEAD
• DC load, 80A min, >750W
• DC Mulitmeter
Conclusion
This application note investigates the use of MOSFETs as
synchronous rectifiers to replace conventional diodes. The
advantanges of improved power efficiency and load transient
are reviewed along with implemention problems that must be
solved.
References
[1] Fred Greenfeld, Intersil Application Note AN1246,
“Techniques to Improve ZVS Full-bridge Performance”
[2]Fred Greenfeld, Intersil Application Note AN1262,
“Designing with the ISL6752, ISL6753 ZVS Full-bridge
Controllers”
Appendix
The following sections cover the set-up of the
ISL6752EVAL1Z board. Also included are the bill of
materials, schematic, measured waveforms, parameters and
pcb layout.
Connect the DC load to the output of the evaluation board.
Terminal P102 is negative and terminal P104 is positive.
Adjust the load to zero. With both supplies turned off,
connect the 13VDC supply to +13V (P3) and PGND (P4).
Connect the 400V supply to +400V (P1) and 400V RTN (P2).
Turn on the 13V supply and adjust the current limit to
200mA. Adjust the voltage to +13.0VDC. The lab supply
current should be approximately 125mA.
Caution
A voltage clamp, D3, is used to protect the primary
side control circuit from catastrophic damage
should the high voltage bridge fail. In order to
prevent this clamp from conducting, do not adjust
the 13VDC lab supply over 13.5VDC.
Turn on the 400V supply and adjust the current limit to 2.5A.
Adjust the voltage to 400VDC. Do not exceed 450VDC! The
current should be approximately 45mA. Turn on the fan and
direct the air flow through the heatsinks mounted on the
bottom of the board. Using TP120 and TP121, the output
voltage should be 12 ±0.5VDC.
The output load and input voltage can now be safely
adjusted. Because there is no thermal shut down circuit, it is
important to maintain adequate airflow over the heatsinks,
especially when applying large loads.
8
AN1341.0
September 13, 2007
Application Note 1341
Waveforms
In Figure 20, the Drain-Source voltage of the low side FETs
is displayed relative to the gate voltage to highlight the ZVS
performance of the bridge. The load is at the rated 50A.
Notice that full ZVS is not achieved because the minimum
resonance voltage is about 160VDC. Even though this not is
an optimum design, 85% of the switching losses are still
recovered. To improve the ZVS performance, a future
version of a ZVS topology evaluation board will use FETs
with less body capacitance to achieve optimum ZVS.
Alternatively, improvements to the ZVS performance can be
made by increasing the leakage inductance of the
transformer or by using saturable inductor snubbers for the
output SRs. For more information, see application note
AN1246, “Techniques to Improve ZVS Full-bridge
Performance.”
NO LOAD
RESONANCE
VALLEY
GATE THRESHOLD
VOLTAGE
FIGURE 20. DRAIN SOURCE VOLTAGE OF THE LOW SIDE FET
60A LOAD
50A LOAD
1V CURRENT
LIMIT
FIGURE 21. CURRENT SENSE VOLTAGE ON SP1 AT NO LOAD, 50A AND 60A (CURRENT LIMIT)
50A LOAD
NO LOAD
CURRENT
SENSE
CURRENT
SENSE
PRIMARY
CURRENT
PRIMARY
CURRENT
FIGURE 22. PRIMARY TRANSFORMER CURRENT
9
AN1341.0
September 13, 2007
Application Note 1341
PRIMARY
CURRENT
CURRENT SENSE
CURRENT SENSE
NO RINGING ON
HIGH VOLTAGE
SWITCHING
TRANSITIONS
VDS
VDS
VGS
FIGURE 23. PRIMARY GATE DRIVE AND HIGH VOLTAGE
SWITCHING ON BOTTOM BRIDGE FETS
SYNCHRONOUS
RECTIFIER GATE
DRIVE (TP116)
PRIMARY
CURRENT
GATE TURNED
ON AT THE
VALLEY OF THE
RESONANCE
VGS
FIGURE 24. PRIMARY GATE DRIVE AND HIGH VOLTAGE
SWITCHING ON BOTTOM BRIDGE FETS
(EXPANDED SWEEP)
SECONDARY SIDE
TRANSFORMER
VOLTAGE (TP119)
SECONDARY SIDE
TRANSFORMER
VOLTAGE (TP118)
SYNCHRONOUS
RECTIFIER GATE
DRIVE (TP115)
FIGURE 25. SECONDARY TRANSFORMER VOLTAGE AND
SYNCHRONOUS GATE DRIVE VOLTAGE
FIGURE 26. OUTPUT VOLTAGE RIPPLE, 20MHZ (SP101)
FIGURE 27. OUTPUT VOLTAGE RIPPLE AND NOISE, 1GHZ
(SP101)
FIGURE 28. OUTPUT LOAD TRANSIENT, 0A TO 12A
10
AN1341.0
September 13, 2007
Application Note 1341
100
EFFICIENCY (%)
90
80
70
60
50
40
30
0
10
20
30
40
50
60
LOAD (AMPS)
FIGURE 29. OUTPUT LOAD TRANSIENT, 12A TO 30A
FIGURE 30. EFFICIENCY
TABLE 2. LINE AND LOAD REGULATION
TABLE 3. EFFICIENCY
VIN
VOUT AT NO
LOAD
VOUT AT 25A
LOAD
VOUT at 50A
LOAD
VIN
IIN
VOUT
IOUT
EFFICIENCY
(%)
POWER
RATED
POWER
425
11.833
11.783
11.763
400
0.07
11.84
1
41
12
2
400
11.845
11.799
11.773
400
0.13
11.83
3
67
35
6
375
11.849
11.808
11.779
400
0.19
11.82
5
77
59
10
350
11.852
11.815
11.784
400
0.25
11.82
5
77
59
10
325
11.856
11.821
11.787
400
0.35
11.80
10
86
118
20
400
0.50
11.79
15
89
177
29
400
0.66
11.79
20
90
236
39
400
0.97
11.78
30
91
353
59
400
1.29
11.77
40
92
471
78
400
1.61
11.76
50
91
588
98
400
1.95
11.75
60
91
705
118
References
[1] Fred Greenfeld, Intersil Application Note AN1246,
“Techniques to Improve ZVS Full-bridge Performance”
[2]Fred Greenfeld, Intersil Application Note AN1262,
“Designing with the ISL6752, ISL6753 Full-Bridge
Controllers”
11
AN1341.0
September 13, 2007
ISL6752EVAL1Z Schematic
VIN+
F1
P1
0464004
2
C1
33UF
C2
33UF
C3
33UF
C5
0.1UF
1
Q1
FQB6N50
P2
3
3
R13
10K
PGND
R14
CR3
4.99
SS12
P4
2
E
CR4
R16
1
2
1
SS12
P0544
CS
R17
10K
3
8
5
C14
1000PF
2
Q5
BSS138
1
1000PF
R12
20
1
Q6
BSS138
6
4.99
12
C13
1UF
2
VDD
3
IN
T2
1
1
4
8
3
P8205
2
Q4
FQB6N50
1
R42
4.7
OUT
SR_A
12V
600W 11
12
9
10
3
CS
R19
100
IN
T4
7
3
2
R21
2
8
OUTUL
100
3
3
SR_B
PA1650
U5
UCC37324DGN
R18
100
6
7
C16
1UF
TP5
OUT
13
14
300-400V
200KHZ
1
NC
4
NC
5
NC
8
NC
VDD
2
7
4.7
U5
U4
UCC37324DGN
IN
6
R44
5
C12
1UF
7
R27
30.1
15
16
6
7
TP4
CR1
BAT54S
T1
2
3
FB_L
IN
C121
3300PF
C20
3300PF
3
C15
T3
4
100
3
R15
20
2
VIN-
R45
Q2
FQB6N50
1
C4
33UF
2
U4
4
CR2
BAT54S
3
P8205
TP11
R20
10K
1
R43
5
1
1
Q3
FQB6N50
4.7
R28
30.1
3
Application Note 1341
R23
10K
C10
OUTLL
R4
VREF
TP6
1000PF
20K
R26
VERR
0.1UF
OUT
2.21K
1
OUT
2
3
R5
C9
0.1UF
R6
665
15.4K
R7
6
7
20K
R8
CS
4
5
TP7
R22
U1
VREF
CS
R24
100
TP13
C11
8
IN
499
VREF
VERR
14
13
OUTUL
OUTUR
RTD
OUTUR
12
TP10
11
OUTLLN
RESDEL
CT
OUT
OUTLLN
10
OUTLRN
OUTLLN
9
CS
TP12
10
15
OUTLL
OUTLR
CTBUF
OUTLR
VDD
OUT
16
VDD
VADJ
TP8
GND
ISL6752AAZA
VDD
OUT
R2
18.2
R9
1.27K
R3
33.2
SP1
C8
1000PF
CS
R10
45.3K
C6
180PF
OUTLRN
D4
BIAS
OUT
MURS160T3
OUTLRN
P3
TP9
C7
47PF
D3
1.5SMC15AT3G
+12VOUT
IN
R130
18K
R128
499
R129
9.09K
VERR
IN
R131
649
R127
499
C122
VREF
R25
20
IN
CR106
U2
4
3
1
COLLECTOR
2
EMITTER
CR5
BAT54
C17
330PF
3
C120
CATHODE
R132
0.033UF
100K
1K
BAT54
PS2701
2
R11
10K
100PF
1
R126
ANODE
3
1
3
1
DRAWN BY:
TIM KLEMANN
3
Q17
PMBT3906
TP2
3
VR102
BZX84C6V8LT1
A
1
100
U102
LM431BIM3
C
2
R1
1
AN1341.0
September 13, 2007
C18
0.1UF
SS
NC
ENABLE
E
R133
2.15K
UPDATED
2
E
RELEASED
E
BY:
BY:
DATE:
04/17/2007
DATE:
DATE:
TESTER
ENGINEER:
RICHARD GARCIA
TITLE:
MASK#
OUT
DATE:
ISL6752
EVALUATION BOARD
SCHEMATIC
HRDWR ID
REV.
ISL6752EVAL1Z
FILENAME:
SHEET
1
B
2
ISL6752EVAL1Z Schematic
(Continued)
SP101
+12VOUT
TP120
OUT
E
L103
SR_B
IN
Q107
SR_B
Q108
3.3UH
Q110
Q109
2
1
2
4
3
1
2
4
3
1
2
4
3
1
2
4
3
7
6
5
7
6
5
7
6
5
7
6
5
TP119
IRF6668
IRF6668
IRF6668
1
C137
D1
DNP
UPS3100E3
R40
3
P104
R41
C127
0.1UF
R29
DNP
R149
1.5
13
C129
0.1UF
Q111
SR_A
TP118
Q112
Q113
7
5
6
7
5
6
7
5
6
7
5
6
3
4
2
1
3
4
2
1
3
4
2
1
3
4
IRF6668
IRF6668
C134
2200UF
C135
2200UF
C136
2200UF
R148
1K
C132
10UF
P103
750
R31
DNP
R32
DNP
R30
DNP
R150
1.5
Q114
2
1
IRF6668
C133
2200UF
750
IRF6668
P11
SGND
R33
TP121
750
R37
3
D2
UPS3100E3
IRF6668
1
C138
E
750
DNP
2
L102
SR_A
IN
3.3UH
Application Note 1341
LLN
TP115
LRN
TP116
VREF
IN
R36
20K
SS
R38
10K
R143
20K
R39
R35
IN
49.9K
1M
8
1
ANODE
2
CATHODE
3
1
2
4
C123
10UF
U6
U7
LM393M
COLLECTOR
4
EMITTER
3
E
PS2701
R34
30.1K
E
VDD
5
7
IN
6
C19
1UF
U7
LM393M
1
OUTLLN
CR108
6
2
C22
7
T6
U3
EL7212
1UF
3
4
4
R140
249
8
E
C125
1000PF
1
2
CR107
P0584
U108
1IN1
GND
1IN2
1OUT
2IN1
VCC
2IN2
2OUT
8
7
6
5
TPS2814
BAT54A
SEC
5
U3
EL7212
3
1
3
7
10
IN
2
SEC
1
PRI
OUTLRN
3
4
IN
2
2
E
E
3
3
4
1
U109
1IN1
GND
1IN2
1OUT
2IN1
VCC
2IN2
2OUT
8
7
6
5
TPS2814
BAT54A
R139
249
E
C126
0.1UF
C124
1000PF
DRAWN BY:
TIM KLEMANN
RELEASED
UPDATED
E
E
BY:
BY:
DATE:
04/17/2007
DATE:
DATE:
TESTER
ENGINEER:
RICHARD GARCIA
TITLE:
DATE:
ISL6752
EVALUATION BOARD
SCHEMATIC
AN1341.0
September 13, 2007
Application Note 1341
TABLE 4. ISL6752EVAL1Z BILL OF MATERIALS
PART NUMBER
REF DES
QTY
VALUE
F1
1
4.0A
C12, C13,
C16, C19,
C22
5
1µF
D3
131-4353-00
464004
TOL.
VOLTAGE PACKAGE MANUFACTURER
DESCRIPTION
250V
SMD
LITTELFUSE
NANO2 UMF Fast-Acting Fuse
25V
805
AVX
Multilayer Capacitor
1
SMC
ON-SEMI
15V 1500W Transient Voltage
Suppressor
SP1, SP101
2
CONN
TEKTRONIX
Scope Probe Test Point PCB
Mount
1514-2
P1 to P4, P11
5
THOLE
KEYSTONE
Test Point Turret 0.150 Pad
0.100 Thole
5016
TP2,TP4 to
TP13,TP115,
TP116,
TP118 to
TP121
17
SMT
KEYSTONE
Compact Surface Mount Test
Point Pad
BAT54
CR5, CR106
2
SOT-23
DIODES
30V Schottky Diode
BAT54A
CR107,
CR108
2
SOT-23
DIODES
30V Schottky Diode
BAT54S
CR1, CR2
2
SOT-23
DIODES
Schottky Barrier (Double) Diode
BSS138LT1
Q5, Q6
2
SOT-23
ON-SEMI
200mA 50V N-Channel Power
MOSFET
BZX84C6V8LT1
VR102
1
SOT-23
ON-SEMI
6.8V 225mW Zener Voltage
Regulator
C1608COG2A331J
C17
1
330pF
5%
100V
603
TDK
Multilayer Capacitor
C2012COG1H470K
C7
1
47pF
10%
50V
805
TDK
Multilayer Capacitor
C2012COG2A181J
C6
1
180pF
5%
100V
805
TDK
Multilayer Capacitor
C2012X7R2A102K
C8, C10,
C14, C15
4
1000pF
10%
100V
805
TDK
Multilayer Capacitor
C4532X7R2J104K
C5
1
0.1µF
10%
630V
1812
TDK
Multilayer Capacitor
EL7212CS
U3
1
SOIC
INTERSIL
HS Dual Channel Power
MOSFET Driver
ERJ6ENF3012
R34
1
30.1k
1%
805
PANASONIC
Precision Thick Film Chip
Resistor
ERJ6ENF4R99
R14, R16
2
4.99
1%
805
PANASONIC
Precision Thick Film Chip
Resistor
FQB6N50
Q1 to Q4
4
D2PAK
FAIRCHILD
500V N-Channel MOSFET
C20, C121
2
3300pF
10%
250V
2220
MURATA
Chip Monolithic Capacitor
C124, C125
2
1000pF
10%
100V
603
GENERIC
Multilayer Capacitor
C126
1
0.1µF
10%
25V
603
GENERIC
Multilayer Capacitor
C122
1
100pF
5%
50V
805
GENERIC
Multilayer Capacitor
C9, C11, C18
3
0.1µF
10%
100V
805
GENERIC
Multilayer Capacitor
C127, C129
2
0.1µF
10%
100V
805
GENERIC
Multilayer Capacitor
C120
1
0.033µF
10%
50V
805
GENERIC
Multilayer Capacitor
C137, C138
2
DNP
5%
DNP
805
GENERIC
Multilayer Capacitor (DNP)
C123
1
10µF
20%
25V
1206
GENERIC
Multilayer Capacitor
C132
1
10µF
20%
25V
1206
GENERIC
Multilayer Capacitor
08053D105KAT2A
1.5SMC15AT3G
GA355QR7GF332KW01L
14
10%
AN1341.0
September 13, 2007
Application Note 1341
TABLE 4. ISL6752EVAL1Z BILL OF MATERIALS (Continued)
PART NUMBER
REF DES
QTY
VALUE
TOL.
R130
1
18k
0.10%
805
GENERIC
Metal Film Chip Resistor
R22
1
10
1%
805
GENERIC
Thick Film Chip Resistor
R12, R15,
R25
3
20
1%
805
GENERIC
Thick Film Chip Resistor
R42 to R44
3
4.7
1%
805
GENERIC
Thick Film Chip Resistor
R1, R18,
R19, R21,
R24
5
100
1%
805
GENERIC
Thick Film Chip Resistor
R126
1
1k
1%
805
GENERIC
Thick Film Chip Resistor
R11, R13,
R17, R20,
R23, R38
6
10k
1%
805
GENERIC
Thick Film Chip Resistor
R132
1
100k
1%
805
GENERIC
Thick Film Chip Resistor
R39
1
1M
1%
805
GENERIC
Thick Film Chip Resistor
R9
1
1.27k
1%
805
GENERIC
Thick Film Chip Resistor
R6
1
15.4k
1%
805
GENERIC
Thick Film Chip Resistor
R2
1
18.2
1%
805
GENERIC
Thick Film Chip Resistor
R4, R7, R36,
R143
4
20k
1%
805
GENERIC
Thick Film Chip Resistor
R133
1
2.15k
1%
805
GENERIC
Thick Film Chip Resistor
R26
1
2.21k
1%
805
GENERIC
Thick Film Chip Resistor
R139, R140
2
249
1%
805
GENERIC
Thick Film Chip Resistor
R27, R28
2
30.1
1%
805
GENERIC
Thick Film Chip Resistor
R3
1
33.2
1%
805
GENERIC
Thick Film Chip Resistor
R10
1
45.3k
1%
805
GENERIC
Thick Film Chip Resistor
R8, R127,
R128
3
499
1%
805
GENERIC
Thick Film Chip Resistor
R35
1
49.9k
1%
805
GENERIC
Thick Film Chip Resistor
R131
1
649
1%
805
GENERIC
Thick Film Chip Resistor
R5
1
665
1%
805
GENERIC
Thick Film Chip Resistor
R129
1
9.09k
1%
805
GENERIC
Thick Film Chip Resistor
R45
1
100
1%
1206
GENERIC
Thick Film Chip Resistor
R148
1
1k
1%
1206
GENERIC
Thick Film Chip Resistor
R149, R150
2
1.5
1%
2512
GENERIC
Thick Film Chip Resistor
R33, R37,
R40, R41
4
750
5%
2512
GENERIC
Thick Film Chip Resistor
R29 to R32
4
DNP
1%
2512
GENERIC
Thick Film Chip Resistor (DNP)
Q107 to
Q114
8
FET
IR
DIRECTFET Power MOSFET
U1
1
SSOP
INTERSIL
ZVS Full-Bridge Current-Mode
Controller
KPA8CTP
P103, P104
2
CONN
BURNDY
Wire Connector Lug
LM393M
U7
1
ALL
NATIONAL
Low Power Low Offset Voltage
Dual Comparator
IRF6668
ISL6752AAZA
15
VOLTAGE PACKAGE MANUFACTURER
DESCRIPTION
AN1341.0
September 13, 2007
Application Note 1341
TABLE 4. ISL6752EVAL1Z BILL OF MATERIALS (Continued)
PART NUMBER
REF DES
QTY
VALUE
TOL.
VOLTAGE PACKAGE MANUFACTURER
LMV431AIMF
U102
1
SOT23
MURS160T3
D4
1
P0544
T3
P0584
DESCRIPTION
NATIONAL
Low-Voltage (1.24V) Adjustable
Shunt Regulator
SMB
ON-SEMI
Ultrafast Power Rectifier
1
SMD
PULSE
Gate Drive Transformer
T6
1
SMD
PULSE
Offline Gate Drive Transformers
P8205
T2, T4
2
SMD
PULSE
Smt Current Sense Transformer
PA1650
T1
1
SMD
PULSE
Full Bridge Transformer
PMBT3906
Q17
1
SOT
Philips
-40V 200mA PNP Switching
Transistor
PS2701-1
U2, U6
2
SOP
NEC
High Isolation SOP Multi
Photocoupler
SER2814L-332KL
L102, L103
2
SMD
CoilCraft
Power Inductor High Current
SS12T3
CR3, CR4
2
SMA
ON-SEMI
1A 20V SCHOTTKY POWER
RECTIFIER
U108, U109
2
SOIC
TI
Dual High-speed MOSFET
Driver
UCC37324DGN
U4, U5
2
MSOP
TI
Dual 4 Power Driver
UPS3100E3
D1, D2
2
POWER
DIODES
3A High Voltage Schottky
Rectifier
UUG1C222MNR1MS
C133 to C136
4
2200µF
20%
16V
SMD
NICHICON
Aluminum Electrolytic Capacitor
UUG2W330MNR1ZD
C1 to C4
4
33µF
20%
450V
SMD
NICHICON
Aluminum Electrolytic Capacitor
TPS2814D
3.3µH
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
16
AN1341.0
September 13, 2007
ISL6752EVAL1Z Layout
DANGER
L103
TP119
Q1
Q109
Q108
Q110
Q107
R33
T1
C137
16
17
C127
1
R41
Q2
F1
+
Pb
+
HIGH VOLTAGE PRESENT
ELECTRICAL HAZARD
OPERATE WITH EXTREME
CAUTION
- THIS EVALUATION UNIT SHOULD BE USED AND OPERATED
ONLY BY PERSIONS EXPERENCED AND KNOWLEDGABLE IN THE
DESIGN AND OPERATION OF HIGH VOLTAGE POWER CONVERSION
EQUIPMENT.
- USE OF THIS EVALUATION UNIT CONSTITUTES ACCEPTANCE
OF ALL RISKS INHERENT IN THE OPERATION OF EQUIPMENT
HAVING ACCESSIBLE HAZARDOUS VOLTAGES. CARELESS
OPERATION MAY RESULT IN SERIOUS INJURY OR DEATH.
- USE SAFTY GLASSES OR OTHER SUITABLE EYE PROTECTION.
P103
TP121
D1
C5
R14
C125
TP115
Q114
TP5
CR3
T3
R30 R32
C132
SP101
C134
P104
C136
Q112
T2
T4
C3
C135
R29 R149
C129
R15
R17
R31
U109
Q6
C133
R139
C124
C126
TP116
R140
Q5
TP4
R13
R12
R148
CR4
C15
U108
R16
C14
C4
+
TP120
D2
R150
Q111
R40
Q113
R37
C138
Q4
8
TP118
+
9
+
Q3
C2
C121
+
R27
R34
P1
R1
400V RTN
P2
TP2
P4
ENABLE
PGND
CS
CR108
C123
T6
C22
R132
R131 R130
D3
R133
U102
4
1
C122
R19
TP7
SP1
L102
C120
U1
R21
U3
R9 R6
C8 R8
C6 C7
R2
+400V
R7
R129
U2
D4
R3
C18
R25
C17
R10
10
R39
R22
R5
Q17
CR107
R38
7
C11
R36
R26
C10
R4
C9
C19
R35
U6
U7 R24
TP6
R143
C12
R23
R18
CR5
+
R11
C1
R42
R20
U4 R44
R28
U5
R43
R45
C20
CR1
C13
C16
CR2
TP11
TP10
TP12
TP13
P3
TP8
TP9
OUTUL
OUTUR
OUTLR
OUTLL
+13V
OUTLLN
OUTLRN
R126 CR106 VR102
R127 R128
P11
SGND
FIGURE 31. LAYER 1, TOP
ISL6752EVAL1Z REV.B
Application Note 1341
+
AN1341.0
September 13, 2007
ISL6752EVAL1Z Layout
y
(Continued)
DANGER
- THIS EVALUATION UNIT SHOULD BE USED AND OPERATED
ONLY BY PERSIONS EXPERENCED AND KNOWLEDGABLE IN THE
DESIGN AND OPERATION OF HIGH VOLTAGE POWER CONVERSION
EQUIPMENT.
- USE OF THIS EVALUATION UNIT CONSTITUTES ACCEPTANCE
OF ALL RISKS INHERENT IN THE OPERATION OF EQUIPMENT
HAVING ACCESSIBLE HAZARDOUS VOLTAGES. CARELESS
OPERATION MAY RESULT IN SERIOUS INJURY OR DEATH.
- USE SAFTY GLASSES OR OTHER SUITABLE EYE PROTECTION.
L103
TP119
Q1
Q109
Q108
Q110
Q107
R33
T1
C137
16
18
C127
1
R41
Q2
F1
+
Pb
+
HIGH VOLTAGE PRESENT
ELECTRICAL HAZARD
OPERATE WITH EXTREME
CAUTION
ISL6752EVAL1Z REV.B
P103
TP121
D1
C5
R14
C125
TP115
Q114
TP5
CR3
T3
R30 R32
C132
SP101
C134
P104
C136
Q112
T2
T4
C3
C135
R29 R149
C129
R17
R31
U109
Q6
R15
C133
R139
C124
C126
TP116
R140
C15
Q5
TP4
R13
R12
R148
CR4
U108
R16
C14
C4
+
TP120
D2
R150
Q111
R40
Q113
R37
C138
Q4
8
TP118
+
9
+
Q3
C2
C121
+
R27
R34
P1
R1
400V RTN
P2
TP2
P4
ENABLE
PGND
CS
CR108
C123
T6
C22
R132
R131 R130
D3
R133
U102
4
1
C122
R19
TP7
SP1
L102
C120
U1
R21
U3
R9 R6
C8 R8
C6 C7
R2
+400V
R7
R129
U2
D4
R3
C18
R25
C17
R10
10
R39
R22
R5
Q17
CR107
R38
7
C11
R36
R4
C9
R26
C10
C19
R35
U6
U7 R24
TP6
R143
C12
R23
R18
CR5
+
R11
C1
R42
R20
U4 R44
R28
U5
R43
R45
C20
CR1
C13
C16
CR2
TP11
TP10
TP12
TP13
P3
TP8
TP9
OUTUL
OUTUR
OUTLR
OUTLL
+13V
OUTLLN
OUTLRN
R126 CR106 VR102
R127 R128
P11
SGND
FIGURE 32. LAYER 2
ISL6752EVAL1Z REV.B
Application Note 1341
+
AN1341.0
September 13, 2007
ISL6752EVAL1Z Layout
y
(Continued)
DANGER
- THIS EVALUATION UNIT SHOULD BE USED AND OPERATED
ONLY BY PERSIONS EXPERENCED AND KNOWLEDGABLE IN THE
DESIGN AND OPERATION OF HIGH VOLTAGE POWER CONVERSION
EQUIPMENT.
- USE OF THIS EVALUATION UNIT CONSTITUTES ACCEPTANCE
OF ALL RISKS INHERENT IN THE OPERATION OF EQUIPMENT
HAVING ACCESSIBLE HAZARDOUS VOLTAGES. CARELESS
OPERATION MAY RESULT IN SERIOUS INJURY OR DEATH.
- USE SAFTY GLASSES OR OTHER SUITABLE EYE PROTECTION.
L103
TP119
Q1
Q109
Q108
Q110
Q107
R33
T1
C137
16
19
C127
1
R41
Q2
F1
+
Pb
+
HIGH VOLTAGE PRESENT
ELECTRICAL HAZARD
OPERATE WITH EXTREME
CAUTION
ISL6752EVAL1Z REV.B
P103
TP121
D1
C5
R14
C125
TP115
Q114
TP5
CR3
T3
R30 R32
C132
SP101
C134
P104
C136
Q112
T2
T4
C3
C135
R29 R149
C129
R17
R31
U109
Q6
R15
C133
R139
C124
C126
TP116
R140
C15
Q5
TP4
R13
R12
R148
CR4
U108
R16
C14
C4
+
TP120
D2
R150
Q111
R40
Q113
R37
C138
Q4
8
TP118
+
9
+
Q3
C2
C121
+
R27
R34
P1
R1
400V RTN
P2
TP2
P4
ENABLE
PGND
CS
CR108
C123
T6
C22
R132
R131 R130
D3
R133
U102
4
1
C122
R19
TP7
SP1
L102
C120
U1
R21
U3
R9 R6
C8 R8
C6 C7
R2
+400V
R7
R129
U2
D4
R3
C18
R25
C17
R10
10
R39
R22
R5
Q17
CR107
R38
7
C11
R36
R4
C9
R26
C10
C19
R35
U6
U7 R24
TP6
R143
C12
R23
R18
CR5
+
R11
C1
R42
R20
U4 R44
R28
U5
R43
R45
C20
CR1
C13
C16
CR2
TP11
TP10
TP12
TP13
P3
TP8
TP9
OUTUL
OUTUR
OUTLR
OUTLL
+13V
OUTLLN
OUTLRN
R126 CR106 VR102
R127 R128
P11
SGND
FIGURE 33. LAYER 3
ISL6752EVAL1Z REV.B
Application Note 1341
+
AN1341.0
September 13, 2007
ISL6752EVAL1Z Layout
(Continued)
DANGER
L103
TP119
Q1
Q108
C137
16
20
Q110
Q107
C127
T1
R33
Q109
1
F1
R41
Q2
+
Pb
+
HIGH VOLTAGE PRESENT
ELECTRICAL HAZARD
OPERATE WITH EXTREME
CAUTION
- THIS EVALUATION UNIT SHOULD BE USED AND OPERATED
ONLY BY PERSIONS EXPERENCED AND KNOWLEDGABLE IN THE
DESIGN AND OPERATION OF HIGH VOLTAGE POWER CONVERSION
EQUIPMENT.
- USE OF THIS EVALUATION UNIT CONSTITUTES ACCEPTANCE
OF ALL RISKS INHERENT IN THE OPERATION OF EQUIPMENT
HAVING ACCESSIBLE HAZARDOUS VOLTAGES. CARELESS
OPERATION MAY RESULT IN SERIOUS INJURY OR DEATH.
- USE SAFTY GLASSES OR OTHER SUITABLE EYE PROTECTION.
P103
TP121
D1
C5
R14
C125
TP115
Q114
TP5
CR3
T3
R30 R32
C132
SP101
C134
P104
C136
Q112
T2
T4
C3
C135
R29 R149
C129
R15
R17
R31
U109
TP116
Q6
C133
R139
C124
C126
Q5
TP4
R13
R12
R140
C15
R148
CR4
U108
R16
C14
C4
+
TP120
+
D2
R150
R40
Q111
R37
C138
Q4
8
TP118
+
9
+
Q3
C2
C121
+
R27
R34
P1
400V RTN
P2
TP2
P4
ENABLE
PGND
CS
CR108
C123
T6
C22
R132
R131 R130
D3
R133
U102
4
1
C122
R19
TP7
SP1
L102
C120
U1
R21
U3
R9 R6
C8 R8
C6 C7
R2
+400V
R1
R7
R129
U2
D4
R3
C18
R25
C17
R10
10
R39
R22
R5
Q17
CR107
R38
7
C11
R36
R26
C10
R4
C9
C19
R35
U6
U7 R24
TP6
R143
C12
R23
R18
CR5
+
R11
C1
R42
R20
U4 R44
R28
U5
R43
R45
C20
CR1
C13
C16
CR2
TP11
TP10
TP12
TP13
P3
TP8
TP9
OUTUL
OUTUR
OUTLR
OUTLL
+13V
OUTLLN
OUTLRN
R126 CR106 VR102
R127 R128
P11
SGND
FIGURE 34. LAYER 4, BOTTOM
ISL6752EVAL1Z REV.B
Application Note 1341
Q113
AN1341.0
September 13, 2007
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