SiHF28N60EF Datasheet

SiHF28N60EF
www.vishay.com
Vishay Siliconix
EF Series Power MOSFET with Fast Body Diode
FEATURES
PRODUCT SUMMARY
VDS (V) at TJ max.
• Fast body diode MOSFET using E series
technology
• Reduced trr, Qrr, and IRRM
• Low figure-of-merit (FOM): Ron x Qg
• Low input capacitance (Ciss)
• Low switching losses due to reduced Qrr
• Ultra low gate charge (Qg)
• Avalanche energy rated (UIS)
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
650
RDS(on) max. at 25 °C (Ω)
VGS = 10 V
0.123
Qg (Max.) (nC)
120
Qgs (nC)
17
Qgd (nC)
33
Configuration
Single
D
TO-220 FULLPAK
APPLICATIONS
• Telecommunications
- Server and telecom power supplies
• Lighting
- High intensity discharge (HID)
- Light emitting diodes (LEDs)
• Consumer and computing
- ATX power supplies
• Industrial
- Welding
- Battery chargers
• Renewable energy
- Solar (PV inverters)
• Switch mode power suppliers (SMPS)
• Applications using the following topologies
- LLC
- Phase shifted bridge (ZVS)
- 3-level inverter
- AC/DC bridge
G
G D S
S
N-Channel MOSFET
ORDERING INFORMATION
Package
TO-220 FULLPAK
Lead (Pb)-free and Halogen-free
SiHF28N60EF-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
600
Gate-Source Voltage
VGS
± 30
Continuous Drain Current (TJ = 150 °C) e
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Current a
ID
IDM
Linear Derating Factor
UNIT
V
28
18
A
75
0.31
W/°C
Single Pulse Avalanche Energy b
EAS
691
mJ
Maximum Power Dissipation
PD
39
W
TJ, Tstg
-55 to +150
°C
Operating Junction and Storage Temperature Range
Drain-Source Voltage Slope
TJ = 125 °C
Reverse Diode dV/dt d
Soldering Recommendations (Peak Temperature) c
for 10 s
dV/dt
70
13
300
V/ns
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. VDD = 50 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 Ω, IAS = 7 A.
c. 1.6 mm from case.
d. ISD ≤ ID, dI/dt = 100 A/μs, starting TJ = 25 °C.
e. Limited by maximum junction temperature.
S15-0277-Rev. B, 23-Feb-15
Document Number: 91604
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHF28N60EF
www.vishay.com
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
65
Maximum Junction-to-Case (Drain)
RthJC
-
3.2
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage (N)
Gate-Source Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
Forward Transconductance
VDS
VGS = 0 V, ID = 250 μA
600
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.76
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
VGS = ± 20 V
-
-
± 100
nA
IGSS
IDSS
RDS(on)
gfs
VGS = ± 30 V
-
-
±1
μA
VDS = 480 V, VGS = 0 V
-
-
1
μA
VDS = 480 V, VGS = 0 V, TJ = 125 °C
VGS = 10 V
ID = 14 A
VDS = 30 V, ID = 14 A
-
-
2
mA
-
0.107
0.123
Ω
-
9.7
-
S
Dynamic
Input Capacitance
Ciss
VGS = 0 V,
-
2714
-
Output Capacitance
Coss
VDS = 100 V,
-
123
-
f = 1 MHz
-
6
-
-
98
-
-
356
-
Reverse Transfer Capacitance
Crss
Effective output capacitance, energy
related a
Co(er)
Effective output capacitance, time
related b
Co(tr)
pF
VGS = 0 V, VDS = 0 V to 480 V
-
80
120
-
17
-
-
33
-
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Turn-On Delay Time
td(on)
-
24
48
tr
-
40
80
-
82
123
-
39
78
-
0.5
-
-
-
28
-
-
70
Rise Time
Turn-Off Delay Time
td(off)
Fall Time
tf
Gate Input Resistance
Rg
VGS = 10 V
ID = 14 A, VDS = 480 V
VDD = 480 V, ID = 14 A
Rg = 9.1 Ω, VGS = 10 V
f = 1 MHz, open drain
nC
ns
Ω
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Current
ISM
Diode Forward Voltage
VSD
Reverse Recovery Time
trr
Reverse Recovery Charge
Qrr
Reverse Recovery Current
IRRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IS = 11 A, VGS = 0 V
TJ = 25 °C, IF = IS = 14 A,
dI/dt = 100 A/μs, VR = 25 V
S
-
0.9
1.2
V
-
142
284
ns
-
0.97
1.94
μC
-
13.2
-
A
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDS.
b. Coss(tr) is a fixed capacitance that gives the charging time as Coss while VDS is rising from 0 % to 80 % VDS.
S15-0277-Rev. B, 23-Feb-15
Document Number: 91604
2
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHF28N60EF
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
3.0
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
60
TJ = 25 °C
ID = 14 A
RDS(on), Drain-to-Source On-Resistance
(Normalized)
40
20
0
0
5
10
15
20
25
VDS, Drain-to-Source Voltage (V)
1.0
VGS = 10 V
0.5
-40 -20
0 20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 4 - Normalized On-Resistance vs. Temperature
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
TJ = 150 °C
Ciss
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds shorted
Crss = Cgd
Coss = Cds + Cgd
1000
C, Capacitance (pF)
ID, Drain-to-Source Current (A)
1.5
10 000
TOP
30
2.0
0
-60
30
Fig. 1 - Typical Output Characteristics
45
2.5
15
Coss
100
Crss
10
1
0
0
5
10
15
20
25
VDS, Drain-to-Source Voltage (V)
0
30
100
200
300
400
500
VDS, Drain-to-Source Voltage (V)
600
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 2 - Typical Output Characteristics
80
18
16
14
60
TJ = 150 °C
12
Coss (pF)
ID, Drain-to-Source Current (A)
5000
TJ = 25 °C
40
10
Coss
Eoss
8
500
Eoss (μJ)
ID, Drain-to-Source Current (A)
80
6
20
4
2
VDS = 28 V
0
50
0
5
10
15
20
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S15-0277-Rev. B, 23-Feb-15
25
0
0
100
200
300
VDS
400
500
600
Fig. 6 - Coss and Eoss vs. VDS
Document Number: 91604
3
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHF28N60EF
www.vishay.com
Vishay Siliconix
30
VDS = 480 V
VDS = 300 V
VDS = 120 V
20
24
ID, Drain Current (A)
VGS, Gate-to-Source Voltage (V)
24
16
12
8
18
12
6
4
0
0
0
40
80
120
Qg, Total Gate Charge (nC)
25
160
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
50
75
100
125
TC, Case Temperature (°C)
150
Fig. 10 - Maximum Drain Current vs. Case Temperature
750
VDS, Drain-to-Source Breakdown Voltage (V)
ISD, Reverse Drain Current (A)
100
TJ = 150 °C
10
TJ = 25 °C
1
VGS = 0 V
0.1
0.2
0.4
0.6
0.8
1.0
1.2
VSD, Source-Drain Voltage (V)
1.4
1.6
Fig. 8 - Typical Source-Drain Diode Forward Voltage
Operation in this Area
Limited by RDS(on)
100
725
700
675
650
625
600
ID = 250 μA
575
-60 -40 -20
0 20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 11 - Typical Drain-to-Source Voltage vs. Temperature
IDM Limited
ID, Drain Current (A)
10
100 μs
Limited by RDS(on)*
1
1 ms
0.1
10 ms
TC = 25 °C
TJ = 150 °C
Single Pulse
0.01
1
BVDSS Limited
10
100
1000
VDS, Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Fig. 9 - Maximum Safe Operating Area
S15-0277-Rev. B, 23-Feb-15
Document Number: 91604
4
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHF28N60EF
www.vishay.com
Vishay Siliconix
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
0.0001
0.001
0.01
Pulse Time (s)
0.1
1
Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case
RD
VDS
VDS
tp
VGS
VDD
D.U.T.
RG
+
- VDD
VDS
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
IAS
Fig. 13 - Switching Time Test Circuit
Fig. 16 - Unclamped Inductive Waveforms
VDS
QG
10 V
90 %
QGS
10 %
VGS
QGD
VG
td(on)
td(off) tf
tr
Charge
Fig. 14 - Switching Time Waveforms
Fig. 17 - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
L
Vary tp to obtain
required IAS
VDS
50 kΩ
D.U.T
RG
12 V
+
-
IAS
0.2 µF
0.3 µF
V DD
+
D.U.T.
-
VDS
10 V
tp
0.01 Ω
VGS
3 mA
Fig. 15 - Unclamped Inductive Test Circuit
IG
ID
Current sampling resistors
Fig. 18 - Gate Charge Test Circuit
S15-0277-Rev. B, 23-Feb-15
Document Number: 91604
5
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHF28N60EF
www.vishay.com
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 19 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91604.
S15-0277-Rev. B, 23-Feb-15
Document Number: 91604
6
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
TO-220 FULLPAK (HIGH VOLTAGE)
A
E
A1
ØP
n
d1
d3
D
u
L1
V
L
b3
A2
b2
c
b
e
MILLIMETERS
DIM.
A
A1
A2
b
b2
b3
c
D
d1
d3
E
e
L
L1
n
ØP
u
v
ECN: X09-0126-Rev. B, 26-Oct-09
DWG: 5972
MIN.
4.570
2.570
2.510
0.622
1.229
1.229
0.440
8.650
15.88
12.300
10.360
INCHES
MAX.
4.830
2.830
2.850
0.890
1.400
1.400
0.629
9.800
16.120
12.920
10.630
MIN.
0.180
0.101
0.099
0.024
0.048
0.048
0.017
0.341
0.622
0.484
0.408
13.730
3.500
6.150
3.450
2.500
0.500
0.520
0.122
0.238
0.120
0.094
0.016
2.54 BSC
13.200
3.100
6.050
3.050
2.400
0.400
MAX.
0.190
0.111
0.112
0.035
0.055
0.055
0.025
0.386
0.635
0.509
0.419
0.100 BSC
0.541
0.138
0.242
0.136
0.098
0.020
Notes
1. To be used only for process drawing.
2. These dimensions apply to all TO-220, FULLPAK leadframe versions 3 leads.
3. All critical dimensions should C meet Cpk > 1.33.
4. All dimensions include burrs and plating thickness.
5. No chipping or package damage.
Document Number: 91359
Revision: 26-Oct-09
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1
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Revision: 02-Oct-12
1
Document Number: 91000