DATASHEET

Data Sheet
Microprocessor CORE Voltage Regulator
Using Multi-Phase Buck PWM Control
Without Programmable Droop
The ISL6554 is the first controller in the Intersil Multi-Phase
family without the programmable droop feature. The
ISL6554 in combination with the HIP6601A, HIP6602A or
HIP6603A companion gate drivers and Intersil MOSFETs
form a complete solution for high-current, high slew-rate
applications. The ISL6554 regulates output voltage,
balances load currents and provides protective functions for
two to four synchronous-rectified buck-converter channels.
A novel approach to current sensing is used to reduce
overall solution cost. The voltage developed across the
lower MOSFET’s parasitic on-resistance during conduction
is sampled and fed back to the controller. This lossless
current-sensing approach allows the controller to maintain
phase-current balance between the power channels and
overcurrent protection.
• Multi-Phase Power Conversion
• Precision Channel Current Balance
- Lossless Current Sampling - Uses rDS(ON)
• Precision CORE Voltage Regulation
- 1% System Accuracy Over Temperature
- No Programmable Droop
• Microprocessor Voltage Identification Input
- 5-Bit VID Decoder
- 0.95V to 1.70V in 25mV Steps
• Fast Transient Response
• Overcurrent Protection
• Selection of 2, 3, or 4 Phase Operation
• High Ripple Frequency (80kHz to 2MHz)
• Pb-Free Available (RoHS Compliant)
Applications
The PGOOD signal is held low during soft-start until the
output voltage increases to within 4% of the programmed.
When the CORE voltage falls 9% below the programmed
VID level, an undervoltage condition is detected and results
in PGOOD transitioning low.
• Servers and Workstations
In the event of an overvoltage condition, The converter shuts
down and turns ON the lower MOSFETs to clamp and
protect the microprocessor. Overcurrent protection reduces
the regulator RMS output current to 41% of the programmed
overcurrent trip value. These features provide monitoring
and protection for the microprocessor and power system.
ISL6554CB
• Power Supply Controller for Intel® Itanium™ Processor
Family
• Voltage Regulator Modules
Ordering Information
PART NUMBER
ISL6554CB-T
ISL6554CBZ (Note)
ISL6554CBZ-T (Note)
ISL6554CBZA (Note)
ISL6554 (SOIC)
TOP VIEW
ISL6554CBZA-T (Note)
VID4 1
20 VCC
VID3 2
19 PGOOD
VID2 3
18 PWM4
VID1 4
17 ISEN4
VID0 5
16 ISEN1
COMP 6
15 PWM1
FB 7
14 PWM2
FS/DIS 8
13 ISEN2
GND 9
12 ISEN3
VSEN 10
11 PWM3
1
FN9003.3
Features
A 5-bit DAC allows digital programming of the output voltage
in 25mV steps over a range from 0.95V to 1.70V with a
system accuracy of 1%. Internal pull ups on each DAC
input make external pull-up resistors unnecessary when
interfacing with open-drain output signals.
Pinout
ISL6554
IGNS
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TERSIL
1-888-IN
TEMP. (°C)
0 to 70
PACKAGE
20 Ld SOIC
PKG.
DWG. #
M20.3
20 Ld SOIC Tape and Reel
0 to 70
20 Ld SOIC
(PB-free)
M20.3
20 Ld SOIC Tape and Reel (PB-free)
0 to 70
20 Ld SOIC
(PB-free)
M20.3
20 Ld SOIC Tape and Reel (PB-free)
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, 2004, 2005. All Rights Reserved. Intel® is a registered trademark of Intel Corporation.
Itanium™ is a trademark of Intel Corporation. All other trademarks mentioned are the property of their respective owners.
ISL6554
Block Diagram
PGOOD
VCC
POWER-ON
RESET (POR)
VSEN
X 0.9
+
-
UV
THREE
STATE
OV
LATCH
CLOCK AND
SAWTOOTH
GENERATOR
S
OVP
X1.15
+
+
-
SOFTSTART
AND FAULT
LOGIC

-
+
FS/EN
+
PWM
PWM1
-

+
-
PWM
PWM2
-
COMP
+

+
-
PWM
PWM3
-
VID4
VID3
VID2
+
D/A
+
VID1

-
E/A
+
PWM
PWM4
-
-
VID0
CURRENT
FB
CORRECTION
I_TOT
CHANNEL
DETECTOR
ISEN1
+

+
OC
PHASE
NUMBER
+
I_TRIP
+
+
ISEN2
ISEN3
ISEN4
GND
2
FN9003.3
February 11, 2005
ISL6554
Simplified Power System Diagram
SYNCHRONOUS
RECTIFIED BUCK
CHANNEL
VSEN
PWM 1
SYNCHRONOUS
RECTIFIED BUCK
CHANNEL
PWM 2
MICROPROCESSOR
ISL6554
SYNCHRONOUS
RECTIFIED BUCK
CHANNEL
PWM 3
PWM 4
VID
SYNCHRONOUS
RECTIFIED BUCK
CHANNEL
Functional Pin Description
converter. Pulling this pin to ground disables the converter
and three states the PWM outputs. See Figure 10.
VID4 1
20 VCC
GND (Pin 9)
VID3 2
19 PGOOD
VID2 3
18 PWM4
Bias and reference ground. All signals are referenced to this
pin.
VID1 4
17 ISEN4
VID0 5
16 ISEN1
COMP 6
15 PWM1
FB 7
14 PWM2
FS/DIS 8
13 ISEN2
GND 9
12 ISEN3
VSEN 10
11 PWM3
VID4 (Pin 1), VID3 (Pin 2), VID2 (Pin 3), VID1 (Pin 4)
and VID0 (Pin 5)
VSEN (Pin 10)
Power good monitor input. Connect to the microprocessorCORE voltage.
PWM1 (Pin 15), PWM2 (Pin 14), PWM3 (Pin 11) and
PWM4 (Pin 18)
PWM outputs for each driven channel in use. Connect these
pins to the PWM input of an HIP6601/2/3 driver. For systems
which use 3 channels, connect PWM4 high. Two channel
systems connect PWM3 and PWM4 high.
Voltage Identification inputs from microprocessor. These
pins respond to TTL and 3.3V logic signals. The ISL6554
decodes VID bits to establish the output voltage. See
Table 1.
ISEN1 (Pin 16), ISEN2 (Pin 13), ISEN3 (Pin 12) and
ISEN4 (Pin 17)
COMP (Pin 6)
PGOOD (Pin 19)
Output of the internal error amplifier. Connect this pin to the
external feedback and compensation network.
Power good. This pin provides a logic-high signal when the
microprocessor CORE voltage is within specified limits and
soft-start has timed out.
FB (Pin 7)
Inverting input of the internal error amplifier.
Current sense inputs from the individual converter channel’s
phase nodes. Unused sense lines MUST be left open.
VCC (Pin 20)
Bias supply. Connect this pin to a 5V supply.
FS/DIS (Pin 8)
Channel frequency, FSW, select and disable. A resistor from
this pin to ground sets the switching frequency of the
3
FN9003.3
February 11, 2005
ISL6554
Typical Application - 2 Phase Converter Using HIP6601 Gate Drivers
+12V
BOOT
VIN = +5V
PVCC
UGATE
+5V
VCC
PWM
FB
PHASE
DRIVER
HIP6601
COMP
LGATE
GND
VCC
VSEN
+VCORE
PWM4
PGOOD
+12V
PWM3
VID4
PWM2
VID3
PWM1
BOOT
PVCC
UGATE
MAIN
CONTROL
ISL6554
VID1
VID2
PHASE
VCC
VID0
FS/DIS
VIN = +5V
ISEN4
NC
ISEN3
NC
PWM
DRIVER
HIP6601
LGATE
GND
ISEN2
ISEN1
GND
4
FN9003.3
February 11, 2005
ISL6554
Typical Application - 4 Phase Converter Using HIP6602 Gate Drivers
VIN = +12V
BOOT1
+12V
UGATE1
L01
VCC
PHASE1
LGATE1
+5V
DUAL
DRIVER
HIP6602
FB
PVCC
BOOT2
COMP
+5V
VIN +12V
VCC
VSEN
UGATE2
L02
ISEN1
PGOOD
PWM1
VID4
PWM2
VID3
ISEN2
PHASE2
PWM1
PWM2
LGATE2
MAIN
CONTROL
ISL6554
VID1
VID2
GND
+VCORE
VID0
ISEN3
FS/DIS
PWM3
PWM4
GND
+12V
VIN+12V
BOOT3
ISEN4
UGATE3
L03
VCC
PHASE3
LGATE3
DUAL
DRIVER
HIP6602
PVCC
BOOT4
UGATE4
+5V
VIN +12V
L04
PHASE4
PWM3
PWM4
LGATE4
GND
5
FN9003.3
February 11, 2005
ISL6554
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V
Input, Output, or I/O Voltage . . . . . . . . . . GND -0.3V to VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5KV
Thermal Resistance (Typical, Note 1)
JA (°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Recommended Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V 5%
Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Operating Conditions: VCC = 5V, TA = 0°C to 70°C, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
10
15
mA
VCC Rising Threshold
4.25
4.38
4.5
V
VCC Falling Threshold
3.75
3.88
4.00
V
Reference Voltage Accuracy
-1
-
1
%
DAC Pin Input Low Voltage Threshold
-
-
0.8
V
INPUT SUPPLY POWER
RT = 100k
Input Supply Current
POWER-ON RESET (POR)
REFERENCE AND DAC
DAC Pin Input High Voltage Threshold
VID Pull-Up
VIDx = 0V or VIDx = 3V
2.0
-
-
V
10
20
40
A
OSCILLATOR
Frequency, FSW
RT = 100k, 1%
224
280
336
kHz
Adjustment Range (GBD) (Note 2)
(See Figure 10)
0.05
-
1.5
MHz
ERROR AMPLIFIER
DC Gain (GBD) (Note 2)
RL = 10K to GND
-
72
-
dB
Gain-Bandwidth Product (GBD) (Note 2)
CL = 100pF, RL = 10K to GND
-
18
-
MHz
Slew Rate
CL = 100pF, RL = 10K to GND
-
5.3
-
V/s
Maximum Output Voltage
RL = 10K to GND
3.6
4.1
-
V
Minimum Output Voltage
RL = 10K to GND
-
0.16
0.5
V
ISEN
Full Scale Input Current (GBD) (Note 2)
-
50
-
A
Overcurrent Trip Level
-
82.5
-
A
POWER GOOD
Upper Threshold
VSEN Rising
0.95
0.97
0.99
VDAC
Lower Threshold
VSEN Falling
0.89
0.91
0.93
VDAC
PGOOD Low Output Voltage
IPGOOD = 4mA
-
0.18
0.4
V
1.12
1.15
1.2
VDAC
-
2
-
%
PROTECTION
Overvoltage Threshold
VSEN Rising
Percent Overvoltage Hysteresis (GNT) (Note 3) VSEN Falling after Overvoltage
NOTES:
2. GBD = Guaranteed by design.
3. GNT = Guaranteed not tested.
6
FN9003.3
February 11, 2005
ISL6554
RIN
FB
VIN
ISL6554
ERROR
AMPLIFIER
COMPARATOR
CORRECTION
-
+
+
-
PWM
CIRCUIT
+

Q1
L1
PWM1
HIP6601
IL1
-
Q2
PHASE
PROGRAMMABLE
REFERENCE
DAC

+
CURRENT
RISEN1
ISEN1
SENSING
I AVERAGE
CURRENT
AVERAGING
VCORE
+

CURRENT
ISEN2
COUT
RISEN2
RLOAD
SENSING
VIN
PHASE
+
-

CORRECTION
COMPARATOR
+
-
Q3
PWM
CIRCUIT
L2
PWM2
HIP6601
IL2
Q4
FIGURE 1. SIMPLIFIED BLOCK DIAGRAM OF THE ISL6554 VOLTAGE AND CURRENT CONTROL LOOPS FOR A TWO POWER
CHANNEL REGULATOR
Operation
Figure 1 shows a simplified diagram of the voltage regulation
and current control loops. Both voltage and current feedback
are used to precisely regulate voltage and tightly control
output currents, IL1 and IL2 , of the two power channels. The
voltage loop comprises the error amplifier, comparators, gate
drivers and output MOSFETs. The error amplifier is
essentially connected as a voltage follower that has as an
input, the programmable reference DAC and an output that
is the CORE voltage.
Voltage Loop
Feedback from the CORE voltage is applied via resistor RIN
to the inverting input of the error amplifier. This signal can
drive the error amplifier output either high or low, depending
upon the CORE voltage. Low CORE voltage makes the
amplifier output move towards a higher output voltage level.
Amplifier output voltage is applied to the positive inputs of
the comparators via the correction summing networks.
Out-of-phase sawtooth signals are applied to the two
comparators inverting inputs. Increasing error amplifier
voltage results in increased comparator output duty cycle.
This increased duty cycle signal is passed through the PWM
7
circuit with no phase reversal and on to the HIP6601, again
with no phase reversal for gate drive to the upper MOSFETs,
Q1 and Q3. Increased duty cycle or ON time for the
MOSFET transistors results in increased output voltage to
compensate for the low output voltage sensed.
Current Loop
The current control loop works in a similar fashion to the
voltage control loop, but with current control information
applied individually to each channel’s comparator. The
information used for this control is the voltage that is
developed across rDS(ON) of each lower MOSFET, Q2 and
Q4, when they are conducting. A single resistor converts and
scales the voltage across the MOSFETs to a current that is
applied to the current sensing circuit within the ISL6554.
Output from these sensing circuits is applied to the current
averaging circuit. Each PWM channel receives the
difference current signal from the summing circuit that
compares the average sensed current to the individual
channel current. When a power channel’s current is greater
than the average current, the signal applied via the summing
correction circuit to the comparator, reduces the output pulse
width of the comparator to compensate for the detected
“above average” current in that channel.
FN9003.3
February 11, 2005
ISL6554
Applications and Converter Start-Up
Each PWM power channel’s current is regulated. This
enables the PWM channels to accurately share the load
current for enhanced reliability. The HIP6601, HIP6602 or
HIP6603 MOSFET driver interfaces with the ISL6554. For
more information, see the HIP6601, HIP6602 or HIP6603
data sheets [1], [2].
The ISL6554 is capable of controlling up to 4 PWM power
channels. Connecting unused PWM outputs to VCC
automatically sets the number of channels. The phase
relationship between the channels is 360 degrees/number of
active PWM channels. For example, for three channel
operation, the PWM outputs are separated by 120 degrees.
Figure 2 shows the PWM output signals for a four channel
system.
PWM 1
PWM 2
PWM 3
PWM 4
FIGURE 2. FOUR PHASE PWM OUTPUT AT 500kHz
Power supply ripple frequency is determined by the channel
frequency, FSW, multiplied by the number of active
channels. For example, if the channel frequency is set to
250kHz and there are three phases, the ripple frequency is
750kHz.
The IC monitors and precisely regulates the CORE voltage
of a microprocessor. After initial start-up, the controller also
provides protection for the load and the power supply. The
following section discusses these features.
Initialization
The ISL6554 usually operates from an ATX power supply.
Many functions are initiated by the rising supply voltage to
the VCC pin of the ISL6554. Oscillator, sawtooth generator,
soft-start and other functions are initialized during this
interval. These circuits are controlled by POR, Power-On
Reset. During this interval, the PWM outputs are driven to a
three state condition that makes these outputs essentially
open. This state results in no gate drive to the output
MOSFETs.
8
Once the VCC voltage reaches 4.375V (125mV), a voltage
level to insure proper internal function, the PWM outputs are
enabled and the soft-start sequence is initiated. If for any
reason, the VCC voltage drops below 3.875V (125mV). The
POR circuit shuts the converter down and again three states
the PWM outputs.
Soft-Start
After the POR function is completed with VCC reaching
4.375V, the soft-start sequence is initiated. soft-start, by its
slow rise in CORE voltage from zero, avoids an overcurrent
condition by slowly charging the discharged output
capacitors. This voltage rise is initiated by an internal DAC
that slowly raises the reference voltage to the error amplifier
input. The voltage rise is controlled by the oscillator
frequency and the DAC within the ISL6554, therefore; the
output voltage is effectively regulated as it rises to the final
programmed CORE voltage value.
For the first 32 PWM switching cycles, the DAC output
remains inhibited and the PWM outputs remain three stated.
From the 33rd cycle and for another, approximately 150
cycles, the PWM output remains low, clamping the lower
output MOSFETs to ground (see Figure 3). The time
variability is due to the error amplifier, sawtooth generator
and comparators moving into their active regions. After this
short interval, the PWM outputs are enabled and increment
the PWM pulse width from zero duty cycle to operational
pulse width, thus allowing the output voltage to slowly reach
the CORE voltage. The CORE voltage will reach its
programmed value before the 2048 cycles, but the PGOOD
output will not be initiated until the 2048th PWM switching
cycle.
The soft-start time or delay time, DT = 2048/FSW. For an
oscillator frequency, FSW, of 200kHz, the first 32 cycles or
160s, the PWM outputs are held in a three state level as
explained above. After this period and a short interval
described above, the PWM outputs are initiated and the
voltage rises in 10.08ms, for a total delay time DT of 10.24ms.
Figure 3 shows the start-up sequence as initiated by a fast
rising 5V supply, VCC, applied to the ISL6554. Note the
short rise to the three state level in PWM 1 output during first
32 PWM cycles.
Figure 4 shows the waveforms when the regulator is
operating at 200kHz. Note that the soft-start duration is a
function of the channel frequency as explained previously.
Also note the pulses on the COMP terminal. These pulses
are the current correction signal feeding into the comparator
input (see the Block Diagram).
Figure 5 shows the regulator operating from an ATX supply.
In this figure, note the slight rise in PGOOD as the 5V supply
rises. The PGOOD output stage is made up of NMOS and
PMOS transistors. On the rising VCC, the PMOS device
becomes active slightly before the NMOS transistor pulls
“down”, generating the slight rise in the PGOOD voltage.
FN9003.3
February 11, 2005
ISL6554
PWM 1
OUTPUT
DELAY TIME
PGOOD
Note that Figure 5 shows the 12V gate driver voltage
available before the 5V supply to the ISL6554 has reached
its threshold level. If conditions were reversed and the 5V
supply was to rise first, the start-up sequence would be
different. In this case the ISL6554 will sense an overcurrent
condition due to charging the output capacitors. The supply
will then restart and go through the normal soft-start cycle.
Fault Protection
VCORE
5V
VCC
The ISL6554 protects the microprocessor and the entire
power system from damaging stress levels. Within the
ISL6554 both Overvoltage and Overcurrent circuits are
incorporated to protect the load and regulator.
Overvoltage
VIN = 12V
FIGURE 3. START-UP OF 4 PHASE SYSTEM OPERATING AT
500kHz
V COMP
DELAY TIME
PGOOD
VCORE
5V
VCC
VIN = 12V
FIGURE 4. START-UP OF 4 PHASE SYSTEM OPERATING AT
200kHz
12V ATX
SUPPLY
The VSEN pin is connected to the microprocessor CORE
voltage. A CORE overvoltage condition is detected when the
VSEN pin goes more than 15% above the programmed VID
level.
The overvoltage condition is latched, disabling normal PWM
operation, and causing PGOOD to go low. The latch can
only be reset by lowering and returning VCC high to initiate a
POR and soft-start sequence.
During a latched overvoltage, the PWM outputs will be driven
either low or three state, depending upon the VSEN input.
PWM outputs are driven low when the VSEN pin detects that
the CORE voltage is 15% above the programmed VID level.
This condition drives the PWM outputs low, resulting in the
lower or synchronous rectifier MOSFETs to conduct and shunt
the CORE voltage to ground to protect the load.
If after this event, the CORE voltage falls below the overvoltage limit (plus some hysteresis), the PWM outputs will
three state. The HIP6601 family drivers pass the three-state
information along, and shuts off both upper and lower
MOSFETs. This prevents “dumping” of the output capacitors
back through the lower MOSFETs, avoiding a possibly
destructive ringing of the capacitors and output inductors. If
the conditions that caused the overvoltage still persist, the
PWM outputs will be cycled between three state and VCORE
clamped to ground, as a hysteretic shunt regulator.
Undervoltage
PGOOD
VCORE
The VSEN pin also detects when the CORE voltage falls
more than 9% below the VID programmed level. This causes
PGOOD to go low, but has no other effect on operation and
is not latched. There is also hysteresis in this detection point.
Overcurrent
5 V ATX
SUPPLY
VIN = 5V, CORE LOAD CURRENT = 31A
FREQUENCY 200kHz
ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”
FIGURE 5. SUPPLY POWERED BY ATX SUPPLY
9
In the event of an overcurrent condition, the overcurrent
protection circuit reduces the RMS current delivered to 41%
of the current limit. When an overcurrent condition is
detected, the controller forces all PWM outputs into a three
state mode. This condition results in the gate driver
removing drive to the output stages. The ISL6554 goes into
a wait delay timing cycle that is equal to the soft-start ramp
FN9003.3
February 11, 2005
ISL6554
time. PGOOD also goes “low” during this time due to VSEN
going below its threshold voltage. To lower the average
output dissipation, the soft-start initial wait time is increased
from 32 to 2048 cycles, then the soft-start ramp is initiated.
At a PWM frequency of 200kHz, for instance, an overcurrent
detection would cause a dead time of 10.24ms, then a ramp
of 10.08ms.
At the end of the delay, PWM outputs are restarted and the
soft-start ramp is initiated. If a short is present at that time,
the cycle is repeated. This is the hiccup mode.
Figure 6 shows the supply shorted under operation and the
hiccup operating mode described above. Note that due to
the high short circuit current, overcurrent is detected before
completion of the start-up sequence so the delay is not quite
as long as the normal soft-start cycle.
SHORT APPLIED HERE
PGOOD
TABLE 1. VOLTAGE IDENTIFICATION CODES (Continued)
VOLTAGE IDENTIFICATION CODE AT
PROCESSOR PINS
VID4
VID3
VID2
VID1
VID0
VCCCORE
(VDC)
1
0
1
1
0
1.150
1
0
1
0
1
1.175
1
0
1
0
0
1.200
1
0
0
1
1
1.225
1
0
0
1
0
1.250
1
0
0
0
1
1.275
1
0
0
0
0
1.300
0
1
1
1
1
1.325
0
1
1
1
0
1.350
0
1
1
0
1
1.375
0
1
1
0
0
1.400
0
1
0
1
1
1.425
0
1
0
1
0
1.450
0
1
0
0
1
1.475
0
1
0
0
0
1.500
0
0
1
1
1
1.525
SHORT
0
0
1
1
0
1.550
CURRENT
0
0
1
0
1
1.575
50A/DIV.
0
0
1
0
0
1.600
0
0
0
1
1
1.625
0
0
0
1
0
1.650
0
0
0
0
1
1.675
0
0
0
0
0
1.700
HICCUP MODE. SUPPLY POWERED BY ATX SUPPLY
CORE LOAD CURRENT = 31A, 5V LOAD = 5A
SUPPLY FREQUENCY = 200kHz, V IN = 12V
ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”
FIGURE 6. SHORT APPLIED TO SUPPLY AFTER POWER-UP
Current Sensing and Balancing
Overview
CORE Voltage Programming
The voltage identification pins (VID0, VID1,VID2,VID3 and
VID4) set the CORE output voltage. Each VID pin is pulled to
VCC by an internal 20A current source and accepts opencollector/open-drain/open-switch-to-ground or standard lowvoltage TTL or CMOS signals.
Table 1 shows the nominal DAC voltage as a function of the
VID codes. The power supply system is 1% accurate over
the operating temperature and voltage range.
TABLE 1. VOLTAGE IDENTIFICATION CODES
VOLTAGE IDENTIFICATION CODE AT
PROCESSOR PINS
The ISL6554 samples the on-state voltage drop across each
synchronous rectifier MOSFET, Q2, as an indication of the
inductor current in that phase (see Figure 7). Neglecting AC
effects (to be discussed later), the voltage drop across Q2 is
simply rDS(ON)(Q2) x inductor current (IL). Note that IL, the
inductor current, is either 1/2, 1/3, or 1/4 of the total current
(ILT), depending on how many phases are in use.
The voltage at Q2’s drain, the PHASE node, is applied to the
RISEN resistor to develop the IISEN current to the ISL6554
ISEN pin. This pin is held at virtual ground, so the current
through RISEN is IL x rDS(ON)(Q2) / RISEN.
The IISEN current provides information to perform the
following functions:
VID4
VID3
VID2
VID1
VID0
VCCCORE
(VDC)
1
1
1
1
1
Output Off
1
1
1
1
0
0.95
1
1
1
0
1
0.975
1
1
1
0
0
1.000
Overcurrent, Selecting RISEN
1
1
0
1
1
1.025
1
1
0
1
0
1.050
1
1
0
0
1
1.075
1
1
0
0
0
1.100
1
0
1
1
1
1.125
The current detected through the RISEN resistor is
averaged with the current(s) detected in the other 1, 2, or 3
channels. The averaged current is compared with a
trimmed, internally generated current, and used to detect
an overcurrent condition.
10
1. Detection of an overcurrent condition
2. Balance the IL currents in multiple channels
FN9003.3
February 11, 2005
ISL6554
RFB
Cc
RIN
COMP
ISL6554
ERROR
AMPLIFIER
GENERATOR
-
+
CORRECTION
+
-
VIN
COMPARATOR
HIP6601
PWM
IL
+
Q2
DIFFERENCE
+
REFERENCE
DAC
L01
Q1
PWM
CIRCUIT
CURRENT
VCORE
RLOAD
SAWTOOTH
COUT
FB
PHASE
RISEN
ISEN
SENSING
TO OTHER
CHANNELS
TO OVER
CURRENT
TRIP
-
COMPARATOR
AVERAGING
+
-
CURRENT
SENSING
FROM
OTHER
CHANNELS
ONLY ONE OUTPUT
STAGE SHOWN
INDUCTOR
CURRENT(S)
FROM
OTHER
CHANNELS
REFERENCE
FIGURE 7. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM SHOWING CURRENT AND VOLTAGE SAMPLING
The nominal current through the RISEN resistor should be
50A at full output load current, and the nominal trip point for
overcurrent detection is 165% of that value, or 82.5A.
Therefore, RISEN = IL x rDS(ON) (Q2) / 50A.
For a full load of 25A per phase, and an rDS(ON) (Q2) of
4m, RISEN = 2k.
The overcurrent trip point would be 165% of 25A, or ~ 41A
per phase. The RISEN value can be adjusted to change the
overcurrent trip point, but it is suggested to stay within 25%
of nominal.
values of the input and output voltage. Ignoring secondary
effects, such as series resistance, the peak to peak value of
the sawtooth current can be described by:
iPK-PK = (VIN x VCORE - VCORE2) / (L x FSW x VIN)
Where: VCORE = DC value of the output or VID voltage
VIN= DC value of the input or supply voltage
L= value of the inductor
FSW= switching frequency
Example: For VCORE= 1.6V,
VIN= 12V,
L= 1.3H,
Current Balancing
The detected currents are also used to balance the phase
currents.
FSW= 250kHz,
Then iPK-PK = 4.3A
Each phase’s current is compared to the average of all
phase currents, and the difference is used to create an offset
in that phase’s PWM comparator. The offset is in a direction
to reduce the imbalance.
Figures 8 and 9 show the inductor current of a two phase
system without and with current balancing.
The inductor, or load current, flows alternately from VIN
through Q1 and from ground through Q2. The ISL6554
samples the on-state voltage drop across each Q2 transistor
to indicate the inductor current in that phase. The voltage
drop is sampled 1/3 of a switching period, i/FSW, after Q1 is
turned OFF and Q2 is turned on. Because of the sawtooth
current component, the sampled current is different from the
average current per phase. Neglecting secondary effects,
the sampled current (ISAMPLE) can be related to the load
current (ILT) by:
Inductor Current
ISAMPLE = ILT / n + (VINVCORE -3VCORE2) / (6L x FSW x VIN)
The balancing circuit can not make up for a difference in
rDS(ON) between synchronous rectifiers. If a FET has a higher
rDS(ON), the current through that phase will be reduced.
The inductor current in each phase of a multi-phase Buck
converter has two components. There is a current equal to
the load current divided by the number of phases (ILT / n),
and a sawtooth current, (iPK-PK) resulting from switching.
The sawtooth component is dependent on the size of the
inductors, the switching frequency of each phase, and the
11
Where:
ILT = total load current
n = the number of channels
Example: Using the previously given conditions, and
For
ILT = 100A,
n=4
Then ISAMPLE
= 25.49A
FN9003.3
February 11, 2005
ISL6554
AMPERES
resistor RT. To avoid pickup by the FS/DIS pin, it is important
to place this resistor next to the pin.
25
Layout Considerations
20
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting impedances
and parasitic circuit elements. These voltage spikes can
degrade efficiency, radiate noise into the circuit and lead to
device overvoltage stress. Careful component layout and
printed circuit design minimizes the voltage spikes in the
converter. Consider, as an example, the turnoff transition of
the upper PWM MOSFET. Prior to turnoff, the upper MOSFET
was carrying channel current. During the turnoff, current stops
flowing in the upper MOSFET and is picked up by the lower
MOSFET. Any inductance in the switched current path
generates a large voltage spike during the switching interval.
Careful component selection, tight layout of the critical
components, and short, wide circuit traces minimize the
magnitude of voltage spikes. Contact Intersil for evaluation
board drawings of the component placement and printed
circuit board.
15
10
5
0
FIGURE 8. TWO CHANNEL MULTI-PHASE SYSTEM WITH
CURRENT BALANCING DISABLED
25
AMPERES
20
There are two sets of critical components in a DC-DC
converter using a ISL6554 controller and a HIP6601 gate
driver. The power components are the most critical because
they switch large amounts of energy. Next are small signal
components that connect to sensitive nodes or supply critical
bypassing current and signal coupling.
15
10
5
0
FIGURE 9. TWO CHANNEL MULTI-PHASE SYSTEM WITH
CURRENT BALANCING ENABLED
As discussed previously, the voltage drop across each Q2
transistor at the point in time when current is sampled is rDSON
(Q2) x ISAMPLE. The voltage at Q2’s drain, the PHASE node,
is applied through the RISEN resistor to the ISL6554 ISEN pin.
This pin is held at virtual ground, so the current into ISEN is:
ISENSE
= ISAMPLE x rDS(ON) (Q2) / RISEN.
RIsen
= ISAMPLE x rDS(ON) (Q2) / 50A
Example: From the previous conditions,
where ILT
= 100A,
ISAMPLE
= 25.49A,
rDS(ON) (Q2)
= 4m
Then: RISEN
= 2.04K and
ICURRENT TRIP
= 165%
Short circuit ILT
= 165A.
Channel Frequency Oscillator
The channel oscillator frequency is set by placing a resistor,
RT, to ground from the FS/DIS pin. Figure 10 is a curve
showing the relationship between frequency, FSW, and
12
The power components should be placed first. Locate the
input capacitors close to the power switches. Minimize the
length of the connections between the input capacitors, CIN ,
and the power switches. Locate the output inductors and
output capacitors between the MOSFETs and the load.
Locate the gate driver close to the MOSFETs.
The critical small components include the bypass capacitors for
VCC and PVCC on the gate driver ICs. Locate the bypass
capacitor, CBP, for the ISL6554 controller close to the device. It
is especially important to locate the resistors associated with
the input to the amplifiers close to their respective pins, since
they represent the input to feedback amplifiers. Resistor RT,
that sets the oscillator frequency should also be located next to
the associated pin. It is especially important to place the RSEN
resistors at the respective terminals of the ISL6554.
A multi-layer printed circuit board is recommended. Figure 11
shows the connections of the critical components for one
output channel of the converter. Note that capacitors CIN and
COUT could each represent numerous physical capacitors.
Dedicate one solid layer, usually the middle layer of the PC
board, for a ground plane and make all critical component
ground connections with vias to this layer. Dedicate another
solid layer as a power plane and break this plane into smaller
islands of common voltage levels. Keep the metal runs from
the PHASE terminal to output inductor short. The power plane
should support the input power and output power nodes. Use
FN9003.3
February 11, 2005
ISL6554
copper filled polygons on the top and bottom circuit layers for
the phase nodes. Use the remaining printed circuit layers for
small signal wiring. The wiring traces from the driver IC to the
MOSFET gate and source should be sized to carry at least
one ampere of current.
1,000
500
200
Output Inductor Selection
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Small inductors in a multi-phase converter reduces
the response time without significant increases in total ripple
current.
100
50
20
The output inductor of each power channel controls the
ripple current. The control IC is stable for channel ripple
current (peak-to-peak) up to twice the average current. A
single channel’s ripple current is approximately:
10
5
2
20
50
100 200
500 1,000 2,000 5,000 10,000
CHANNEL OSCILLATOR FREQUENCY, FSW (kHz)
FIGURE 10. RESISTANCE RT vs FREQUENCY
Component Selection Guidelines
Output Capacitor Selection
The output capacitor is selected to meet both the dynamic
load requirements and the voltage ripple requirements. The
load transient for the microprocessor CORE is characterized
by high slew rate (di/dt) current demands. In general,
multiple high quality capacitors of different size and dielectric
are paralleled to meet the design constraints.
Modern microprocessors produce severe transient load rates.
High frequency capacitors supply the initially transient current
and slow the load rate-of-change seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and voltage rating
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR determines the output ripple voltage
and the initial voltage drop following a high slew-rate
transient’s edge. In most cases, multiple capacitors of small
case size perform better than a single large case capacitor.
13
The current from multiple channels tend to cancel each other
and reduce the total ripple current. Figure 12 gives the total
ripple current as a function of duty cycle, normalized to the
parameter  Vo    LxF SW  at zero duty cycle. To determine
the total ripple current from the number of channels and the
duty cycle, multiply the y-axis value by  Vo    LxF SW  .
Small values of output inductance can cause excessive
power dissipation. The ISL6554 is designed for stable
operation for ripple currents up to twice the load current.
However, for this condition, the RMS current is 115% above
the value shown in the following MOSFET Selection and
Considerations section. With all else fixed, decreasing the
inductance could increase the power dissipated in the
MOSFETs by 30%.
1.0
SINGLE
CHANNEL
0.8
VO / (LX FSW)
1
10
V IN – V OUT V OUT
I = --------------------------------  ---------------F SW  L
V IN
RIPPLE CURRENT (APEAK-PEAK)
RT (k)
Bulk capacitor choices include aluminum electrolytic, OSCon, Tantalum and even ceramic dielectrics. An aluminum
electrolytic capacitor’s ESR value is related to the case size
with lower ESR available in larger case sizes. However, the
equivalent series inductance (ESL) of these capacitors
increases with case size and can reduce the usefulness of
the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Consult the
capacitor manufacturer and measure the capacitor’s
impedance with frequency to select a suitable component.
0.6
2 CHANNEL
0.4
3 CHANNEL
0.2
4 CHANNEL
0
0
0.1
0.2
0.3
0.4
0.5
DUTY CYCLE (VO/VIN)
FIGURE 11. RIPPLE CURRENT vs DUTY CYCLE
FN9003.3
February 11, 2005
ISL6554
+5VIN
USE INDIVIDUAL METAL RUNS
FOR EACH CHANNEL TO HELP
ISOLATE OUTPUT STAGES
+12V
CBP
VCC PVCC
LOCATE NEXT TO IC PIN(S)
CBOOT
VCC
CBP
PWM
ISL6554
RFB
LOCATE NEXT
TO FB PIN
LOCATE NEAR TRANSISTOR
LO1
HIP6601
VCORE
PHASE
COMP FS/DIS
CT
CIN
COUT
RT
FB
LOCATE NEXT TO IC PIN
RSEN
RIN
VSEN
ISEN
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 12. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
Input Capacitor Selection
The important parameters for the bulk input capacitors are the
voltage rating and the RMS current rating. For reliable
operation, select bulk input capacitors with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum input
voltage and a voltage rating of 1.5 times is a conservative
guideline. The RMS current required for a multi-phase
converter can be approximated with the aid of Figure 13.
CURRENT MULTIPLIER
0.5
SINGLE
CHANNEL
0.4
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use ceramic capacitance for
the high frequency decoupling and bulk capacitors to supply
the RMS current. Small ceramic capacitors should be placed
very close to the drain of the upper MOSFET to suppress the
voltage induced in the parasitic circuit impedances.
For bulk capacitance, several electrolytic capacitors (Panasonic
HFQ series or Nichicon PL series or Sanyo MV-GX or
equivalent) may be needed. For surface mount designs, solid
tantalum capacitors can be used, but caution must be
exercised with regard to the capacitor surge current rating.
These capacitors must be capable of handling the surgecurrent at power-up. The TPS series available from AVX, and
the 593D series from Sprague are both surge current tested.
MOSFET Selection and Considerations
0.3
2 CHANNEL
0.2
3 CHANNEL
0.1
0
4 CHANNEL
0
0.1
0.2
0.3
0.4
0.5
DUTY CYCLE (VO/VIN)
FIGURE 13. CURRENT MULTIPLIER vs DUTY CYCLE
First determine the operating duty ratio as the ratio of the
output voltage divided by the input voltage. Find the Current
Multiplier from the curve with the appropriate power
channels. Multiply the current multiplier by the full load
output current. The resulting value is the RMS current rating
required by the input capacitor.
14
In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes two
loss components; conduction loss and switching loss. These
losses are distributed between the upper and lower
MOSFETs according to duty factor (see the following
equations). The conduction losses are the main component
of power dissipation for the lower MOSFETs, Q2 and Q4 of
Figure 1. Only the upper MOSFETs, Q1 and Q3 have
significant switching losses, since the lower device turns on
and off into near zero voltage.
The equations assume linear voltage-current transitions and
do not model power loss due to the reverse-recovery of the
lower MOSFETs body diode. The gate-charge losses are
dissipated by the Driver IC and don’t heat the MOSFETs.
However, large gate-charge increases the switching time,
FN9003.3
February 11, 2005
ISL6554
tSW which increases the upper MOSFET switching losses.
Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
thermal-resistance specifications. A separate heatsink may
be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
References
Intersil documents are available on the web at
www.intersil.com/
[1] HIP6601/HIP6603 Data Sheet, Intersil Corporation,
File No. 4819
[2] HIP6602 Data Sheet, Intersil Corporation, File No. 4838
2
I O  r DS  ON   V OUT I O  V IN  t SW  F SW
P UPPER = ------------------------------------------------------------ + ---------------------------------------------------------V IN
2
2
I O  r DS  ON    V IN – V OUT 
P LOWER = --------------------------------------------------------------------------------V IN
A diode, anode to ground, may be placed across Q2 and Q4
of Figure 1. These diodes function as a clamp that catches
the negative inductor swing during the dead time between
the turn off of the lower MOSFETs and the turn on of the
upper MOSFETs. The diodes must be a Schottky type to
prevent the lossy parasitic MOSFET body diode from
conducting. It is usually acceptable to omit the diodes and let
the body diodes of the lower MOSFETs clamp the negative
inductor swing, but efficiency could drop one or two percent
as a result. The diode’s rated reverse breakdown voltage
must be greater than the maximum input voltage.
15
FN9003.3
February 11, 2005
ISL6554
Small Outline Plastic Packages (SOIC)
M20.3 (JEDEC MS-013-AC ISSUE C)
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
INCHES
H
0.25(0.010) M
B M
E
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.014
0.019
0.35
0.49
9
C
0.0091
0.0125
0.23
0.32
-
D
0.4961
0.5118
12.60
13.00
3
E
0.2914
0.2992
7.40
7.60
4
e
-C-
e
µ
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
MILLIMETERS
0.050 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N

20
0o
20
8o
0o
7
8o
Rev. 1 1/02
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
16
FN9003.3
February 11, 2005
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