DATASHEET

DPDT CMOS Analog Switch
HI-5046A/883
Features
This CMOS analog switch offers low-resistance switching
performance for analog voltages up to the supply rails and for
signal currents up to 70mA. “ON” resistance is low and stays
reasonably constant over the full range of operating signal
voltage and current. RON remains exceptionally constant for
input voltages between +5V and -5V and currents up to 50mA.
Switch impedance also changes very little over temperature,
particularly between 0°C and +75°C. RON is nominally 25Ω
for the HI-5046A/883.
• This Circuit is Processed in Accordance to MIL-STD-883 and
is Fully Conformant Under the Provisions of Paragraph 1.2.1.
This device provides break-before-make switching and is TTL
and CMOS compatible for maximum application versatility.
Performance is further enhanced by Dielectric Isolation
processing which insures latch-free operation with very low
input and output leakage currents (0.8nA at +25°C). The
HI-5046A/883 also features very low power operation (1.5mW
at +25°C). The HI-5046A/883 is available in a 16 Ld CerDIP
package and is specified over the temperature range of -55°C
to +125°C.
• Wide Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . ±15V
• Low “On” Resistance . . . . . . . . . . . . . . 25Ω (Typ), 50Ω (Max)
• High Current Capability . . . . . . . . . . . . . . . . . . . . . 70mA (Max)
• Break-Before-Make Switching
- Turn-On Time. . . . . . . . . . . . . . . . . 370ns (Typ), 800ns (Max)
- Turn-Off Time . . . . . . . . . . . . . . . .280ns (Typ), 400ns (Max)
• No Latch Up
• Input MOS Gates are Protected from Electrostatic Discharge
• DTL, TTL, CMOS, PMOS Compatible
Applications
• High Frequency Analog
• Sample and Hold
• Digital Filters
• Operational Amplifier Gain Switching
Functional Diagram
Pin Configuration
LOGIC “1” INPUT
HI1-5046/883
(16 LD CERDIP)
TOP VIEW
VL
LOGIC “0” INPUT
S1
S2
2
16 S2
15 A
S3
D1 3
14 V-
A
S1 4
13 VR
S4 5
D4 6
12 VL
11 V+
D2 1
V+
12
S4
11
4
3
16
1
9
8
5
6
D1
D2
D3
D4
15
13
VR
14
V-
10
7
9 S3
D3 8
TYPICAL SWITCH
S
NOTE: Unused pins may be internally connected. Ground all unused pins.
Ordering Information
PART NUMBER
PART
MARKING
TEMP. RANGE
(°C)
A
PACKAGE
PKG.
DWG. #
N
P
D
HI1-5046A/883 HI1-5046A/883 -55 to +125 16 Ld CerDIP F16.3
NOTE: Source and Drain are arbitrarily depicted as Analog Input and
Output, respectively. They may be interchanged without affecting
performance.
May 3, 2012
FN8274.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 1989, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
HI-5046A/883
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V
±VSUPPLY to Ground (V+, V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18V
VR to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VSUPPLY
VL to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY
Digital and Analog Input Voltage (VA, VS, VD) . . . . . . . . . . . . +VSUPPLY +4V
-VSUPPLY -4V
Peak Current (Source to Drain)
(Pulse at 1ms, 10% Duty Cycle Max) . . . . . . . . . . . . . . . . . . . . . . . . 70mA
Continuous Current Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<2000V
Thermal Resistance
θJA (°C/W) θJC (°C/W)
CerDIP Package . . . . . . . . . . . . . . . . . . . . . .
82
20
Package Power Dissipation at +75°C
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Package Power Dissipation Derating Factor above +75°C
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.3mW/°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . . . . . . . .+300°C
Recommended Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Operating Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±15V
Logic Supply Voltage (VL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.0V
Logic Reference Voltage (VR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.0V
Analog Input Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VSUPPLY
Address Low Level (VAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 0.8V
Address High Level (VAH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V to +5.0V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
TABLE 1. D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Tested at: Supply Voltage = ±15V, VL = +5.0V, VR = 0.0V, VAH = 2.4V, VAL = +0.8V, unused pins are grounded, unless otherwise specified.
D.C. PARAMETERS
Switch “ON” Resistance
SYMBOL
RDS2
CONDITIONS
VD = -10V, IS = 10mA
S1/S2/S3/S4
VD = 10V, IS = -10mA
S1/S2/S3/S4
Source “OFF”
Leakage Current
IS(OFF)
VS = -10V, VD = 10V
S1/S2/S3/S4
VS = 10V, VD = -10V
S1/S2/S3/S4
Drain “OFF”
Leakage Current
ID(OFF)
VD = -10V, VS = 10V
S1/S2/S3/S4
VD = 10V, VS = -10V
S1/S2/S3/S4
Channel “ON”
Leakage Current
ID(ON)
VD = VS = 10V
S1/S2/S3/S4
VD = VS = -10V
S1/S2/S3/S4
Low Level Address Current
IAL
VA = 0V
High Level Address Current
IAH
VA = 2.4V, 5V
Positive Supply Current
+ICC
VA = 0V, 5V
Negative Supply Current
-ICC
2
VA = 0V, 5V
GROUP A
SUBGROUPS
TEMPERATURE
(°C)
MIN
MAX
UNITS
1
+25
-
45
Ω
2, 3
-55 to +125
-
50
Ω
1
+25
-
45
Ω
2, 3
-55 to +125
-
50
Ω
1
+25
-1
1
nA
2, 3
-55 to +125
-100
100
nA
1
+25
-1
1
nA
2, 3
-55 to +125
-100
100
nA
1
+25
-1
1
nA
2, 3
-55 to +125
-100
100
nA
1
+25
-1
1
nA
2, 3
-55 to +125
-100
100
nA
1
+25
-2
2
nA
2, 3
-55 to +125
-200
200
nA
1
+25
-2
2
nA
2, 3
-55 to +125
-200
200
nA
1
+25
-1
1
µA
2, 3
-55 to +125
-10
1
µA
1
+25
-1
1
µA
2, 3
-55 to +125
-1
10
µA
1
+25
-
200
µA
2, 3
-55 to +125
-
300
µA
1
+25
-200
-
µA
2, 3
-55 to +125
-300
-
µA
FN8274.0
May 3, 2012
HI-5046A/883
TABLE 1. D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Tested at: Supply Voltage = ±15V, VL = +5.0V, VR = 0.0V, VAH = 2.4V, VAL = +0.8V, unused pins are grounded, unless otherwise specified.
D.C. PARAMETERS
SYMBOL
Logic Supply Current
+IL
Reference Supply Current
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
(°C)
MIN
MAX
UNITS
1
+25
-
200
µA
2, 3
-55 to +125
-
300
µA
1
+25
-200
-
µA
2, 3
-55 to +125
-300
-
µA
VA = 0V, 5V
VA = 0V, 5V
+IR
TABLE 2. A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Tested at: Supply Voltage = ±15V, VL = +5.0V, VR = 0.0V, VAH = +5.0V, VAL = +0.0V, unused pins are grounded, unless otherwise specified.
PARAMETERS
SYMBOL
Turn “ON” Time
t(ON)
Turn “OFF” Time
t(OFF)
GROUP A
SUBGROUPS
TEMPERATURE
(°C)
MIN
MAX
UNITS
VS = 10V, -10V
CL = 10pF
RL = 1kΩ
11
-55
-
450
ns
9
+25
-
500
ns
10
+125
-
800
ns
VS = 10V, -10V
CL = 10pF
RL = 1kΩ
11
-55
-
350
ns
9
+25
-
450
ns
10
+125
-
600
ns
CONDITIONS
TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS (NOTE 1)
Device Characterized at: +VSUPPLY = +15V, −VSUPPLY = −15V, GND = 0V
PARAMETERS
SYMBOL
“ON” Resistance Match
(Channel to Channel)
NOTE
TEMPERATURE
(°C)
MIN
MAX
UNITS
rON2 Match
VD = ±10V
ID = 10mA
1
+25
-
10
Ω
CA
VA = 0V, 5V
1
+25
-
45
pF
Address Capacitance
CONDITIONS
Switch Input Capacitance
CS (OFF)
Switch Off: VA = 0V
1
+25
-
60
pF
Switch Output Capacitance
CD (OFF)
Switch Off: VA = 0V
1
+25
-
60
pF
CD (ON)
Switch On: VA = 5V
1
+25
-
60
pF
Drain to Source Capacitance
CDS (OFF)
Switch Off: VA = 0V
1
+25
-
10
pF
Off Isolation
VISO
VS = 2VP-P @ f = 100kHz,
RL = 100Ω
1
+25
1
60
dB
Crosstalk
VCT
VS = 2VP-P @ f = 100kHz,
RL = 100Ω
1
+25
1
60
dB
Charge Transfer Error
VCTE
VS = GND, CL = 0.01µF
VA = 0V to 4V @ f = 200kHz
1
+25
-
30
mV
NOTE:
1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab
characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from
multiple production runs which reflect lot to lot and within lot variation.
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS
Interim Electrical Parameters (Pre Burn-in)
Final Electrical Test Parameters
SUBGROUPS (Tables 1 and 2)
1
1 (Note 2), 2, 3, 9, 10, 11
Group A Test Requirements
1, 2, 3, 9, 10, 11
Groups C & D Endpoints
1
NOTE:
2. PDA applies to Subgroup 1 only.
3
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May 3, 2012
HI-5046A/883
Test Circuits
10mA
RON =
V2
V2
10mA
ID(OFF)
IS(OFF)
IN
OUT
A
±10V
IN
OUT
±10V
±10V
FIGURE 1. RDS
FIGURE 2. IS(OFF)
IN
OUT
ID(OFF)
IS(OFF)
A
A
IN
OUT
A
A
±10V
±10V
ID(ON)
±10V
FIGURE 3. ID(OFF)
FIGURE 4. ID(ON)
+VCC
+ICC
OUT
IN
VA
+VCC
IN
OUT
GND
VA
-ICC
IA
-VCC
-VCC
GND
FIGURE 5. ADDRESS CURRENTS
4
FIGURE 6. SUPPLY CURRENTS
FN8274.0
May 3, 2012
HI-5046A/883
Test Circuits
(Continued)
SWITCHED
CHANNEL
IN
VIN
OUT
50Ω
2VP-P
VOUT
VIN
2VP-P
RL
50Ω
VOUT
⎛ V IN ⎞
CROSSTALK = 20 Log ⎜ ----------------⎟
⎝ V OUT⎠
⎛ V IN ⎞
OFF ISOLATION = 20 Log ⎜ ----------------⎟
⎝ V OUT⎠
RL
RL
NOTE: Applies only to dual or double throw switches.
FIGURE 7. OFF ISOLATION
FIGURE 8. CROSSTALK
D
S
0.01MF
DRIVER
f = 200kHz
SQUARE WAVE
tR ≤ 20ns
TO MEASUREMENT
CIRCUITRY WITH INPUT
RESISTANCE OF 1MΩ
OR GREATER
IF PULSE TEST IS USED:
tR, tF ≤ 20ns
VIN (DRIVER)
VCTE
DROOP CAUSED BY
DEVICE LEAKAGE
AND MEASUREMENT
CIRCUITRY
SWITCHING TRANSIENT
NOTE: VCTE may be a positive or negative value.
FIGURE 9. CHARGE TRANSFER
Test Characteristics
VAH
VA
90%
90%
IN1
OUT 1
tON
+10V
90%
IN2
1k
VA
tOFF
90%
OUT 2
1k
tOFF
tON
FIGURE 10. ON/OFF SWITCH TIME (tON, tOFF)
5
FN8274.0
May 3, 2012
HI-5046A/883
Test Characteristics
(Continued)
720
720
660
660
600
600
540
540
480
480
420
420
tON
360
300
360
tON
300
tOFF
240
240
180
180
120
120
tOFF
60
60
2.4
3.0
3.6
4.2
4.8
0
0.5
DIGITAL “HIGH” (VAH)
1.0
1.5
DIGITAL “LOW” (VAL)
FIGURE 11. SWITCHING TIMES FOR DIGITAL TRANSITION
FIGURE 12. SWITCHING TIMES FOR NEGATIVE DIGITAL TRANSITION
Test Waveforms
5V
5V
INPUT
INPUT
OUTPUT
OUTPUT
5V
100ns
Vertical Scale: Input = 5V/Div, (TTL; VAH = 5V, VAL = 0V)
Output = 5V/Div
Horizontal Scale: 100ns/Div
FIGURE 13.
6
5V
100ns
Vertical Scale: Input = 5V/Div, (CMOS; VAH = 10V, VAL = 0V)
Output = 5V/Div
Horizontal Scale: 100ns/Div
FIGURE 14.
FN8274.0
May 3, 2012
HI-5046A/883
Burn-In Circuit
HI-5046A/883 CERAMIC DIP
R1
R2
R3
R4
1 D1
S1 16
2
A1 15
3 D3
V- 14
4 S3
VR 13
5 S4
VL 12
6 D4
V+ 11
7
A2 10
8 D2
S2 9
VA
C1
D1
C2
D2
C3
D3
V-
VL
V+
NOTES:
R1 thru R4 = 10kΩ, ±5%, 1/4W (Min)
C1, C2, C3 = 0.01µF/Socket (Min) or 0.1µF/Row, (Min)
D1, D2, D3 = 1N4002 or Equivalent/Board
VL = 5.5V ±0.5V
A2 = A2 = 5.5V ±0.5V
|(V+) - (V-)| = 30V
7
FN8274.0
May 3, 2012
HI-5046A/883
Schematic Diagrams
V+
R3
V+
VR
A1 (A2)
N1
TO (VR’)
V+
N3
IN
OUT
P2
N2
VP1
V-
A1 (A2)
NOTE: Connect V+ to VL for minimizing power consumption when driving
from CMOS circuits.
FIGURE 15. TTL/CMOS REFERENCE CIRCUIT
FIGURE 16. SWITCH CELL
V+
P3
P5
P1
V+
P4
N1
P6
D1
R4
P8
P7
P9
P10
P11
P12
A1
A1
VR'
A
200Ω
D2
A2
A2
VL'
N6
V-
N7
N8
N9
N10
N11
N12
P2
N4
N2
N5
N3
V-
All N-Channel bodies to V-, all P-Channel bodies to V+, except as shown.
DIGITAL INPUT BUFFER AND LEVEL SHIFTER
8
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May 3, 2012
HI-5046A/883
Die Characteristics
GLASSIVATION:
Type: Nitride over Silox
Silox Thickness: 12kÅ ±2kÅ
Nitride Thickness: 3.5kÅ ±1kÅ
DIE DIMENSIONS:
96mils x 81mils x 19mils
(2430µm x 2050µm x 480µm
SUBSTRATE POTENTIAL (Powered-up): V-
METALLIZATION:
DEVICE COUNT: 82
Type: Aluminum
Thickness: 16kÅ ±2kÅ
WORST CASE CURRENT DENSITY:
1.0 x 105A/cm2 at 20mA
Metallization Mask Layout
HI-5046A/883
D2
S2
A
D1
VS1
VR
VL
S4
D4
V+
D3
S3
NOTE: Unused pins may be connected. Ground all unused pins.
9
FN8274.0
May 3, 2012
HI-5046A/883
Design Information
The information contained in this section has been developed through characterization and is for use as
application and design information only. No guarantee is implied.
Typical Performance Curves
TA = +25°C, VSUPPLY = ±15V
NORMALIZED ON RESISTANCE
(REFERRED TO +25°C)
ON RESISTANCE (Ω)
80
60
V+ = +12V
V- = -12V
V+ = +10V
V- = -10V
40
20
V+ = +15V
V- = -15V
0
-15
0
-5
-10
5
10
1.2
1.1
VIN = 0V
1.0
0.9
0.8
0.7
0.6
15
-50
-25
0
ANALOG SIGNAL LEVEL (V)
50
75
100
125
FIGURE 18. NORMALIZED ON RESISTANCE vs TEMPERATURE
1.4
100nA
1.3
10nA
LEAKAGE CURRENT
NORMALIZED ON RESISTANCE
(REFERRED TO 1mA)
FIGURE 17. ON RESISTANCE vs ANALOG SIGNAL LEVEL AND POWER
SUPPLY VOLTAGE
1.2
1.1
IS(OFF) = ID(OFF)
1nA
ID(ON)
100pA
1.0
0
20
40
60
10pA
25
80
50
75
ANALOG CURRENT (mA)
100
125
TEMPERATURE (°C)
FIGURE 19. NORMALIZED ON RESISTANCE vs ANALOG CURRENT
FIGURE 20. ON/OFF LEAKAGE CURRENTS vs TEMPERATURE
200
CROSSTALK (dB)
-200
OFF ISOLATION (dB)
25
TEMPERATURE (°C)
-160
RL = 100Ω
-120
-80
RL = 10kΩ
-40
1
10
100
1k
10k
RL = 100Ω
120
RL = 1kΩ
80
RL = 10kΩ
40
100k
FREQUENCY (Hz)
FIGURE 21. OFF ISOLATION vs FREQUENCY
10
160
1M
0
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 22. CROSSTALK vs FREQUENCY
FN8274.0
May 3, 2012
HI-5046A/883
Design Information
The information contained in this section has been developed through characterization and is for use as
application and design information only. No guarantee is implied.
Typical Performance Curves
TA = +25°C, VSUPPLY = ±15V (Continued)
POWER CONSUMPTION (mW)
200
160
120
80
40
0
1k
10k
100k
1M
TOGGLE FREQUENCY (50% DUTY CYCLE) (Hz)
FIGURE 23. POWER CONSUMPTION vs FREQUENCY
11
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May 3, 2012
HI-5046A/883
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
LEAD FINISH
c1
-D-
-A-
BASE
METAL
SYMBOL
E
M
-Bbbb S
C A-B S
-C-
2
0.36
0.58
3
1.14
1.65
-
0.045
0.58
1.14
4
0.018
0.20
0.46
2
0.008
0.015
0.20
-
0.840
0.36
b1
0.014
0.023
b2
0.045
0.065
b3
0.023
c
0.008
c1
D
E
0.220
α
eA
eA/2
aaa M C A - B S
D S
-
0.66
0.026
A A
ccc M C A - B S
5.08
0.200
A
e
-
0.014
b2
b
MAX
b
L
S1
MIN
A
Q
SEATING
PLANE
MAX
M
(b)
D
BASE
PLANE
MILLIMETERS
MIN
b1
SECTION A-A
D S
INCHES
(c)
c
e
D S
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be measured
at the centroid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial
lead paddle. For this configuration dimension b3 replaces dimension
b2.
0.310
5.59
0.100 BSC
NOTES
0.38
3
21.34
5
7.87
5
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
α
90o
105o
90o
-
7
105o
-
aaa
-
0.015
-
0.38
-
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
N
16
5. This dimension allows for off-center lid, meniscus, and glass overrun.
16
8
Rev. 0 4/94
6. Dimension Q shall be measured from the seating plane to the base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
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in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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12
FN8274.0
May 3, 2012
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