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1-88
DG412/883, DG413/883
®
Monolithic Quad SPST CMOS Analog
Switches
The DG412-13/883 analog switches feature lower analog
ON-resistance (<35Ω) and faster switch time (tON <175ns)
compared to the DG212. Charge injection has been
reduced, simplifying sample and hold applications.
The improvements in the DG412-13/883 series are made
possible by using a high voltage silicon-gate process. An
epitaxial layer prevents the latch-up associated with older
CMOS technologies. The 44V maximum voltage range
permits controlling 40VP-P signals. Power supplies may be
single-ended from +5V to +34V, or split from ±5V to ±20V.
The four switches are bilateral, equally matched for AC or
bidirectional signals. The ON-resistance variation with analog
signals is quite low over a ±15V analog input range. All
switches in the DG412/883 use positive logic (i.e. a logic “1”
turns the switch ON). Two of the switches (1 and 4) in the
DG413/883 use positive logic and the other two switches (2
and 3) use negative logic (i.e. a logic “1” turns the switch
OFF). This permits independent control of turn-on and turn-off
times for SPDT configurations, permitting “break-beforemake” or “make-before-break” operation with a minimum of
external logic.
• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• ON-Resistance <35Ω Max
• Low Power Consumption (PD <35mW)
• Fast Switching Action
- tON <175ns
- tOFF <145ns
• Low Charge Injection
• Upgrade from DG212
• TTL/CMOS Compatible
• Single or Split Supply Operation
Applications
• Audio Switching
• Battery Operated Systems
• Data Acquisition
• Hi-Rel Systems
• Sample and Hold Circuits
• Communication Systems
• Automatic Test Equipment
Pinout
Ordering Information
PART NUMBER
FN3681.2
Features
The DG412/883 CMOS analog switch is a drop-in
replacement for the popular DG212 device. It includes four
independent single pole single throw (SPST) analog
switches and has TTL/CMOS compatible digital inputs.
TEMP. RANGE
(°C)
June 25, 2008
PACKAGE
PKG.
DWG. #
DG412AK/883
-55 to +125
16 Ld CerDIP
F16.3
DG413AK/883
-55 to +125
16 Ld CerDIP
F16.3
DG412/883, DG413/883
(16 LD CERDIP)
TOP VIEW
IN1 1
16 IN2
D1 2
15 D2
S1 3
14 S2
V- 4
13 V+
GND 5
12 VL
S4 6
11 S3
D4 7
10 D3
IN4 8
9 IN3
(NC) NO CONNECTION
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
DG412/883, DG413/883
Functional Diagrams
Four SPST Switches per Package Switches Shown for Logic “1” Input
DG412/883
DG413/883
S1
IN1
S1
IN1
D1
S2
D1
S2
IN2
IN2
D2
S3
D2
S3
IN3
IN3
D3
S4
D3
S4
IN4
IN4
D4
D4
TABLE 1. TRUTH TABLE
Pin Description
DG412/883
PIN
SYMBOL
DESCRIPTION
1
IN1
Logic Control for Switch 1
2
D1
3
DG413/883
LOGIC
SWITCH
SWITCH
1, 4
SWITCH
2, 3
Drain (Output) Terminal for Switch 1
0
OFF
OFF
ON
S1
Source (Input) Terminal for Switch 1
1
ON
ON
OFF
4
V-
Negative Power Supply Terminal
5
GND
6
S4
Source (Input) Terminal for Switch 4
7
D4
Drain (Output) Terminal for Switch 4
8
IN4
Logic Control for Switch 4
9
IN3
Logic Control for Switch 3
10
D3
Drain (Output) Terminal for Switch 3
11
S3
Source (Input) Terminal for Switch 3
12
VL
Logic Reference Voltage
13
V+
Positive Power Supply Terminal (Substrate)
14
S2
Source (Input) Terminal for Switch 2
15
D2
Drain (Output) Terminal for Switch 2
16
IN2
Logic Control for Switch 2
NOTE: Logic “0” ≤0.8V. Logic “1” ≥2.4V.
Ground Terminal (Logic Common)
2
FN3681.2
June 25, 2008
DG412/883, DG413/883
Absolute Maximum Ratings
Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44V
GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25V
VL (Note 3) . . . . . . . . . . . . . . . . . . . . . . . .(GND -0.3V) to (V+) +0.3V
Digital Inputs, VS, VD (Note 4) . . . . . .(V-) -2V to (V+) + 2V or 30mA,
Whichever Occurs First
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA
Current, S or D (Pulsed 1ms, 10% Duty Cycle) . . . . . . . . . . . 100mA
Thermal Resistance (Notes 1, 2)
θJA
θJC
16 LD CerDIP Package . . . . . . . . . . . . . .
75°C/W
20°C/W
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Operating Temperature (A Suffix) . . . . . . . . . . . . . .-55°C to +125°C
Storage Temperature Range (A Suffix) . . . . . . . . . .-65°C to +125°C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300°C
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . ±20V Max
Operating Temperature Range . . . . . . . . . . . . . . . .-55°C to +125°C
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V Max
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V Min
Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .≤20ns
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
DC Electrical Specifications
PARAMETERS
Device Tested at: V+ = +15V, V- = -15V, VL = 5V, GND = 0V, Unless Otherwise Specified. Parameters
with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits
established by characterization and are not production tested.
SYMBOL
Drain-to-Source
ON-Resistance
rDS(ON)
DG412/883
DG413/883
DG412/883
V+ = +13.5V,
V- = -13.5V,
IS = -10mA,
VD = ±8.5V
V+ = +10.8V,
V- = -0V,
IS = -10mA,
VD = 3.0V and
8.0V
DG413/883
Source OFF Leakage Current
IS(OFF)
DG412/883
DG413/883
DG412/883
V+ = 16.5V,
V- = -16.5V,
VD = -15.5V,
VS = 15.5V
V+ = 16.5V,
V- = -16.5V,
VD = 15.5V,
VS = -15.5V
DG413/883
Drain OFF Leakage Current
ID(OFF)
DG412/883
DG413/883
DG412/883
V+ = 16.5V,
V- = -16.5V,
VD = -15.5V,
VS = 15.5V
V+ = 16.5V,
V- = -16.5V,
VD = 15.5V,
VS = -15.5V
DG413/883
3
LIMITS
GROUP A
SUBGROUP
TEMPERATURE
(°C)
MIN
MAX
UNITS
VIN = 2.4V
1, 3
+25, -55
0
35
Ω
2
+125
0
45
Ω
VIN = 0.8V or
2.4V (Note 3)
1, 3
+25, -55
0
35
Ω
2
+125
0
45
Ω
VIN = 2.4V
1, 3
+25, -55
0
80
Ω
2
+125
0
100
Ω
VIN = 0.8V or
2.4V (Note 3)
1, 3
+25, -55
0
80
Ω
CONDITIONS
VIN = 0.8V
VIN = 0.8V or
2.4V (Note 3)
VIN = 0.8V
VIN = 0.8V or
2.4V (Note 3)
VIN = 0.8V
VIN = 0.8V or
2.4V (Note 3)
VIN = 0.8V
VIN = 0.8V or
2.4V (Note 3)
2
+125
0
100
Ω
1
+25
-0.25
+0.25
nA
2, 3
+125, -55
-20
+20
nA
1
+25
-0.25
+0.25
nA
2, 3
+125, -55
-20
+20
nA
1
+25
-0.25
+0.25
nA
2, 3
+125, -55
-20
+20
nA
1
+25
-0.25
+0.25
nA
2, 3
+125, -55
-20
+20
nA
1
+25
-0.25
+0.25
nA
2, 3
+125, -55
-20
+20
nA
1
+25
-0.25
+0.25
nA
2, 3
+125, -55
-20
+20
nA
1
+25
-0.25
+0.25
nA
2, 3
+125, -55
-20
+20
nA
1
+25
-0.25
+0.25
nA
2, 3
+125, -55
-20
+20
nA
FN3681.2
June 25, 2008
DG412/883, DG413/883
DC Electrical Specifications
PARAMETERS
Device Tested at: V+ = +15V, V- = -15V, VL = 5V, GND = 0V, Unless Otherwise Specified. Parameters
with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits
established by characterization and are not production tested. (Continued)
SYMBOL
Channel ON Leakage Current
ID(ON) +
IS(ON)
DG412/883
DG413/883
CONDITIONS
V+ = 16.5V,
V- = -16.5V,
VS = VD = ±15.5V
VIN = 2.4V
VIN = 0.8V or
2.4V (Note 3)
GROUP A
SUBGROUP
LIMITS
TEMPERATURE
(°C)
MIN
MAX
UNITS
1
+25
-0.4
+0.4
nA
2, 3
+125, -55
-40
+40
nA
1
+25
-0.4
+0.4
nA
2, 3
+125, -55
-40
+40
nA
Input Current with VIN Low
IIL
Input Under Test = 0.8V,
All Others = 2.4V
1, 2, 3
+25, +125, -55
-0.5
+0.5
µA
Input Current with VIN High
IIH
Input Under Test = 2.4V,
All Others = 0.8V
1, 2, 3
+25, +125, -55
-0.5
+0.5
µA
Positive Supply Current
I+
V+ = 16.5V, V- = -16.5,
VIN = 0Vor 5.0V
1
+25
-
+1.0
µA
2, 3
+125, -55
-
+5.0
µA
V+ = 13.2V, V- = 0V,
VIN = 0V or 5.0V
VL = 5.25V
Negative Supply Current
I-
V+ = 16.5V, V- = -16.5,
VIN = 0V or 5.0V
V+ = 13.2V, V- = 0V,
VIN = 0V or 5.0V
VL = 5.25V
Logic Supply Current
IL
V+ = 16.5V, V- = -16.5,
VIN = 0V or 5.0V
V+ = 13.2V, V- = 0V,
VIN = 0V or 5.0V
VL = 5.25V
Ground Current
IGND
V+ = 16.5V, V- = -16.5,
VIN = 0V or 5.0V
V+ = 13.2V, V- = 0V,
VIN = 0V or 5.0V
VL = 5.25V
AC Electrical Specifications
PARAMETERS
tON
Turn OFF Time
tOFF
4
+25
-
+1.0
µA
+125, -55
-
+5.0
µA
1
+25
-1.0
-
µA
2, 3
+125, -55
-5.0
-
µA
1
+25
-1.0
-
µA
2, 3
+125, -55
-5.0
-
µA
1
+25
-
+1.0
µA
2, 3
+125, -55
-
+5.0
µA
1
+25
-
+1.0
µA
2, 3
+125, -55
-
+5.0
µA
1
+25
-1.0
-
µA
2, 3
+125, -55
-5.0
-
µA
1
+25
-1.0
-
µA
2, 3
+125, -55
-5.0
-
µA
Device Tested at: V+ = +15V, V- = -15V, VL = 5V, GND = 0V, Unless Otherwise Specified. Parameters
with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits
established by characterization and are not production tested.
SYMBOL
Turn ON Time
1
2, 3
LIMITS
GROUP A
SUBGROUP
TEMPERATURE
(°C)
MIN
MAX
UNITS
CL = 35pF, VS = ±10V,
RL = 300Ω
9, 11
+25, -55
0
175
ns
10
+125
0
240
ns
V+ = 12V, V- = 0V,
CL = 35pF, VS = +8V,
RL = 300Ω
9, 11
+25, -55
0
250
ns
10
+125
0
400
ns
CL = 35pF, VS = ±10V,
RL = 300Ω
9, 11
+25, -55
0
145
ns
10
+125
0
160
ns
V+ = 12V, V- = 0V,
CL = 35pF, VS = +8V,
RL = 300Ω
9, 11
+25, -55
0
125
ns
10
+125
0
140
ns
CONDITIONS
FN3681.2
June 25, 2008
DG412/883, DG413/883
Electrical Specifications
Device Tested at: V+ = +15V, V- = -15V, VL = 5V, GND = 0V, Unless Otherwise Specified. Parameters with MIN
and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
PARAMETERS
TEMPERATURE
(°C)
MIN
MAX
UNITS
See Figure 2, VG = 0V, RG = 0Ω,
TA = +25°C, CL = 10nF
9
+25
-100
+100
pC
See Figure 2,
VG = 6V, RG = 0Ω, TA = +25°C
CL = 10nF, V+ = 12V, V- = 0V
9
SYMBOL
Charge Injection (Note 4)
CONDITIONS
Q
LIMITS
GROUP A
SUBGROUP
+25
pC
+25
-100
+100
pC
+25
pC
NOTES:
3. VIN = Input Voltage to Perform Proper Function.
4. Signals on SX, DX or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
TABLE 2. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS
SUBGROUPS (See “Electrical Spec Tables” on page 3 and page 4)
Interim Electrical Parameters (Pre Burn-In)
1
Final Electrical Test Parameters
1 (Note 5), 2, 3, 9, 10, 11
Group A Test Requirements
1, 2, 3, 9, 10, 11
Groups C and D Endpoints
1
NOTE:
5. PDA applies to Subgroup 1 only.
Typical Performance Curves
40
rDS(ON) (Ω)
35
A:
B:
C:
D:
E:
F:
240
±5V
±8V
±10V
±12V
±15V
±20V
V+ = 15V, V- = -15V
210 VL = 5V, VS = 10V
A
180
tON, tOFF (ns)
50
45
B
30
C
25
D
E
20
F
150
tON
120
tOFF
90
15
60
10
30
5
0
-20
TA = +25°C
-15
-10
-5
0
5
DRAIN VOLTAGE (V)
10
15
FIGURE 1. ON-RESISTANCE vs VD AND POWER SUPPLY
VOLTAGE
5
20
0
-55
-35
-15
5
25
45
65
TEMPERATURE (°C)
85
105
125
FIGURE 2. SWITCHING TIME vs TEMPERATURE
FN3681.2
June 25, 2008
DG412/883, DG413/883
Typical Performance Curves
(Continued)
100mA
40
V+ = 15V, V- = -15V
30 VL = 5V, TA = 25oC
10mA
V+ = 15V, V- = -15V
VL = 5V
20
ID(OFF)
1mA
I+, IISUPPLY
IS, ID (pA)
10
0
IS(OFF)
-10
ID + S(ON)
-20
100µA
4SW
10µA
IL
-30
1µA
4SW
-40
100nA
-50
-60
-15
1SW
1SW
-10
-5
0
5
10
DRAIN OR SOURCE VOLTAGE (V)
10nA
10
15
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 4. SUPPLY CURRENT vs INPUT SWITCHING FREQUENCY
FIGURE 3. LEAKAGE CURRENT vs ANALOG VOLTAGE
100
140
V+ = 15V, V- = -15V
120 VL = 5V
V+ = 15V, V- = -15V
80 VL = 5V
CL = 10nF
100
60
80
CL = 10nF
Q (pC)
Q (pC)
40
20
0
CL = 1nF
60
40
20
0
-20
CL = 1nF
-20
-40
-40
-60
-15
-60
-15
-10
-5
0
5
SOURCE VOLTAGE (V)
10
15
FIGURE 5. CHARGE INJECTION vs ANALOG VOLTAGE (VD)
Test Circuits
-10
-5
0
5
DRAIN VOLTAGE (V)
10
15
FIGURE 6. CHARGE INJECTION vs ANALOG VOLTAGE (VS)
.
VO is the steady state output with the switch on.
Feedthrough via switch capacitance may result in spikes at
the leading and trailing edge of the output waveform.
tR < 20ns (10% TO 90% VIN)
tF < 20ns (90% TO 10% VIN)
3V
LOGIC
INPUT
50%
0V
tOFF
SWITCH
INPUT VS
VO
SWITCH
OUTPUT
0.9 VO
0.9 VO
0V
tON
NOTE: Logic input waveform is inverted for switches that
have the opposite logic sense.
FIGURE 7A.
6
FN3681.2
June 25, 2008
DG412/883, DG413/883
+5V
VL
SWITCH
INPUT
+15V
V+
D1
S1
V+
SWITCH
OUTPUT
RG
D1
VO
VO
IN1
RL
LOGIC
INPUT
CL
VG
CL
V-
GND
V-
-15V
VIN = 3V
Repeat test for all IN and S.
For load conditions, see Specifications CL (includes fixture and
stray capacitance)
GND
R
V
L
V -----------------------------------O = S R +r
DS ( ON )
L
FIGURE 8A.
FIGURE 7B.
FIGURE 7. SWITCHING TIME
ΔVO
0V
INX
INX
OFF
ON
OFF
OFF
ON
Q = ΔVO x CL
OFF
INX dependent on switch configuration input polarity determined by
sense of switch.
FIGURE 8B.
FIGURE 8. CHARGE INJECTION
7
FN3681.2
June 25, 2008
DG412/883, DG413/883
Burn-In Circuit
R1
V-
C1
D1
VA
1 IN1
IN2 16
2 D1
D2 15
3 S1
S2 14
4 V-
V+ 13
5 GND
VL 12
6 S4
S3 11
7 D4
D3 10
8 IN4
IN3
R4
R2
V+
D2
C2
VL
9
D3
C3
R4
Typical Schematic Diagram (Typical Channel)
V+
S
VVL
V+
INX
D
GND
V-
8
FN3681.2
June 25, 2008
DG412/883, DG413/883
Die Characteristics
GLASSIVATION:
Type: Nitride
Thickness: 8kÅ ± 1kÅ
DIE DIMENSIONS:
2760µm x 1780µm x 485 ± 25µm
WORST CASE CURRENT DENSITY:
1.5 x 105A/cm2
METALLIZATION:
Type: SiAl
Thickness: 12kÅ ± 1kÅ
Metallization Mask Layout
DG412/883, DG413/883
D1
2
IN1
IN2
1
16
15
D2
S1
3
14
S2
V-
4
13
V+ SUBSTRATE
GND
5
12
VL
S4
6
11
S3
9
7
8
9
10
D4
IN4
IN3
D3
FN3681.2
June 25, 2008
DG412/883, DG413/883
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
LEAD FINISH
c1
-D-
-A-
BASE
METAL
E
M
-Bbbb S
C A-B S
-C-
S1
0.200
-
5.08
-
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.840
-
21.34
5
E
0.220
0.310
5.59
7.87
5
eA
e
ccc M
C A-B S
eA/2
c
aaa M C A - B S D S
D S
NOTES
-
b2
b
MAX
0.014
α
A A
MIN
b
A
L
MILLIMETERS
MAX
A
Q
SEATING
PLANE
MIN
M
(b)
D
BASE
PLANE
SYMBOL
b1
SECTION A-A
D S
INCHES
(c)
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
105o
90o
105o
-
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
α
90o
aaa
-
0.015
-
0.38
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
16
16
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
8
Rev. 0 4/94
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
FN3681.2
June 25, 2008
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