DATASHEET

ESIGNS
R NEW D NT
O
F
D
E
D
N
ME
C OM M E
EPL ACE
NO T R E
NDED R
E
nter at
e
M
C
M
rt
O
uppo
S
l
NO REC
a
ic
m/tsc
n
tersil.co
our Tech
contact ERSIL or www.in
88-INT
1-8Sheet
Data
January 30, 2006
HI-200/883
FN6059.2
Dual SPST CMOS Analog Switch
Features
The HI-200/883 is a monolithic device comprising two
independently selectable SPST switchers which feature fast
switching speeds (240ns typical) combined with low power
dissipation (15mW typical @ +25°C).
• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
Each switch provides low “ON” resistance operation for input
signal voltages up to the supply rails and for signal currents
up to 25mA continuous. Rugged DI construction eliminates
latch-up and substrate SCR failure modes.
• Wide Analog Signal Range . . . . . . . . . . . . . . . . . . . .±15V
All devices provide break-before-make switching and are
TTL and CMOS compatible for maximum application
versatility. HI-200/883 is an ideal component for use in high
frequency analog switching. Typical applications include
signal path switching, sample and hold circuits, digital filters,
and op amp gain switching networks.
• Analog Current Range (Continuous) . . . . . . . . . . . . 25mA
• Low “On” Release . . . . . . . . . . . . . . . . . . . . . . .100 Max
• TTL/CMOS Compatible . . . . . . . . . . . . . . 2.4V (Logic “1”)
• Turn-On Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns
• No Latch-Up
• Replaces DG200
Applications
• High Frequency Analog Switching
Functional Diagram
V+
• Sample and Hold Circuits
• Digital Filters
VREF
INPUT
• Op Amp Gain Switching Networks
SOURCE
LOGIC
INPUT
GATE
REFERENCE,
LEVEL SHIFTER,
AND DRIVER
SWITCH
CELL
Ordering Information
GATE
PART NUMBER
DRAIN
OUTPUT
V-
HI2-0200/883
TEMP.
RANGE (°C)
PACKAGE
-55 to 125
10 Pin Metal Can
PKG.
DWG. #
T10.B
Pinout
HI2-200/883 (METAL CAN)
TOP VIEW
V+
A1
10
1
9
IN1
2
8
OUT1
GND 3
7
VREF
A2
IN2
4
5
6
V-
OUT2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HI-200/883
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . .40V
VSUPPLY to Ground (V+, V-)  20V
Analog Input Voltage, (+VS ) . . . . . . . . . . . . . . . . . . .+VSUPPLY +2V
Analog Input Voltage, (-VS ) . . . . . . . . . . . . . . . . . . . . -VSUPPLY -2V
Digital Input Voltage, (+VA) . . . . . . . . . . . . . . . . . . . .+VSUPPLY +4V
Digital Input Voltage, (-VA) . . . . . . . . . . . . . . . . . . . . . -VSUPPLY -4V
Peak Current (S or D)
(Pulse at 1ms, 10% Duty Cycle Max). . . . . . . . . . . . . . . . . . 40mA
Continuous Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Lead Temperature (Soldering 10s) 275°C
Thermal Resistance
JA (°C/W)
JC (°C/W)
Metal Can Package . . . . . . . . . . . . . . .
160
75
Package Power Dissipation at +75°C
Metal Can Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.62W/°C
Package Power Dissipation Derating Factor above +75°C
Metal Can Package . . . . . . . . . . . . . . . . . . . . . . . . . . .8.24mW/°C
Recommended Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . .-55°C to +125°C
Operating Supply Voltage Range (±VSUPPLY) 15V
Analog Input Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY
Logic Low Level (VAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 0.8V
Logic High Level (VAH) . . . . . . . . . . . . . . . . . . . . 2.4V to VSUPPLY
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
TABLE 1. D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Tested at: VSUPPLY = 15V, VSUPPLY = 15V, VREF = OPEN, GND = 0V, Unless Otherwise Specified.
D.C. PARAMETERS
Switch “ON” Resistance
Source “OFF”
Leakage Current
SYMBOL
rDS
IS(OFF)
CONDITIONS
ID(OFF)
ID(ON)
IAL
High Level
Input Current
IAH
Supply Current
+ICC
UNITS
-
70

2, 3
-55 to 125
-
100

VA = 0.8V, VS = -10V, ID = 1mA,
All Unused Channels VA = 0.8V
1
25
-
70

2, 3
-55 to 125
-
100

1
25
-5
5
nA
2, 3
-55 to 125
-500
500
nA
1
25
-5
5
nA
2, 3
-55 to 125
-500
500
nA
VS = +14V, VD = -14V, VA = 2.4V,
All Unused Channels VA = 2.4V,
VD = +14V, VS = -14V
VD = -14V, VS = +14V, VA = 2.4V,
All Unused Channels VA = 2.4V,
VD = +14V, VS = -14V
VD = VS = +14V, VA = 0.8V,
All Unused Channels VA = 0.8V,
VD = VS = -14V
VAL = 0.8V
All Channels VA = 2.4V
VAH = 2.4V
All Channels VAH = 4.0V
All Channels VA = 0V
All Channels VA = 3V
2
MAX
25
VD = VS = -14V, VA = 0.8V,
All Unused Channels VA = 0.8V,
VD = VS = +14V
Low Level
Input Current
MIN
1
VD = +14V, VS = -14V, VA = 2.4V,
All Unused Channels VA = 2.4V,
VD = -14V, VS = +14V
Channel “ON”
Leakage Current
TEMPERATURE
(°C)
VA = 0.8V, VS = 10V, ID = -1mA,
All Unused Channels VA = 0.8V
VS = -14V, VD = +14V, VA = 2.4V,
All Unused Channels VA = 2.4V,
VD = -14V, VS = +14V
Drain “OFF”
Leakage Current
GROUP A
SUBGROUPS
1
25
-5
5
nA
2, 3
-55 to 125
-500
500
nA
1
25
-5
5
nA
2, 3
-55 to 125
-500
500
nA
1
25
-5
5
nA
2, 3
-55 to 125
-500
500
nA
1
25
-5
5
nA
2, 3
-55 to 125
-500
500
nA
1
25
-1.0
1.0
A
2, 3
-55 to 125
-1.0
1.0
A
1
25
-1.0
1.0
A
2, 3
-55 to 125
-1.0
1.0
A
1
25
-
2.0
µA
2, 3
-55 to 125
-
2.0
µA
1
25
-
2.0
mA
2, 3
-55 to 125
-
2.0
mA
FN6059.2
January 30, 2006
HI-200/883
TABLE 1. D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Tested at: VSUPPLY = 15V, VSUPPLY = 15V, VREF = OPEN, GND = 0V, Unless Otherwise Specified.
D.C. PARAMETERS
Supply Current
SYMBOL
-ICC
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
(°C)
MIN
MAX
UNITS
1
25
-2.0
-
µA
2, 3
-55 to 125
-2.0
-
µA
1
25
-2.0
-
µA
2, 3
-55 to 125
-2.0
-
µA
All Channels VA = 0V
All Channels VA = 3V
TABLE 2. A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Tested at: VSUPPLY = 15V, VSUPPLY = 15V, VREF = OPEN, GND = 0V, Unless Otherwise Specified.
PARAMETERS
SYMBOL
Turn “ON” Time
tON
Turn “OFF” Time
tOFF
GROUP A
SUBGROUPS
CONDITIONS
CL = 35pF,
RL = 1k
CL = 33pF,
RL = 1k
TEMPERATURE
(°C)
MIN
MAX
UNITS
9
25
-
500
ns
10, 11
55 to 125
-
800
ns
9
25
-
500
ns
10, 11
55 to 125
-
650
ns
TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS (NOTE 1)
Device Tested at: VSUPPLY = 15V, VSUPPLY = 15V, VREF = OPEN, GND = 0V
PARAMETERS
SYMBOL
Address Capacitance
CA
NOTE
TEMPERATURE
(°C)
MIN
MAX
UNITS
f = 1MHz, VAL = 0V
1
25
-
20
pF
CONDITIONS
Switches Input
Capacitance
CS (OFF)
f = 1MHz, VAH = 5V,
Measured Source to GND
1
25
-
20
pF
Switch Output Capacitance
CD (OFF)
f = 1MHz, VAH = 5V,
Measured Output to Ground
1
25
-
20
pF
CD (ON)
f = 1MHz, VAL = 0V,
Measured Output to Ground
1
25
-
30
pF
Drain to Source
Capacitance
CDS
f = 1MHz, VAH = 5V
1
25
-
2.0
pF
Off Isolation
VISO
f = 200kHz, VA = 2.4, RL = 1K,
VGEN = 1VP-P, CL = 10pF
1
25
55
-
dB
Cross Talk
VCT
f = 200kHz, VA = 2.4, RL = 1K,
VGEN = 1VP-P, CL = 10pF
1
25
60
-
dB
f = 200kHz, VA = 0 to 4V,
CL = 0.01µF
1
25
-10
10
mV
Charge Transfer Error
VCTE
NOTE:
1. Parameters listed in Table 2 are controlled via design or process parameters and are not directly tested at final production. These parameters
are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon
data from multiple production runs which reflect lot to lot and within lot variation.
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS
Interim Electrical Parameters (Pre Burn-in)
Final Electrical Test Parameters
SUBGROUPS (Tables 1 and 2)
1
1 (Note 2), 2, 3, 9, 10, 11
Group A Test Requirements
1, 2, 3, 9, 10, 11
Groups C & D Endpoints
1
NOTE:
2. PDA applies to Subgroup 1 only.
3
FN6059.2
January 30, 2006
HI-200/883
Test Circuits
+VCC
+VCC
S
D
VS
D
S
VD
ID
VIN
IIN
VIN
-VCC
GND
GND
-VCC
FIGURE 2. ID (OFF)
FIGURE 1. INPUT LEAKAGE CURRENT
+VCC
+VCC
S
S
VS
IS
VD
D
ID(ON)
VIN
VIN
V
GND
-VCC
GND
-VCC
FIGURE 4. ID (ON)
FIGURE 3. IS (OFF)
+VCC
I1
15V
D
S
STEP
GENERATOR
TEST
POINT
0.01µF
VIN
IN1 V+ IN3
S1
S3
D1
D3
IN2
IN4
S2
GND
I2
TEST
POINT
0.01µF
D2
V-
STEP
GENERATOR
(SEE NOTE)
TEST
POINT
0.01µF
S4
D4
GND
TEST
POINT
0.01µF
-15V GND
-VCC
FIGURE 5. SUPPLY CURRENTS
4
FIGURE 6. CHARGE TRANSFER ERROR
FN6059.2
January 30, 2006
HI-200/883
Test Circuits
(Continued)
15V
+VCC
S
SINE WAVE
GENERATOR
24V
D
1k
TEST
POINT
VIN
VD
GND
TEST
POINT
2.4V
1k
-VCC
0.8V
TEST
POINT
1k
S3
D1
D3
IN2
IN4
S2
D2
V-
S4
D4
GND
1k
2.4V
1k
TEST
POINT
TEST
POINT
FIGURE 8. OFF CHANNEL ISOLATION
15V
24V
TEST
POINT
S1
-15V GND
FIGURE 7. RDS
1k
SINE WAVE
GENERATOR
IN1 V+ IN3
24V
0.8V
24V
IN1 V+ IN3
S1
S3
D1
D3
IN2
IN4
S2
S4
D2
V-
1k
0.8V
TEST
POINT
24V
0.8V
1k
TEST
POINT
D4
GND
-15V GND
1k
STEP
GENERATOR
FIGURE 9. CROSSTALK BETWEEN CHANNELS
5
FN6059.2
January 30, 2006
HI-200/883
Switching Waveforms
FIGURE 10.
FIGURE 11.
6
FN6059.2
January 30, 2006
HI-200/883
Burn-In Circuit
FIGURE 12. HI-200/883 METAL CAN (TO-99)
NOTES:
3. R1 = R2 = 10k
4. C1 = C2 = 0.01µF (per socket) or 0.1µF (per row)
5. D1 = D2 = IN4002 or equivalent
6. |(V+) - (V-)| = 30V
Schematic Diagrams
TTL/CMOS REFERENCE CIRCUIT VREF CELL
V+
R6
300
R2
5K
QP2
QP1
QP3
QP4
MP13
VREF
QN4
QP5
TO P2
QN1
R3
24.2K
D3
QN2
GND
MN14
R4
5.4K
VLL
R5
7.9K
MN15
MN16
MN17
V-
R7
100K
GND
7
FN6059.2
January 30, 2006
HI-200/883
Schematic Diagrams
(Continued)
SWITCH CELL
A’
N11
V+
N12
P11
INPUT
OUTPUT
N13
V-
P12
A’
DIGITAL INPUT BUFFER AND LEVEL SHIFTER
V+
P3
P1
V+
P4
N11
N1
P6
D1
R1
200
P5
P8
P7
TO VLL
INPUT
TO VREF
D2
N12
P10
P9
N8
N6
N9
P11
OUTPUT
N13
N10
N7
P2
VA
V-
P12
N2
N4
N5
N3
VV-
8
FN6059.2
January 30, 2006
HI-200/883
Test Circuits and Waveforms
TA = 25°C, VSUPPLY = ±15V, VAH = 2.4V, VAL = 0.8V and VREF = Open
80
100
V+ = +10V
V- = -10V
VIN = 0V
60
ON RESISTANCE ()
ON RESISTANCE ()
70
50
40
30
20
V+ = +12.5V
V- = -12.5V
50
V+ = +15V
V- = -15V
10
0
-50
-25
0
25
50
75
100
0
-15
125
-10
TEMPERATURE (°C)
FIGURE 13. ON RESISTANCE vs TEMPERATURE
-5
0
5
ANALOG SIGNAL LEVEL (V)
10
15
FIGURE 14. ON RESISTANCE vs ANALOG SIGNAL
LEVEL AND POWER SUPPLY VOLTAGE
100
90
80
SWITCH CURRENT (mA)
ID(ON)
1.0
70
60
50
40
30
20
10
0.1
0
25
50
75
100
125
1
0
2
3
4
5
6
7
VOLTAGE ACROSS SWITCH (V)
TEMPERATURE (°C)
FIGURE 15. LEAKAGE CURRENT vs TEMPERATURE
FIGURE 16. SWITCH CURRENT vs VOLTAGE
140
120
OFF ISOLATION (dB)
CURRENT (nA)
IS(OFF)/ID(OFF)
10
100
80
RL = 1k
60
40
20
0
100Hz
1kHz
10kHz
100kHz
1MHz
FREQUENCY (Hz)
FIGURE 17. OFF ISOLATION vs FREQUENCY
9
FN6059.2
January 30, 2006
HI-200/883
Die Characteristics
DIE ATTACH:
Material: Gold/Silicon Eutectic Alloy
Temperature: Metal Can - 420°C (Max)
Metallization Mask Layout
HI-200
GND
A2
2
IN 2
OUT 2
1
10
9
3
4
5
V-
10
V+
A1
6
8
IN 1
7
OUT 1
VREF
FN6059.2
January 30, 2006
HI-200/883
Metal Can Packages (Can)
T10.B MIL-STD-1835 MACY1-X10 (A2)
REFERENCE PLANE
A
10 LEAD METAL CAN PACKAGE
e1
L
L2
L1
INCHES
SYMBOL
ØD2
A
A
k1
Øe
ØD ØD1
2
N
1

Øb1
Øb
F

k
C
L
BASE AND
SEATING PLANE
Q
BASE METAL
Øb1
LEAD FINISH
Øb2
SECTION A-A
NOTES:
1. (All leads) Øb applies between L1 and L2. Øb1 applies between
L2 and 0.500 from the reference plane. Diameter is uncontrolled
in L1 and beyond 0.500 from the reference plane.
2. Measured from maximum diameter of the product.
MIN
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.165
0.185
4.19
4.70
-
Øb
0.016
0.019
0.41
0.48
1
Øb1
0.016
0.021
0.41
0.53
1
Øb2
0.016
0.024
0.41
0.61
-
ØD
0.335
0.375
8.51
9.52
-
ØD1
0.305
0.335
7.75
8.51
-
ØD2
0.110
0.160
2.79
4.06
-
e
e1
0.230 BSC
5.84 BSC
0.115 BSC
-
2.92 BSC
-
F
-
0.040
-
1.02
-
k
0.027
0.034
0.69
0.86
-
k1
0.027
0.045
0.69
1.14
2
12.70
19.05
1
1.27
1
L
0.500
0.750
L1
-
0.050
L2
0.250
-
6.35
-
1
Q
0.010
0.045
0.25
1.14
-
-

36o BSC
36o BSC
36o BSC
36o BSC
N
10
10

3.  is the basic spacing from the centerline of the tab to terminal 1
and is the basic spacing of each lead or lead position (N -1
places) from looking at the bottom of the package.
3
3
4
Rev. 0 5/18/94
4. N is the maximum number of terminal positions.
5. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
6. Controlling dimension: INCH.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
FN6059.2
January 30, 2006
Similar pages