Si1330EDL Vishay Siliconix N-Channel 60 V (D-S) MOSFET FEATURES PRODUCT SUMMARY VDS (V) 60 RDS(on) (Ω) ID (A) 2.5 at VGS = 10 V 0.25 3 at VGS = 4.5 V 0.23 8 at VGS = 3 V 0.05 • Halogen-free According to IEC 61249-2-21 Definition • TrenchFET® Power MOSFET • ESD Protected: 2000 V • Compliant to RoHS Directive 2002/95/EC APPLICATIONS • P-Channel Driver - Notebook PC - Servers SOT-323 SC-70 (3-LEADS) G D 1 S D KD XX YY Marking Code 3 Lot Traceability and Date Code 2 G Part # Code Top View Ordering Information: Si1330EDL-T1-E3 (Lead (Pb)-free) Si1330EDL-T1-GE3 (Lead (Pb)-free and Halogen-free) S ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted Parameter Symbol 5s Steady State Drain-Source Voltage VDS 60 Gate-Source Voltage VGS ± 20 Continuous Drain Current (TJ = 150 °C)a TA = 25 °C TA = 70 °C Pulsed Drain Current IS TA = 25 °C TA = 70 °C PD 0.24 0.2 0.19 1.0 0.26 A 0.23 0.31 0.28 0.20 0.18 TJ, Tstg Operating Junction and Storage Temperature Range V 0.25 IDM Continuous Source Current (Diode Conduction)a Maximum Power Dissipationa ID Unit - 55 to 150 W °C THERMAL RESISTANCE RATINGS Parameter Maximum Junction-to-Ambienta Maximum Junction-to-Foot (Drain) Symbol t≤5s Steady State Steady State RthJA RthJF Typical Maximum 355 400 380 450 285 340 Unit °C/W Notes: a. Surface mounted on 1" x 1" FR4 board. Document Number: 72861 S10-0721-Rev. B, 29-Mar-10 www.vishay.com 1 Si1330EDL Vishay Siliconix SPECIFICATIONS TJ = 25 °C, unless otherwise noteda Limits Parameter Symbol Test Conditions Min. Typ. Max. 2.0 2.5 Unit Static VDS VGS = 0 V, ID = 10 µA 60 VGS(th) VDS = VGS, ID = 250 µA 1 Gate-Body Leakage IGSS VDS = 0 V, VGS = ± 10 V Zero Gate Voltage Drain Current IDSS On-State Drain Currentb ID(on) Drain-Source Breakdown Voltage Gate-Threshold Voltage ±1 VDS = 60 V, VGS = 0 V 1 VDS = 60 V, VGS = 0 V, TJ = 55 °C 10 VGS = 10 V, VDS = 7.5 V 0.5 VGS = 4.5 V, VDS = 10 V 0.4 VGS = 3 V, VDS = 10 V 0.05 µA A VGS = 10 V, ID = 0.25 A 1.0 2.5 RDS(on) VGS = 4.5 V, ID = 0.2 A 1.4 3 VGS = 3 V, ID = 0.025 A 3.0 8 Forward Transconductanceb gfs VDS = 10 V, ID = 0.25 A 350 Diode Forward Voltage VSD IS = 0.23 A, VGS = 0 V 0.83 1.2 0.4 0.6 Drain-Source On-Resistanceb V Ω mS V Dynamicb Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Gate Resistance Rg VDS = 10 V, VGS = 4.5 V ID ≅ 0.25 A VDD = 30 V, RL = 150 Ω ID ≅ 0.2 A, VGEN = 10 V Rg = 10 Ω tr td(off) Turn-Off Time nC Ω 173 td(on) Turn-On Time 0.11 0.15 tf 3.8 10 4.8 15 12.8 20 9.6 15 ns Notes: a. Pulse test: PW ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 1.0 1.0 TJ = - 55 °C 6V VGS = 10 V, 7 V 25 °C 0.8 5V I D - Drain Current (A) I D - Drain Current (A) 0.8 0.6 4V 0.4 125 °C 0.6 0.4 0.2 0.2 3V 0 0.0 0 1 2 3 4 VDS - Drain-to-Source Voltage (V) Output Characteristics www.vishay.com 2 5 0 1 2 3 4 5 VGS - Gate-to-Source Voltage (V) Transfer Characteristics Document Number: 72861 S10-0721-Rev. B, 29-Mar-10 Si1330EDL Vishay Siliconix 4.0 7 3.5 6 VGS - Gate-to-Source Voltage (V) R DS(on) - On-Resistance (Ω) TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 3.0 2.5 VGS = 4.5 V 2.0 1.5 VGS = 10 V 1.0 0.5 0.0 0.0 0.2 0.4 0.6 0.8 VDS = 10 V ID = 250 mA 5 4 3 2 1 0 0.0 1.0 0.1 0.2 0.3 0.4 0.5 0.6 Qg - Total Gate Charge (nC) I D - Drain Current (mA) On-Resistance vs. Drain Current Gate Charge 1000 2.0 VGS = 10 V at 250 mA VGS = 0 V I S - Source Current (A) R DS(on) - On-Resistance (Normalized) 1.6 VGS = 4.5 V at 200 mA 1.2 0.8 100 TJ = 125 °C TJ = 25 °C 10 0.4 TJ = - 55 °C 0.0 - 50 1 - 25 0 25 50 75 100 125 0 150 0.6 0.9 1.2 1.5 TJ - Junction Temperature (°C) VSD - Source-to-Drain Voltage (V) On-Resistance vs. Junction Temperature Source-Drain Diode Forward Voltage 0.4 5 ID = 200 mA 0.2 4 VGS(th) Variance (V) R DS(on) - On-Resistance (Ω) 0.3 3 2 1 ID = 250 µA 0.0 - 0.2 - 0.4 - 0.6 0 0 2 4 6 8 10 - 0.8 - 50 - 25 0 25 50 75 100 125 150 VGS - Gate-to-Source Voltage (V) TJ - Temperature (°C) On-Resistance vs. Gate-Source Voltage Threshold Voltage Variance over Temperature Document Number: 72861 S10-0721-Rev. B, 29-Mar-10 www.vishay.com 3 Si1330EDL Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 10 5 IDM Limited Limited by R DS(on)* 4 I D - Drain Current (A) Power (W) 1 3 TA = 25 °C 2 1 ms 0.1 100 ms TA = 25 °C Single Pulse 0.01 1 10 ms ID(on) Limited 1s 10 s, DC BVDSS Limited 0 10 -2 10 -1 1 10 100 Time (s) Single Pulse Power 600 0.001 0.1 1 10 100 VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which R DS(on) is specified Safe Operating Area 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 Notes: 0.1 PDM 0.1 0.05 t1 t2 1. Duty Cycle, D = t1 t2 2. Per Unit Base = R thJA = 380 °C/W 0.02 3. T JM - T A = PDMZthJA(t) Single Pulse 0.01 10-4 10-3 4. Surface Mounted 10-2 10-1 1 Square Wave Pulse Duration (s) 10 100 600 Normalized Thermal Transient Impedance, Junction-to-Ambient 2 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10 -4 10 -3 10 -2 10 -1 Square Wave Pulse Duration (s) 1 10 Normalized Thermal Transient Impedance, Junction-to-Foot Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?72861. www.vishay.com 4 Document Number: 72861 S10-0721-Rev. B, 29-Mar-10 Package Information Vishay Siliconix SCĆ70: 3ĆLEADS MILLIMETERS 3 E1 E 1 2 e b e1 D c A2 A L 0.08 c A1 Dim A A1 A2 b c D E E1 e e1 L INCHES Min Nom Max Min Nom Max 0.90 – 1.10 0.035 – 0.043 – – 0.10 – – 0.004 0.80 – 1.00 0.031 – 0.039 0.25 – 0.40 0.010 – 0.016 0.10 – 0.25 0.004 – 0.010 1.80 2.00 2.20 0.071 0.079 0.087 1.80 2.10 2.40 0.071 0.083 0.094 1.15 1.25 1.35 0.045 0.049 0.053 0.65BSC 0.026BSC 1.20 1.30 1.40 0.047 0.051 0.055 0.10 0.20 0.30 0.004 0.008 0.012 7_Nom 7_Nom ECN: S-03946—Rev. C, 09-Jul-01 DWG: 5549 Document Number: 71153 06-Jul-01 www.vishay.com 1 AN813 Vishay Siliconix Single-Channel LITTLE FOOTR SC-70 3-Pin and 6-Pin MOSFET Recommended Pad Pattern and Thermal Peformance INTRODUCTION BASIC PAD PATTERNS This technical note discusses pin-outs, package outlines, pad patterns, evaluation board layout, and thermal performance for single-channel LITTLE FOOT power MOSFETs in the SC-70 package. These new Vishay Siliconix devices are intended for small-signal applications where a miniaturized package is needed and low levels of current (around 350 mA) need to be switched, either directly or by using a level shift configuration. Vishay provides these single devices with a range of on-resistance specifications and in both traditional 3-pin and new 6-pin versions. The new 6-pin SC-70 package enables improved on-resistance values and enhanced thermal performance compared to the 3-pin package. See Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/doc?72286) for the basic pad layout and dimensions for the 3-pin SC-70 and the 6-pin SC-70. These pad patterns are sufficient for the low-power applications for which this package is intended. Increasing the pad pattern has little effect on thermal resistance for the 3-pin device, reducing it by only 10% to 15%. But for the 6-pin device, increasing the pad patterns yields a reduction in thermal resistance on the order of 35% when using a 1-inch square with full copper on both sides of the printed circuit board (PCB). The availability of four drain leads rather than the traditional single drain lead allows a better thermal path from the package to the PCB and external environment. PIN-OUT Figure 1 shows the pin-out description and Pin 1 identification for the single-channel SC-70 device in both 3-pin and 6-pin configurations. The pin-out of the 6-pin device allows the use of four pins as drain leads, which helps to reduce on-resistance and junction-to-ambient thermal resistance. SOT-323 SC-70 (3-LEADS) SOT-363 SC-70 (6-LEADS) Top View G Top View 1 3 S D 2 D 1 6 D 2 5 G 3 4 EVALUATION BOARDS FOR THE SINGLE SC70-3 AND SC70-6 Figure 2 shows the 3-pin and 6-pin SC-70 evaluation boards (EVB). Both measure 0.6 inches by 0.5 inches. Their copper pad traces are the same as described in the previous section, Basic Pad Patterns. Both boards allow interrogation from the outer pins to 6-pin DIP connections, permitting test sockets to be used in evaluation testing. The thermal performance of the single SC-70 has been measured on the EVB for both the 3-pin and 6-pin devices, the results shown in Figures 3 and 4. The minimum recommended footprint on the evaluation board was compared with the industry standard of 1-inch square FR4 PCB with copper on both sides of the board. FIGURE 1. For package dimensions see outline drawings: SC-70 (3-Leads) (http://www.vishay.com/doc?71153) SC-70 (6-Leads) (http://www.vishay.com/doc?71154) Front of Board SC70-3 Back of Board, SC70-3 and SC70-6 Front of Board SC70-6 ChipFETr ChipFETr vishay.com FIGURE 2. Document Number: 71236 12-Dec-03 www.vishay.com 1 AN813 Vishay Siliconix THERMAL PERFORMANCE Junction-to-Foot Thermal Resistance (the Package Performance) SC-70 (6-PIN) Thermal performance for the 3-pin SC-70 measured as junction-to-foot thermal resistance is 285_C/W typical, 340_C/W maximum. Junction-to-foot thermal resistance for the 6-pin SC70-6 is 105_C/W typical, 130_C/W maximum — a nearly two-thirds reduction compared with the 3-pin device. The “foot” is the drain lead of the device as it connects with the body. This improved performance is obtained by the increase in drain leads from one to four on the 6-pin SC-70. Note that these numbers are somewhat higher than other LITTLE FOOT devices due to the limited thermal performance of the Alloy 42 lead-frame compared with a standard copper lead-frame. The typical RθJAfor the single 3-pin SC-70 is 360_C/W steady state, compared with 180_C/W for the 6-pin SC-70. Maximum ratings are 430_C/W for the 3-pin device versus 220_C/W for the 6-pin device. All figures are based on the 1-inch square FR4 test board.The following table shows how the thermal resistance impacts power dissipation for the two different pin-outs at two different ambient temperatures. TJ(max) * TA PD + Rq JA o o PD + 150 Co* 25 C 180 CńW Room Ambient 25 _C Elevated Ambient 60 _C TJ(max) * TA PD + Rq JA TJ(max) * TA Rq JA o o PD + 150 Co* 25 C 360 CńW o o PD + 150 Co* 60 C 360 CńW PD + 347 mW PD + 250 mW PD + 694 mW PD + 500 mW To aid comparison further, Figures 3 and 4 illustrate single-channel SC-70 thermal performance on two different board sizes and two different pad patterns. The results display the thermal performance out to steady state and produce a graphic account of the thermal performance variation between the two packages. The measured steady state values of RθJA for the single 3-pin and 6-pin SC-70 are as follows: LITTLE FOOT SC-70 Thermal Resistance (C/W) 320 3-pin 6-pin 160 80 329.7_C/W 360_C/W 211.8_C/W 3-pin 6-pin 160 80 1” Square FR4 PCB 0 10-3 10-2 10-1 1 10 100 1000 10-5 10-4 Comparison of SC70-3 and SC70-6 on EVB 10-3 10-2 10-1 1 10 100 1000 Time (Secs) Time (Secs) 2 410.31_C/W 240 0.5 in x 0.6 in EVB 0 www.vishay.com 6-Pin The results show that designers can reduce thermal resistance RθJA on the order of 20% simply by using the 6-pin device rather than the 3-pin device. In this example, a 80_C/W reduction was achieved without an increase in board area. If increasing board size is an option, a further 118_C/W reduction could be obtained by utilizing a 1-inch square PCB area. 320 240 3-Pin 2) Industry standard 1” square PCB with maximum copper both sides. 400 FIGURE 3. Rq JA NOTE: Although they are intended for low-power applications, devices in the 6-pin SC-70 will handle power dissipation in excess of 0.5 W. 400 10-5 10-4 TJ(max) * TA o o PD + 150 Co* 60 C 180 CńW 1) Minimum recommended pad pattern (see Figure 4) on the EVB. SC-70 (3-PIN) Thermal Resistance (C/W) PD + Elevated Ambient 60 _C Testing Junction-to-Ambient Thermal Resistance (dependent on PCB size) PD + Room Ambient 25 _C FIGURE 4. Comparison of SC70-3 and SC70-6 on 1” Square FR4 PCB Document Number: 71236 12-Dec-03 Application Note 826 Vishay Siliconix 0.045 (1.143) (0.648) 0.022 (0.559) 0.026 0.025 (0.622) (2.438) 0.096 RECOMMENDED MINIMUM PADS FOR SC-70: 3-Lead 0.027 (0.686) 0.071 (1.803) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE Document Number: 72601 Revision: 21-Jan-08 www.vishay.com 17 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU. Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000