IRFD9010, SiHFD9010 Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • • • • • • • • - 50 RDS(on) (Ω) VGS = - 10 V 0.50 Qg (Max.) (nC) 11 Qgs (nC) 3.8 Qgd (nC) 4.1 Configuration Single For Automatic Insertion Compact, End Stackable Fast Switching Low Drive Current Easy Paralleled Excellent Temperature Stability P-Channel Versatility Compliant to RoHS Directive 2002/95/EC DESCRIPTION The HVMDIP technology is the key to Vishay’s advanced line of power MOSFET transistors. The efficient geometry and unique processing of the HVMDIP design achieves very low on-state resistance combined with high transconductance and extreme device ruggedness. The p-channel HVMDIPs are designed for application which require the convenience of reverse polarity operation. They retain all of the features of the more common n-channel HVMDIPs such as voltage control, very fast switching, ease of paralleling, and excellent temperature stability. P-channels HVMDIPs are intended for use in power stages where complementary symmetry with n-channel devices offers circuit simplification. They are also very useful in drive stages because of the circuit versatility offered by the reverse polarity connection. Applications include motor control, audio amplifiers, switched mode converters, control circuits and pulse amplifiers. S HVMDIP G S G D D P-Channel MOSFET ORDERING INFORMATION Package HVMDIP IRFD9010PbF Lead (Pb)-free SiHFD9010-E3 IRFD9010 SnPb SiHFD9010 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS - 50 Gate-Source Voltage VGS ± 20 Continuous Drain Current VGS at - 10 V TC = 25 °C TC = 100 °C Pulsed Drain Currenta ID IDM Linear Derating Factor Inductive Current, Clamped L = 100 µH see fig. 14 ILM - 8.8 see fig. 15 IL - 1.5 Maximum Power Dissipation TC = 25 °C for 10 s A - 8.8 Inductive Current, Unclamped (Avalanche Current) Soldering Recommendations (Peak Temperature) V - 1.1 - 0.68 0.01 Operating Junction and Storage Temperature Range UNIT PD 1 TJ, Tstg - 55 to + 150 300d W/°C A W °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = - 25 V, starting TJ = 25 °C, L = 52 mH, Rg = 25 Ω, IAS = - 2.0 A (see fig. 12). c. ISD ≤ - 4.0 A, dI/dt ≤ 75 A/μs, VDD ≤ VDS, TJ ≤ 175 °C. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91405 S10-0998-Rev. A, 26-Apr-10 www.vishay.com 1 IRFD9010, SiHFD9010 Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER Maximum Junction-to-Ambient SYMBOL TYP. MAX. UNIT RthJA - 120 °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0 V, ID = - 250 μA - 50 - - V ΔVDS/TJ Reference to 25 °C, ID = - 1 mA - - 0.091 - V/°C VGS(th) VDS = VGS, ID = - 250 μA - 2.0 - - 4.0 V nA Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current On-State Drain Current Drain-Source On-State Resistance Forward Transconductance IGSS IDSS VGS = ± 20 V - - ± 500 VDS = - 50 V, VGS = 0 V - - - 250 VDS = - 40 V, VGS = 0 V, TJ = 125 °C - - - 1000 μA ID(on) VGS = 10 V VDS > ID(on) x RDS(on) max. - 1.1 - - A RDS(on) VGS = - 10 V ID = - 0.58 Ab - 0.35 0.50 Ω 1.7 2.5 - S - 240 - gfs VDS = - 20 V, ID = - 2.4 A Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) Rise Time Turn-Off Delay Time Fall Time tr td(off) VGS = 0 V, VDS = - 25 V, f = 1.0 MHz, see fig. 5 VGS = - 10 V ID = - 4.7 A, VDS = 0.8 V see fig. 6 and 13b VDD = - 25 V, ID = - 4.7 A Rg = 24 Ω, RD = 5.6 Ω, see fig. 10b tf Internal Drain Inductance LD Internal Source Inductance LS Between lead, 6 mm (0.25") from package and center of die contact D - 160 - - 30 - - 7.2 11 - 2.5 3.8 - 2.7 4.1 - 6.1 9.2 - 47 71 - 13 20 - 39 59 - 4.0 - - 6.0 - - - - 1.1 - - - 8.8 pF nC ns nH G S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS = - 0.7 A, VGS = 0 Vb TJ = 25 °C, IF = - 4.7 A, dI/dt = 100 A/μsb - - - 5.5 V 33 75 160 ns 0.090 0.22 0.52 μC Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %. www.vishay.com 2 Document Number: 91405 S10-0998-Rev. A, 26-Apr-10 IRFD9010, SiHFD9010 Vishay Siliconix 10 - 10 V RDS(on), Drain-to-Source on Resistance (Normalized) TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 80 μs Pulse Width - ID, Drain Current (A) -8V 8 6 -7V 4 VGS = - 6 V 2 -5V -4V 0 0 10 5 10 15 20 25 3.0 ID = - 4.7 V 2.4 1.8 1.2 0.6 VGS = - 10 V 0 - 60 - 40 - 20 0 - VGS, Drain-to-Source Voltage (V) TJ, Junction Temperature (°C) Fig. 1 - Typical Output Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature 500 80 μs Pulse Width VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd - 10 V 8 400 -8V 6 Capacitance (pF) - ID, Drain Current (A) 20 40 60 80 100 120 140 160 -7V 4 VGS = - 6 V 2 300 Ciss 200 Coss 100 -5V Crss -4V 0 0 0 1 2 3 4 1 5 100 - VGS, Drain-to-Source Voltage (V) - VGS, Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 10 20 - VGS, Gate-to-Source Voltage (V) 80 μs Pulse Width VDS = 2 x VGS - ID, Drain Current (A) 10 1 TJ = 150 °C 0.1 TJ = 25 °C 0.01 0.001 ID = - 4.7 A 16 VDS = - 40 V 12 8 4 For Test Circuit See Figure 13 0 0 3 4 6 8 10 0 3 6 9 12 15 - VGS, Drain-to-Source Voltage (V) Qg, Total Gate Charge (nC) Fig. 3 - Typical Transfer Characteristics Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Document Number: 91405 S10-0998-Rev. A, 26-Apr-10 www.vishay.com 3 IRFD9010, SiHFD9010 Vishay Siliconix 2.0 - ID, Drain Current (A) - ISD, Reverse Drain Current (A) 100 TJ = 150 °C 10 TJ = 25 °C 1 1.6 1.2 0.8 0.4 0 0.1 0 1 2 3 4 5 25 50 75 125 150 - VSD, Source-to-Drain Voltage (V) TC, Case Temperature (°C) Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 9 - Maximum Drain Current vs. Case Temperature 100 RD Operation in this Area Limited by RDS(on) - ID, Drain Current (A) 100 10 VDS 10 μs 100 μs VGS D.U.T. Rg +VDD 1 ms 1 10 ms 100 ms 0.1 1s TC = 25 °C TJ = 150 °C Single Pulse 0.01 1 Fig. 10a - Switching Time Test Circuit DC 10 - 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 100 - VDS, Drain-to-Source Voltage (V) Fig. 8 - Maximum Safe Operating Area td(on) tr td(off) tf VGS 10 % 90 % VDS Fig. 10b - Switching Time Waveforms www.vishay.com 4 Document Number: 91405 S10-0998-Rev. A, 26-Apr-10 IRFD9010, SiHFD9010 Vishay Siliconix Thermal Response (ZDthJC) 1000 100 0.5 10 0.2 0.1 0.05 PDM 0.02 t1 t2 Notes: 1. Duty Factor, D = t1/t2 2. Peak TJ = PDM x TthJC + TC 0.01 1 Single Pulse (Thermal Response) 0.1 0.00001 0.0001 0.001 0.01 0.1 1 10 100 t1, Rectangular Pulse Duration (s) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case L Vary tp to obtain required IAS VDS QG - 10 V D.U.T Rg QGS + V DD IAS QGD VG - 10 V 0.01 W tp Charge Fig. 12a - Unclamped Inductive Test Circuit Fig. 13a - Basic Gate Charge Waveform Current regulator Same type as D.U.T. IAS 50 kΩ 12 V 0.2 µF 0.3 µF VDS - D.U.T. + VDS VDD VGS tp - 3 mA VDS IG ID Current sampling resistors Fig. 12b - Unclamped Inductive Waveforms Document Number: 91405 S10-0998-Rev. A, 26-Apr-10 Fig. 13b - Gate Charge Test Circuit www.vishay.com 5 IRFD9010, SiHFD9010 Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit D.U.T. + Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + + - - Rg • dV/dt controlled by RG • ISD controlled by duty factor "D" • D.U.T. - device under test + - VDD Compliment N-Channel of D.U.T. for driver Driver gate drive P.W. Period D= P.W. Period VGS = - 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage VDD Body diode forward drop Inductor current Ripple ≤ 5 % * ISD VGS = - 5 V for logic level and - 3 V drive devices Fig. 14 - For P-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91405. www.vishay.com 6 Document Number: 91405 S10-0998-Rev. A, 26-Apr-10 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000