IRFD113, SiHFD113 www.vishay.com Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • For Automatic Insertion 60 RDS(on) (Ω) VGS = 10 V • Compact Plastic Package 0.8 Qg (Max.) (nC) 7 • End Stackable Qgs (nC) 2 • Fast Switching Qgd (nC) 7 • Low Drive Current Configuration Single • Easily Paralleled • Excellent Temperature Stability • Compliant to RoHS Directive 2002/95/EC D Note * Pb containing terminations are not RoHS compliant, exemptions may apply HVMDIP DESCRIPTION G S The HVMDIP technology is the key to Vishay’s advanced line of power MOSFET transistors. The efficient geometry and unique processing of the HVMDIP design achieves very low on-state resistance combined with high transconductance and extreme device ruggedness. HVMDIPs feature all of the established advantages of MOSFETs such as voltage control, very fast switching, ease of paralleling, and temperature stability of the electrical parameters. The HVMDIP 4 pin, dual-in-line package brings the advantages of HVMDIPs to high volume applications where automatic PC board insertion is desireable, such as circuit boards for computers, printers, telecommunications equipment, and consumer products. Their compatibility with automatic insertion equipment, low-profile and end stackable features represent the stat-of-the-art in power device packaging. G S D N-Channel MOSFET ORDERING INFORMATION Package HVMDIP IRFD113PbF SiHFD113-E3 Lead (Pb)-free ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltagea VDS 60 Gate-Source Voltage VGS ± 20 ID 0.8 IDM 6.4 Continuous Drain Current Pulsed Drain VGS at 10 V TC = 25 °C Currentb Linear Derating Factor UNIT V A 0.008 W/°C Inductive Current, Clamped L = 100 μH ILM 6.4 A Maximum Power Dissipation TC = 25 °C PD 1.0 W TJ, Tstg - 55 to + 150 Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) for 10 s 300c °C Notes a. TJ = 25 °C to 150 °C b. Repetitive rating; pulse width limited by maximum junction temperature. c. 1.6 mm from case. S11-2479-Rev. A, 19-Dec-11 1 Document Number: 91487 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFD113, SiHFD113 www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER Maximum Junction-to-Ambient SYMBOL TYP. MAX. UNIT RthJA - 120 °C/W SPECIFICATIONS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current On-State Drain Currentb Drain-Source On-State Resistanceb Forward Transconductanceb VDS VGS = 0 V, ID = 250 μA 60 - - VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 IGSS IDSS VGS = ± 20 V - - ± 500 VDS = max. rating, VGS = 0 V - - 250 VDS = max. rating x 0.8, VGS = 0 V, TC = 125 °C - - 1000 V nA μA ID(on) VGS = 10 V VDS > ID(on) x RDS(on) max. 0.8 - - A RDS(on) VGS = 10 V ID = 0.8 A - 0.6 0.8 Ω S gfs VDS > ID(on) x RDS(on) max., ID = 0.8 A 0.8 1.2 - Input Capacitance Ciss 135 200 Coss - 80 100 Reverse Transfer Capacitance Crss VGS = 0 V, VDS = 25 V, f = 1.0 MHz - Output Capacitance - 20 25 - 5 7 - 2 - Dynamic Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) Rise Time Turn-Off Delay Time tr td(off) Fall Time tf Internal Drain Inductance LD Internal Source Inductance LS VGS = 10 V ID = 4 A, VDS = 0.8 max. rating VDD = 0.5 VDS , ID = 0.8 A, Rg = 50 Ω Between lead, 2 mm (0.08") from package and center of die contact D G - 7 - - 10 20 pF nC - 15 25 - 15 25 - 10 20 - 4.0 - - 6.0 - - - 0.8 - - 6.4 - - 2 - 100 - ns - 0.2 - μC ns nH S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Current Body Diode Voltagea IS ISM VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G S TA = 25 °C, IS = 0.8 A, VGS = 0 V TJ = 150 °C, IF = 1.0 A, dI/dt = 100 A/μs V Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %. S11-2479-Rev. A, 19-Dec-11 2 Document Number: 91487 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFD113, SiHFD113 www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Fig. 1 - Typical Output Characteristics Fig. 3 - Typical Saturation Characteristics Fig. 2 - Typical Transfer Characteristics Fig. 4 - Maximum Safe Operatung Area S11-2479-Rev. A, 19-Dec-11 3 Document Number: 91487 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFD113, SiHFD113 www.vishay.com Vishay Siliconix Fig. 5 - Typical Transconductance vs. Drain Current Fig. 7 - Breakdown Voltage vs. Temperature Fig. 6 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Normalized On-Resistance vs. Temperature S11-2479-Rev. A, 19-Dec-11 4 Document Number: 91487 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFD113, SiHFD113 www.vishay.com Vishay Siliconix Fig. 9 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 11 - Typical On-Resistance vs. Darin Current Fig. 10 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 12 - Maximum Darin Current vs. Case Temperature S11-2479-Rev. A, 19-Dec-11 5 Document Number: 91487 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFD113, SiHFD113 www.vishay.com Vishay Siliconix Fig. 17 - Gate Charge Test Circuit Fig. 13 - Power vs. Temperature Derating Fig. 14 - Clamped Inductive Test Circuit EC IP VDS Fig. 18 - Typical Time to Accumulated 1 % Gate Failure IL VDD Fig. 15 - Clamped Inductive Waveforms Fig. 16 - Switching Time Test Circuit Fig. 19 - Typical High Temperature Reverse Bias (HTRB) Failure Rate S11-2479-Rev. A, 19-Dec-11 6 Document Number: 91487 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFD113, SiHFD113 www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop ISD Ripple ≤ 5 % Note a. VGS = 5 V for logic level devices Fig. 20 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91487. S11-2479-Rev. A, 19-Dec-11 7 Document Number: 91487 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000