DATA SHEET Part No. AN12978A Package Code No. UBGA015-W-2020 Publication date: October 2008 SDE00030BEB 1 AN12978A Contents Overview ……..……………………………………………………………………………………………………. 3 Features ……..……………………………………………………………………………………………………. 3 Applications Package Type ………………………………………………………………………………………………………. 3 …………………………………...………………………………………………………………………. 3 …………….………………………………………………………………………………………………… 3 Application Circuit Example (Block Diagram) ……….…………………………………………………………. 4 Pin Descriptions …………………..………………………………………………………………………………. 5 Absolute Maximum Ratings ……………………..……………..…………………………......………………… 6 Operating Supply Voltage Range …………………………………………..……………………………………. 6 Electrical Characteristics ………………….………………….…………………………………………………. 7 Electrical Characteristics (Reference values for design) Technical Data Usage Notes ……………………………………………………. 9 …………………………………….………….…………………………………………………. 10 ……….……………………….………………….…………………………………………………. 20 SDE00030BEB 2 AN12978A AN12978A Monaural BTL amplifier IC with built-in AGC (I2C bus-control correspondence) Overview AN12978A is the monaural BTL amplifier which contained the AGC circuit for clip prevention of a speaker output. This IC performs a mode change by the I2C bus control system. (Standby function ON/OFF change etc.) Features y Selection by I2C bus control is possible in the on-level of AGC. (3-bit, 8-step) y Selection by I2C bus control is possible in an attack/recovery time of AGC. (attack: 2-bit , recovery: 3-bit) yThe resistance and the capacitor of a detector circuit which were being used for the conventional AGC are unnecessary. y In order to realize high efficiency of output power, it adopts CMOS power amplifier circuit. y Built-in shutdown function. y Built-in Gv-Switch. Applications y Audio amplifier for mobile, such as a cellular phone Package y 15 pin Wafer level chip size package (WLCSP) Size: 2.0 mm × 2.0 mm (0.5 mm pitch) Type y Bi-CMOS IC SDE00030BEB 3 AN12978A Application Circuit Example (Block Diagram) VCC = 3 V Speaker 8 Ω Shutdown Operate VCCD 1 μF 1 μF OUT_NEG VREFSP SD 8 9 10 11 +14 dB GNDSP 12 1 μF 7 OUT_POS 13 VCCSP = 3 V VCCD = 1.8 V +14dB I2C-BUS Control DET 2.2 kΩ 6 SDA 14 AGC 1 μF 2.2 kΩ 5 SCL +3 dB/+6 dB GND 15 1 VREF 1 μF 2 PREOUT 4 3 100 pF 10 kΩ FB GND 10 kΩ 0.1 μF INPUT Note) 1. This circuit and these circuit constants show an example and do not guarantee the design as a mass-production set. 2. The threshold voltage at 8pin has the VCCD dependency. SDE00030BEB 4 AN12978A Pin Descriptions Pin No. Pin name Type Description 1 VREF Output Reference Voltage Output 2 PREOUT Output Pre-amplifier Output 3 FB 4 GND Ground 5 SCL Input SCL Input on I2C-bus Control 6 SDA Input / Output SDA Input on I2C-bus Control 7 VCCD Power Supply Power supply for logic circuit 8 SD 9 VCC 10 VREFSP Output Reference Voltage Output for Speaker Amplifier 11 OUT_NEG Output Speaker Output (Negative Phase) 12 GNDSP Ground Ground for Speaker Amplifier 13 OUT_POS Output Speaker Output (Positive Phase) 14 VCCSP 15 GND Input Input Power Supply Power Supply Ground Pre-amplifier Negative Feedback Input Ground Shutdown Control Power supply Power supply for Speaker Amplifier Ground SDE00030BEB 5 AN12978A Absolute Maximum Ratings A No. 1 Parameter Supply voltage Symbol Rating VCC 5.5 VCCD 3.6 VCCSP 5.5 Unit Note V *1 2 Supply current ICC — A 3 Power dissipation PD 120 mW *2 4 Operating ambient temperature Topr –20 to +70 °C *3 5 Storage temperature Tstg –55 to +150 °C *3 Note) *1: The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2: The power dissipation shown is the value at Ta = 70°C for the independent (unmounted) IC package without a heat sink. When using this IC, refer to the • PD – Ta diagram in the Technical Data and use under the condition not exceeding the allowable value. *3: Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta = 25°C. Operating Supply Voltage Range Parameter Supply voltage range Symbol Range VCC 2.7 to 4.5 1.7 to 2.6 VCCD 1.7 to 3.3 VCCSP Unit V Note *1 *2 2.7 to 4.5 Note) 1. The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. 2. *1: The values under Fast mode. *2: The values under Standard mode. SDE00030BEB 6 AN12978A Electrical Characteristics at VCC = 3.0 V , VCCD = 1.8 V , VCCSP = 3.0 V Note) Ta = 25°C±2°C unless otherwise specified. B No. Parameter Symbol Conditions Limits Min Typ Max Unit No te Circuit Current 1 Circuit current at non-signal 1 (VCC) IVCC1A VCC = 3.0V, Non-signal STB = OFF, SP = ON, AGC = ON 0.5 2.4 4.5 mA 2 Circuit current at non-signal 2 (VCCSP) IVCC2A VCCSP = 3.0V, Non-signal STB = OFF, SP = ON, AGC = ON 1.0 6.5 15.5 mA 3 Circuit current at non-signal 3 (VCCD) IVCC3A VCCD = 1.8V, Non-signal STB = OFF, SP = ON, AGC = ON ⎯ 0.1 10 μA 4 Circuit current at standby mode 1 (VCC) IVCC1B VCC = 3.0V, Non-signal STB = ON, SP = OFF, AGC = ON ⎯ 0.1 1.0 μA 5 Circuit current at standby mode 2 (VCCSP) IVCC2B VCCSP = 3.0V, Non-signal STB = ON, SP = OFF, AGC = ON ⎯ 0.1 1.0 μA 6 Circuit current at standby mode 3 (VCCD) IVCC3B VCCD = 1.8V, Non-signal STB = ON, SP = OFF, AGC = ON ⎯ 0.1 1.0 μA 7 Circuit current at speaker save mode 1 (VCC) IVCC1C VCC = 3.0 V, Non-signal STB = OFF, SP = OFF, AGC = ON 0.5 2.4 4.5 mA 8 Circuit current at speaker save mode 2 (VCCSP) IVCC2C VCCSP = 3.0 V, Non-signal STB = OFF, SP = OFF, AGC = ON ⎯ 0.3 1.0 mA 9 Circuit current at speaker save mode 3 (VCCD) IVCC3C VCCD = 1.8 V, Non-signal STB = OFF, SP = OFF, AGC = ON ⎯ 0.1 10 μA Input/output characteristics VSPO Vin = –31.0 dBV , f = 1 kHz RL = 8 Ω, GAIN = +23 dB –9.5 –8.0 –6.5 dBV 12 SP reference output distortion THSPO Vin = –31.0 dBV, f = 1 kHz RL = 8 Ω, GAIN = +23dB to THD5th ⎯ 0.07 0.5 % 13 SP output noise voltage VNSPO Non-Signal using A curve filter GAIN = +23 Db ⎯ –78 –71 dBV 14 SP maximum rating output VMSPO THD = 10%, f = 1 kHz RL = 8Ω, AGC = OFF 300 500 ⎯ mW 15 SP output level at power save VSSPO Vin = –31.0 dBV, f = 1 kHz RL = 8 Ω, GAIN = +23 dB using A curve filter ⎯ –114 –90 dBV 16 SP AGC output level 1 Vin = –17.0 dBV, f = 1 kHz VSPOA1 RL = 8 Ω, GAIN = +23 dB AGC-Level = 4 dBV 3.0 4.0 5.0 dBV 17 SP AGC output level 2 Vin = –12.0 dBV, f = 1 kHz VSPOA2 RL = 8 Ω, GAIN = +23 dB AGC-Level = 4 dBV 3.0 4.0 5.0 dBV 11 SP reference output level SDE00030BEB 7 AN12978A Electrical Characteristics at VCC = 3.0 V , VCCD = 1.8 V , VCCSP = 3.0 V (continued) Note) Ta = 25°C±2°C unless otherwise specified. B No. Parameter Symbol Conditions 43 SCL, SDA signal input Low Level VIL 44 SCL, SDA signal input Low Level Limits Unit Min Typ Max ⎯ – 0.5 ⎯ 0.3 × VCCD V VIH ⎯ 0.7 × VCCD ⎯ VCCD + 0.5 V 45 SDA output signal Low Level VOL Open corrector Sync current: 3 mA 0 ⎯ 0.2 × VCCD V 46 SCL,SDA Signal Input Current Ii –10 ⎯ 10 μA No te I2C interface SCL maximum frequency of signal input Input voltage: 0.1 V to 1.7 V fSCL ⎯ 0 ⎯ 400 kHz 48 SD input Low Level Vresetlth ⎯ ⎯ ⎯ 0.1 × VCCD V 49 SD input High Level Vresethth ⎯ 0.9 × VCCD ⎯ ⎯ V 47 The threshold voltage at 8-pin SDE00030BEB 8 AN12978A Electrical Characteristics (Reference values for design) at VCC = 3.0 V , VCCD = 1.8 V , VCCSP = 3.0 V Note) Ta = 25°C±2°C unless otherwise specified. The characteristics listed below are reference values derived from the design of the IC and are not guaranteed by inspection. If a problem does occur related to these characteristics, we will respond in good faith to user concerns. B No. Parameter Symbol Conditions tBUF Limits Unit No te ⎯ μs *1 Min Typ Max ⎯ 1.3 ⎯ I2C interface 66 Bass free time between a condition of stop and a condition of start 67 Setup time of a condition of start tSU;STA ⎯ 0.6 ⎯ ⎯ μs *1 68 Hold time of a condition for start tHD;STA ⎯ 0.6 ⎯ ⎯ μs *1 69 "L" time of SCL clock tLow ⎯ 1.3 ⎯ ⎯ μs *1 70 "H" time of SCL clock tHigh ⎯ 0.6 ⎯ ⎯ μs *1 71 Rising time of SDA, SCL signal tR ⎯ ⎯ ⎯ 0.3 μs *1 72 Fall time of SDA,SCL signal tF ⎯ ⎯ ⎯ 0.3 μs *1 73 Data setup time tSU;DAT ⎯ 0.1 ⎯ ⎯ μs *1 74 Data hold time tHD;DAT ⎯ 0 ⎯ 0.9 μs *1 75 Rising up time of a condition of stop tSU;STO ⎯ 0.6 ⎯ ⎯ μs *1 Note) *1: All values are VIHmin (*2) and VILmax (*3) level standard. *2: VIHmin is the minimum limit of the signal input high level. *3: VILmax is the maximum limit of the signal input low level. Repeated START CONDITION START CONDITION STOP CONDITION START CONDITION VIHmin (*2) SDA VILmax (*3) tBUF tR tF tLow tR tSU;DAT tF tHD;STA SCL tHD;STA tHD;DAT tHigh tSU;STA SDE00030BEB tSU;STO 9 AN12978A Technical Data y I2C-bus Mode 1. Write Mode SDA SCL SLAVE ADDRESS START CONDITION ACK 1 0 1 1 0 1 1 0 B 6 SUB ADDRESS 0 0 0 0 DATA ACK 0 0 0 1 0 1 Example of transmission messages ACK 1 0 0 0 0 0 0 0 8 0 STOP CONDITION Two transmission messages (i.e., the SCL and SDA) are sent in synchronous serial transmission. The SCL is a clock with fixed frequency. The SDA indicates address data for the control of the reception side, and is sent in parallel in synchronization with the SCL. The data is transmitted in 8-bit, 3 octets (bytes) in principle, where every octet has an acknowledge bit. The following description provides information on the structure of the frame. <Start Conditions> When the level of the SDA changes to low from high while the level of the SCL is high, the data reception of the receiver will be enabled. <Stop Conditions> When the level of the SDA changes to high from low while the level of the SCL is high, the data reception of the receiver will be aborted. <Slave Address> The slave address is a specified one unique to each device. When the address of another device is sent, the reception will be aborted. <Sub Address> The sub address is a specified one unique to each function. <Data> Data is information under control. <Acknowledge Bit> The acknowledge bit is used to enable the master to acknowledge the reception of data for each octet. The master acknowledges the data reception of the receiver by transmitting a high-level signal to the receiver and receiving a low-level signal returned from the receiver as shown by the dotted lines in Fig. The communication will be aborted if the low signal is not returned. The SDA will not change when the level of the SCL is high except start or stop conditions are enabled. SDE00030BEB 10 AN12978A Technical Data (continued) y I2C-bus Mode (continued) 1. Write Mode (continued) (a) I2C-bus PROTOCOL x Slave address: 10110110 (B6Hex) x Format (normal) S Slave address W A Start condition Sub address A Data byte Acknowledge bit Write Mode: 0 A P Stop condition (b) Auto increment x Sub-address 0*Hex: Auto increment mode (When the data is sent in sequence, the sub address will change one by one and the data will be input.) x Auto increment mode S Slave address W A Sub address A Data 1 A Data 2 A Data n A P (c) Initial condition The initial state of the device is not guaranteed. Therefore, the input of 00Hex resister-D0 (Note.1) will be absolutely 0, when the power is turned ON. (d) Sub-address Byte and Data Byte Format Sub-address Data byte MSB D3 LSB D2 D5 D4 *0Hex AGC-ON GAIN VCCSP 0 → +23dB dependence 1 → +26dB 0 → OFF 1 → ON 0 (Note.2) 0 (Note.2) *1Hex AGC-ON data bit3 AGC-ON data bit2 AGC-ON AGC-REC AGC-REC AGC-REC AGC-ATT AGC-ATT data bit1 data bit3 data bit2 data bit1 data bit2 data bit1 *2Hex 0 (Note.2) 0 (Note.2) D7 D6 0 (Note.2) ＊ <00Hex Register> D0, D4, D5: Always set to 0 0 D1: Standby ON/OFF switch (Note.2) D2: SP Save ON/OFF switch D3: AGC ON/OFF switch D6: AGC-ON VCCSP dependence ON/OFF selection D7: GAIN +17 dB/+20 dB selection <01Hex Register> D0, D1 : AGC-attack-time selection D2, D3,D4: AGC-recovery-time selection D5,D6,D7: AGC-on-level selection <02Hex Register> D0 to D7: Always set to 0 (test & adjust mode) SDE00030BEB AGC 0 → OFF 1 → ON ＊ SP Save 0 → ON 1 → OFF 0 (Note.2) D1 Standby 0 → ON 1 → OFF 0 (Note.2) D0 0 (Note.1) 0 (Note.2) Please use these bit only Data = “0”, because they are used by our company’s final test and fine-tuning AGC-on level. 11 AN12978A Technical Data (continued) y I2C-bus Mode (continued) 1. Write Mode (continued) (e) AGC-attack-time selection Write 01Hex Register (f) AGC-recovery-time selection Write 01Hex Register Attack time Recovery time D4 D3 D2 0.5 ms 0 0 0 1.0 s 1 1 ms 0 0 1 1.5 s 1 0 2 ms 0 1 0 2.0 s 1 1 4 ms 0 1 1 3.0 s 1 0 0 4.0 s 1 0 1 6.0 s 1 1 0 8.0 s 1 1 1 12.0 s D1 D0 0 0 0 (g) AGC-on-level selection (at VCC = 3.0 V, VCCSP = 3.0 V) Write 01Hex Register AGC On Level Output Po ( RL = 8W ) VCCSP (推奨値) D7 D6 D5 0 0 0 1 dBV 157 mW — 0 0 1 2 dBV 198 mW — 0 1 0 3 dBV 249 mW — 0 1 1 4 dBV 314 mW 3.0 V ≤ 1 0 0 5 dBV 395 mW 3.3 V ≤ 1 0 1 6 dBV 498 mW 3.7 V ≤ 1 1 0 7 dBV 626 mW 4.1 V ≤ 1 1 1 8 dBV 789 mW 4.5 V (h) AGC-on-level VCCSP dependence mode (at AGC On Level = 4 dBV) AGC ON level increases by 0.75 dBV with each 0.3 V increase of VCCSP, and baseline of VCCSP is 3.0 V at AGC-onlevel VCCSP dependence mode. When VCCSP is 3.0 V, AGC ON level is set according to table (g). VCCSP AGC On Level Output Po ( RL = 8 Ω) VCCSP AGC On Level Output Po ( RL = 8 Ω) 2.7 V 3.25 dBV 264 mW 3.9 V 6.25 dBV 527 mW 3.0 V 4 dBV 314 mW 4.2 V 7 dBV 626 mW 3.3 V 4.75 dBV 373 mW 4.5 V 7.75 dBV 745 mW 3.6 V 5.5 dBV 444 mW SDE00030BEB 12 AN12978A Technical Data (continued) y I2C-bus Mode (continued) 2. Read Mode (a) I2C-bus PROTOCOL x Slave address 10110111(B7Hex) x Format S Slave address R A Data 0 A Data 1 A Data 2 A P Read Mode: 1 Note) At the slave address input, it is sequentially output from data 0. There is no necessity for inputting the sub-address. (b) Sub-address Byte and Data Byte Format Data byte MSB D7 D6 D4 D5 LSB D3 D2 D1 D0 Data 0 Sub address Sub address Sub address Sub address Sub address Sub address Sub address Sub address *0Hex *0Hex *0Hex *0Hex *0Hex *0Hex *0Hex *0Hex Latch data Latch data Latch data Latch data Latch data Latch data Latch data Latch data [D0] [D1] [D2] [D3] [D4] [D5] [D6] [D7] Data 1 Sub address Sub address Sub address Sub address Sub address Sub address Sub address Sub address *1Hex *1Hex *1Hex *1Hex *1Hex *1Hex *1Hex *1Hex Latch data Latch data Latch data Latch data Latch data Latch data Latch data Latch data [D0] [D1] [D2] [D3] [D4] [D5] [D6] [D7] Data 2 Sub address Sub address Sub address Sub address Sub address Sub address Sub address Sub address *2Hex *2Hex *2Hex *2Hex *2Hex *2Hex *2Hex *2Hex Latch data Latch data Latch data Latch data Latch data Latch data Latch data Latch data [D2] [D3] [D4] [D5] [D6] [D7] [D1] [D0] yOperating temperature guarantee of I2C-bus Control The performance in the ambient temperature of operation is guaranteed theoretically in the design at normal temperature (25°C) by inspecting it at a speed of the clock that is about 50% earlier regarding the operating temperature guarantee of I2C-bus Control. But the following characteristics are logical values derived from the design of the IC and are not guaranteed by inspection. If a problem does occur related to these characteristics, Panasonic will respond in good faith to customer concerns. y Usage note of I2C bus x The I2C bus of this product is designed to correspond to Standard mode (100 Kbps) and Fast mode (400 Kbps) in Philips Corporation I2C specification version 2.1. However, not correspond to High Speed mode (to 3.4 Mbps). x This product operate as a slave device in I2C bus system. x This product is not confirm to operate in multi-master bus system and mixing -speed bus system. And this product is not confirm connectivity to CBUS receiver. If using this product in these mode, please confirm availability to our company. x Purchase of Panasonic I2C components conveys a license to use these components in an I2C systems under the Philips I2C patent right on condition that using condition conform to I2C standard specification approved by Philips Corporation. SDE00030BEB 13 AN12978A Technical Data (continued) y I/O block circuit diagrams and pin function descriptions Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Waveform and voltage Internal circuit Description VCC 10k VREF 1 Reference Voltage Output 1k 150k DC 1.45 V 150k VCC PREOUT 2 Pre-amplifier Output DC 1.45 V FB 500 10k Pre-amplifier Negative Feedback Input 3 DC 1.45 V 4 GND － SDE00030BEB Ground 14 AN12978A Technical Data (continued) y I/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Waveform and voltage Internal circuit Description VCCD SCL 5 SCL Input on I2C-Bus Control Hi-Z VCCD SDA SDA Input on I2C-Bus Control 6 Hi-Z GND VCCD 7 － Power Supply for Logic Circuit 1.8 V(typ.) VCCD Shutdown Control SD 8 Shutdown mode is shorted to GND. (All data becomes 0.) Connect VCCD to VCC 1.8 V to 3.0 V SDE00030BEB 15 AN12978A Technical Data (continued) y I/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Waveform and voltage Internal circuit Description － Power Supply VCC 9 3.0 V(typ.) VCC VREFSP 10 3.0 V(typ.) 10k 1k 150k Reference Voltage Output for Speaker Amplifier 150k VCCSP OUT_NEG Speaker Output (Negative Phase) 11 DC 1.45 V 400k GNDSP 12 GNDSP — SDE00030BEB Ground for Speaker Amplifier 16 AN12978A Technical Data (continued) y I/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Waveform and voltage Internal circuit Description VCCSP OUT_POS Speaker Output (Positive Phase) 13 DC 1.45 V 400k GNDSP VCCSP 14 － Power Supply for Speaker Amplifier － Ground 3.0 V(typ.) 15 GND SDE00030BEB 17 AN12978A Technical Data (continued) y Power supply and logic sequence Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. The timing control of power-ON/OFF and each logic according to the procedure below should be recommended for the best pop performance caused in switching. 1. The sequence of the power supply and each logic The basic procedure at the power-on Please first bring up the power supply, and then the standby off. VCC,VCCSP, VCCD Power supply Off On On Off Off Standby 1. The power OFF condition Both the standby and the SP_Save are in the ON condition. 2. Power ON 3. Standby Off 4. SP_Save Off Off On On Off Off SP_Save The basic procedure at the power-off On On 20 ms or more * After at least 20 ms has passed after the standby off, please off SP_Save. 0 ms or more 1. The power ON condition Both the standby and the SP_Save are in the OFF condition. 2. SP_Save On ( = Standby On) 3. Standby On 4. Power Off Please control Standby On to simultaneous with SP_Save On, or the back. Note) *: This IC contains the pre-charge circuit. It is time until each bias is stabilized from Standby Off. It depends for this time on the capacity value linked to a reference voltage terminal (VREF and VREFSP), and the capacity value and resistance linked to an input terminal (IN). It is a recommendation value in a constant given in the example of Application Circuit Example (Block Diagram). 2．The sequence of VCC and VCCSP and VCCD This IC have not a standup and falling order in VCC and VCCSP. A standup and falling time of VCC and VCCSP recommend 1 or more ms. VCC VCCSP VCCD On On Off Off 1 ms or more 1 ms or more SDE00030BEB 18 AN12978A Technical Data (continued) y PD ⎯ Ta diagram SDE00030BEB 19 AN12978A Usage Notes 1. Please take notice in the use of this product that it might break or occasionally smoke when an abnormal state occurs such as SP output pin (Pin11, Pin13) – power supply pin short, SP output pin (Pin11, Pin13) – GND short, or SP output (Pin11, Pin13) -to-SP output-pin short (load short). 2. Please absolutely do not mount the IC in the reverse direction on to the printed-circuit-board. It damaged when the electricity is turned on. 3. Please do not make it open, because the open SD-pin (Pin8) is not fixed. SDE00030BEB 20 Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. (3) The products described in this book are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: – Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. – Any applications other than the standard applications intended. (4) The products and product specifications described in this book are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company. 20080805