DATASHEET

ACTS74MS
TM
Radiation Hardened Dual D
Flip Flop with Set and Reset
January 1996
Features
Pinouts
• Devices QML Qualified in Accordance with MIL-PRFF-38535
itle
CTS
MS)
bt
adian
rded
al D
p
p
th
t and
set)
thor
eyrds
terminctor,
dian
rded,
,
d
rd,
L,
tel,
D,
ass
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96713 and Intersil’s QM Plan
14 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR CDIP2-T14,
LEAD FINISH C
TOP VIEW
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day
(Typ)
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg
• Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse
• Dose Rate Survivability . . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse
R1 1
14 VCC
D1 2
13 R2
CP1 3
12 D2
S1 4
11 CP2
Q1 5
10 S2
Q1 6
9 Q2
GND 7
8 Q2
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current ≤ 1µA at VOL, VOH
• Fast Propagation Delay . . . . . . . . . . . . . . . . 20ns (Max), 13ns (Typ)
Description
14 PIN CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR CDFP3-F14,
LEAD FINISH C
TOP VIEW
R1
1
14
D1
2
13
R2
VCC
CP1
3
12
D2
S1
4
11
CP2
Q1
5
10
S2
Q1
6
9
Q2
GND
7
8
Q2
The Intersil ACTS74MS is a Radiation Hardened Dual D Flip Flop with
Set(s) and Reset (R). The logic level at data input is transferred to the
output during the positive transition of the clock. The Set and Reset are
independent from the clock and accomplished by a low level on the
appropriate input.
The ACTS74MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic Family.
The ACTS74MS is supplied in a 14 lead Ceramic Flatpack (K suffix) or a
14 Lead Ceramic Dual-In-Line Package (D suffix).
Ordering Information
PART NUMBER
TEMPERATURE RANGE
o
o
SCREENING LEVEL
PACKAGE
5962F9671301VCC
-55 C to +125 C
MIL-PRF-38535 Class V
14 Lead SBDIP
5962F9671301VXC
-55oC
to
+125oC
MIL-PRF-38535 Class V
14 Lead Ceramic Flatpack
ACTS74D/Sample
o
25 C
Sample
14 Lead SBDIP
ACTS74K/Sample
25oC
Sample
14 Lead Ceramic Flatpack
ACTS74HMSR
25oC
Die
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, All Rights Reserved
1
Spec Number
File Number
518787
3382.1
ACTS74MS
Functional Diagram
S
CL
4(10)
P
N
CL
D
2(12)
CL
P
N
CL
CL
P
N
CL
CL
P
N
Q
CL
R
6(8)
1(13)
Q
Cp
5(9)
3(11)
CL
CL
TRUTH TABLE
INPUTS
OUTPUTS
SET
RESET
CP
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
H
H
L
H
H
L
L
H
H
H
X
Q0
Q0
L
H = High Level (Steady State)
L = Low Level (Steady State)
H (Note 2) H (Note 2)
X = Don’t Care
= Transition from Low to
High Level
NOTES:
1. Q0 = the level of Q before the indicated input conditions were established.
2. This configuration is nonstable, that is, it will not persist when set
and reset inputs return to their inactive (high) level.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number
2
518787
ACTS74MS
Die Characteristics
DIE DIMENSIONS:
88 mils x 88 mils
2240mm x 2240mm
METALLIZATION:
Type: AlSi
Metal 1 Thickness: 7.125kÅ ±1.125kÅ
Metal 2 Thickness: 9kÅ ±1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
<2.0 x 105A/cm2
BOND PAD SIZE:
110µm x 110µm
4.3 mils x 4.3 mils
Metallization Mask Layout
ACTS74MS
D1
(2)
R1
(1)
VCC
(14)
R2
(13)
CP1 (3)
(12) D2
S1 (4)
(11) CP2
Q1 (5)
(10) S2
NC
NC
(6)
Q1
(7)
GND
(8)
Q2
(9)
Q2
Spec Number
3
518787
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