DATASHEET

CD4014BMS,
CD4021BMS
CMOS 8-Stage Static Shift Registers
December 1992
Features
Description
• High Voltage Types (20V Rating)
CD4014BMS -Synchronous Parallel or Serial Input/Serial Output
• Medium Speed Operation 12MHz (Typ.) Clock Rate at
VDD-VSS = 10V
CD4021BMS -Asynchronous Parallel Input or Synchronous
Serial Input/Serial Output
• Fully Static Operation
CD4014BMS and CD4021BMS series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK
and PARALLEL/SERIAL CONTROL inputs, a single SERIAL
data input, and individual parallel “JAM” inputs to each register
stage. Each register stage is a D-type, master-slave flip-flop. In
addition to an output from stage 8, “Q” outputs are also available
from stages 6 and 7. Parallel as well as serial entry is made into
the register synchronously with the positive clock line transition in
the CD4014BMS. In the CD4021BMS serial entry is synchronous with the clock but parallel entry is asynchronous. In both
types, entry is controlled by the PARALLEL/SERIAL CONTROL
input. When the PARALLEL/SERIAL CONTROL input is low,
data is serially shifted into the 8-stage register synchronously
with the positive transition of the clock line. When the PARALLEL/
SERIAL CONTROL input is high, data is jammed into the 8stage register via the parallel input lines and synchronous with
the positive transition of the clock line. In the CD4021BMS, the
CLOCK input of the internal stage is “forced” when asynchronous parallel entry is made. Register expansion using multiple
packages is permitted.
• 8 Master-Slave Flip-Flops Plus Output Buffering and
Control Gating
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Full Package Temperature Range)
• 1V at VDD = 5V
• 2V at VDD = 10V
• 2.5V at VDD = 15V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
`B' Series CMOS Devices
Applications:
The CD4014BMS and CD4021BMS are supplied in these 16
lead outline packages:
• Parallel Input/Serial Output Data Queueing
Braze Seal DIP
• Parallel to Serial Data Conversion
Frit Seal DIP
H1F
• General Purpose Register
Ceramic Flatpack
H6W
Pinout
Functional Diagram
16 VDD
Q6 2
15 PI-7
Q8 3
14 PI-6
PI-4 4
13 PI-5
PI-3 5
12 Q7
PI-2 6
11 SERIAL IN
PI-1 7
10 CLOCK
PAR. IN
1 2 3 4 5 6 7 8
7 6 5 4 13 14 15 1
PARALLEL/SERIAL
CONTROL
SERIAL IN
VSS 8
VDD
9 PARALLEL/SERIAL
CONTROL
CLOCK
16
9
11
10
2
12
3
Q6
Q7
BUFFERED
OUT
PI-8 1
H4T
Q8
8
VSS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-80
File Number
3294
Specifications CD4014BMS, CD4021BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . .
θja
θjc
Ceramic DIP and FRIT Package . . . . . 80oC/W
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
o
Maximum Package Power Dissipation (PD) at +125 C
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS (NOTE 1)
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
VDD = 18V
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 20
GROUP A
SUBGROUPS
LIMITS
TEMPERATURE
MIN
+25
-
10
µA
+125oC
-
1000
µA
3
-55oC
-
10
µA
1
+25o
C
-100
-
nA
2
+125oC
-1000
-
nA
3
-55oC
-100
-
nA
1
+25oC
-
100
nA
2
+125oC
-
1000
nA
-
100
nA
-
50
mV
-
V
3
Output Voltage
VOL15
VDD = 15V, No Load
1, 2, 3
+25oC, +125oC, -55oC
Output Voltage
VOH15
VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, -55oC 14.95
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
UNITS
1
-55oC
VDD = 18V
MAX
2
oC
1
+25oC
0.53
-
mA
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1
+25oC
1.4
-
mA
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1
+25oC
3.5
-
mA
1
+25oC
-
-0.53
mA
1
+25oC
-
-1.8
mA
Output Current (Source)
Output Current (Source)
IOH5A
IOH5B
VDD = 5V, VOUT = 4.6V
VDD = 5V, VOUT = 2.5V
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1
+25oC
-
-1.4
mA
Output Current (Source)
IOH15
VDD = 15V, VOUT = 13.5V
1
+25oC
-
-3.5
mA
1
+25oC
-2.8
-0.7
V
1
+25oC
0.7
2.8
V
N Threshold Voltage
P Threshold Voltage
Functional
VNTH
VPTH
F
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
VDD = 2.8V, VIN = VDD or GND
7
+25oC
VDD = 20V, VIN = VDD or GND
7
+25oC
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
VOH > VOL <
VDD/2 VDD/2
V
Input Voltage Low
(Note 2)
VIL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
-
1.5
V
Input Voltage High
(Note 2)
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
3.5
-
V
Input Voltage Low
(Note 2)
VIL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
-
4
V
Input Voltage High
(Note 2)
VIH
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
11
-
V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
7-81
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
Specifications CD4014BMS, CD4021BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Propagation Delay
Transition Time
Maximum Clock Input
Frequency
SYMBOL
TPHL
TPLH
CONDITIONS (NOTE 1, 2)
GROUP A
SUBGROUPS TEMPERATURE
VDD = 5V, VIN = VDD or GND
9
10, 11
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
FCL
VDD = 5V, VIN = VDD or GND
9
10, 11
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
LIMITS
MIN
MAX
UNITS
-
320
ns
-
432
ns
-
200
ns
-
270
ns
9
+25oC
3
-
MHz
10, 11
+125oC, -55oC
2.22
-
MHz
MIN
MAX
UNITS
µA
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
VDD = 5V, VIN = VDD or GND
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
Output Voltage
VOL
VDD = 5V, No Load
1, 2
1, 2
1, 2
1, 2
TEMPERATURE
-55oC,
+25oC
-
5
+125oC
-
150
µA
-55oC, +25oC
-
10
µA
+125oC
-
300
µA
-
10
µA
+125oC
-
600
µA
+25oC, +125oC,
-
50
mV
-55oC,
+25oC
-55oC
Output Voltage
VOL
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
-
50
mV
Output Voltage
VOH
VDD = 5V, No Load
1, 2
+25oC, +125oC,
-55oC
4.95
-
V
Output Voltage
VOH
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
9.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1, 2
+125oC
0.36
-
mA
-55oC
0.64
-
mA
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Input Voltage Low
IOL10
IOL15
IOH5A
IOH5B
IOH10
IOH15
VIL
VDD = 10V, VOUT = 0.5V
1, 2
VDD = 15V, VOUT = 1.5V
1, 2
VDD = 5V, VOUT = 4.6V
1, 2
VDD = 5V, VOUT = 2.5V
1, 2
VDD = 10V, VOUT = 9.5V
1, 2
VDD =15V, VOUT = 13.5V
1, 2
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+125oC
0.9
-
mA
-55oC
1.6
-
mA
+125oC
2.4
-
mA
-55oC
4.2
-
mA
+125oC
-
-0.36
mA
-55oC
-
-0.64
mA
+125oC
-
-1.15
mA
-55oC
-
-2.0
mA
+125oC
-
-0.9
mA
-55oC
-
-1.6
mA
+125oC
-
-2.4
mA
-55oC
-
-4.2
mA
+25oC, +125oC,
-
3
V
7
-
V
-55oC
Input Voltage High
VIH
VDD = 10V, VOH > 9V, VOL < 1V
7-82
1, 2
+25oC, +125oC,
-55oC
Specifications CD4014BMS, CD4021BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
Propagation Delay
Transition Time
Maximum Clock Input
Frequency
Clock Rise and Fall Time
(Note 4)
Minimum Hold Time Serial In, Parallel In
Parallel/Serial Control
SYMBOL
TPHL
TPLH
TTHL
TTLH
FCL
TRCL
TFCL
TH
CONDITIONS
VDD = 10V
TW
TS
Minimum Setup Time
Parallel Inputs
CD4021BMS
(Ref. to P/S)
Minimum Setup Time
Parallel/Serial Control
CD4014BMS (Ref. to CL)
Minimum P/S Pulse
Width (CD4021BMS)
Minimum P/S Removal
Time CD4021BMS
(Ref. to CL)
Input Capacitance
TS
TWH
TREM
CIN
1, 2, 3
-
160
ns
o
+25 C
-
120
ns
+25oC
-
100
ns
1, 2, 3
+25
oC
-
80
ns
VDD = 10V
1, 2, 3
+25oC
6
-
MHz
VDD = 15V
1, 2, 3
+25oC
8.5
-
MHz
VDD = 5V
3, 5
+25oC
-
15
µs
VDD = 10V
3, 5
+25o
C
-
15
µs
VDD = 15V
3, 5
+25oC
-
15
µs
oC
-
0
ns
-
0
ns
1, 2, 3
o
+25 C
-
0
ns
VDD = 5V
1, 2, 3
+25o
C
-
180
ns
VDD = 10V
1, 2, 3
+25oC
-
80
ns
1, 2, 3
+25oC
-
50
ns
oC
-
120
ns
-
80
ns
2, 3
o
+25 C
-
60
ns
VDD = 5V
2, 3
+25
oC
-
80
ns
VDD = 10V
2, 3
+25oC
-
50
ns
2, 3
+25
oC
-
40
ns
VDD = 5V
2, 3
+25oC
-
50
ns
VDD = 10V
2, 3
+25oC
-
30
ns
2, 3
+25oC
-
20
ns
2, 3
+25oC
-
180
ns
VDD = 10V
2, 3
+25oC
-
80
ns
VDD = 15V
2, 3
+25oC
-
60
ns
2, 3
+25
oC
-
160
ns
VDD = 10V
2, 3
+25oC
-
80
ns
VDD = 15V
2, 3
+25oC
-
50
ns
2, 3
+25oC
-
280
ns
VDD = 10V
2, 3
+25oC
-
140
ns
VDD = 15V
2, 3
+25oC
-
100
ns
1, 2
+25oC
-
7.5
pF
VDD = 15V
VDD = 5V
1, 2, 3
+25
VDD = 10V
1, 2, 3
+25oC
VDD = 5V
2, 3
+25
VDD = 10V
2, 3
+25oC
VDD = 15V
TS
UNITS
1, 2, 3
VDD = 15V
TS
MAX
+25oC
1, 2, 3
VDD = 15V
Minimum Setup Time
Parallel Inputs
CD4014BMS
(Ref. to CL)
MIN
VDD = 15V
VDD = 15V
Minimum Setup Time
Serial Input (Ref. to CL)
TEMPERATURE
VDD = 10V
VDD = 15V
Minimum Clock Pulse
Width
NOTES
VDD = 5V
VDD = 5V
VDD = 5V
Any Input
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded, TRCL should be made less than or equal to the sum of the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
7-83
Specifications CD4014BMS, CD4021BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
Supply Current
IDD
CONDITIONS
NOTES
TEMPERATURE
VDD = 20V, VIN = VDD or GND
1, 4
+25oC
VDD = 10V, ISS = -10µA
1, 4
+25oC
VDD = 10V, ISS = -10µA
1, 4
+25oC
MIN
MAX
UNITS
-
25
µA
-2.8
-0.2
V
-
±1
V
N Threshold Voltage
VNTH
N Threshold Voltage
Delta
∆VNTH
P Threshold Voltage
VPTH
VSS = 0V, IDD = 10µA
1, 4
+25oC
0.2
2.8
V
P Threshold Voltage
Delta
∆VPTH
VSS = 0V, IDD = 10µA
1, 4
+25oC
-
±1
V
1
+25oC
VOH >
VDD/2
VOL <
VDD/2
V
1, 2, 3, 4
+25oC
-
1.35 x
+25oC
Limit
ns
Functional
F
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL
TPLH
VDD = 5V
3. See Table 2 for +25oC limit.
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETER
SYMBOL
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
DELTA LIMIT
IDD
± 1.0µA
IOL5
± 20% x Pre-Test Reading
IOH5A
± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
100% 5004
1, 7, 9, Deltas
100% 5004
1, 7, 9
CONFORMANCE GROUP
PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
Final Test
Group A
Group B
Subgroup B-5
Subgroup B-6
Group D
READ AND RECORD
IDD, IOL5, IOH5A
100% 5004
1, 7, 9, Deltas
100% 5004
2, 3, 8A, 8B, 10, 11
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Sample 5005
1, 7, 9
Sample 5005
1, 2, 3, 8A, 8B, 9
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
TEST
READ AND RECORD
MIL-STD-883
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
1, 9
Table 4
Group E Subgroup 2
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
Static Burn-In 1 (Note 1)
OPEN
GROUND
VDD
2, 3, 12
1,4-11, 13-15
16
7-84
9V ± -0.5V
50kHz
25kHz
Specifications CD4014BMS, CD4021BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS (Continued)
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
Static Burn-In 2 (Note 1)
2, 3, 12
8
1, 4-7, 9-11, 13-6
Dynamic Burn-In (Note 1)
-
1, 4-9, 13 -15
16
2, 3, 12
8
1, 4-7, 9-11, 13-16
Irradiation (Note 2)
9V ± -0.5V
50kHz
25kHz
2, 3, 12
10
11
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD =
10V ± 0.5V
Logic Diagram
P1
P2
P3
P4
P5
P6
P7
7
6
5
4
13
14
15
SERIAL
INPUT
*
*
P
P
11
D
*
Q
D
*
P
P
Q
D
*
Q
D
*
P
P
D
Q
*
Q
D
P8
1
*
P
P
Q
D
*
D
Q
Q
CLOCK
*
CL
10
PS
CL
CL
CL
PS
CL
PS
PS
CL
CL
CL
PS
PS
PS
PS
PARALLEL/SERIAL
CONTROL
*
9
P
p
P
D
CL
C
CL
n
Q
≡
CL
p
p
n
n
2
2
3
Q6
Q7
Q8
Q
CL
p
CL
CL
CL
D
PS
n
CL
CL
VDD
PS
p
p
n
n
CL
CL
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
VSS
FIGURE 1. CD4014BM LOGIC DIAGRAM
TRUTH TABLE - CD4014BMS
CL
SERIAL INPUT
PARALLEL/SERIAL CONTROL
PI-1
PI-n
Q1 (INTERNAL)
Qn
X
1
0
0
0
0
X
1
1
0
1
0
X
1
0
1
0
1
X
1
1
1
1
1
0
0
X
X
0
Qn-1
1
0
X
X
1
Qn-1
X
X
X
X
Q1
Qn
X = Don’t Care Case
NC = No Change
7-85
NC
CD4014BMS, CD4021BMS
SERIAL
INPUT
*
P1
P2
P3
P4
P5
P6
P7
7
6
5
4
13
14
15
*
P
P
11
D
*
D
Q
*
P
P
Q
D
*
D
Q
*
P
P
Q
D
*
D
Q
P8
1
*
P
P
Q
D
*
D
Q
Q
CLOCK
*
*
10
CL
CL
PS
CL
CL
PS
CL
CL
PS
PS
CL
CL
PS
PS
PS
PS
9
P
PARALLEL/
SERIAL
CONTROL
CL
CL
p
CL
CL
n
2
3
Q7
Q8
p
P
D
2
Q6
Q
Q
n
CL
≡
CL
CL
p
p
n
n
CL
CL
D
PS
p
p
n
n
CL
CL
PS
CL
VDD
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
VSS
FIGURE 2.
CD4021BMS LOGIC DIAGRAM
TRUTH TABLE - CD4021BMS
CL
SERIAL
INPUT
PARALLEL/SERIAL
CONTROL
PI-1
PI-n
Q1
(INTERNAL)
Qn
X
X
1
0
0
0
0
X
X
1
0
1
0
1
X
X
1
1
0
1
0
X
X
1
1
1
1
1
0
0
X
X
0
Qn-1
1
0
X
X
1
Qn-1
X
0
X
X
Q1
Qn
X = Don’t Care Case
7-86
NC
CD4014BMS, CD4021BMA
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25
20
15
10V
10
5
5V
0
5
10
AMBIENT TEMPERATURE (TA) = +25oC
15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
10V
7.5
5.0
2.5
15
5V
0
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
0
-5
-10
-15
-10V
-20
-25
-15V
-30
-5
-10V
PROPAGATION DELAY TIME (tTHL, tTLH) (ns)
TRANSITION TIME (tTHL, tTLH) (ns)
SUPPLY VOLTAGE (VDD) = 5V
100
10V
15V
20
-15
FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
200
0
0
-10
-15V
AMBIENT TEMPERATURE (TA) = +25oC
50
0
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
150
0
AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
0
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
30
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
Typical Performance Characteristics
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
AMBIENT TEMPERATURE (TA) = +25oC
300
SUPPLY VOLTAGE (VDD) = 5V
200
10V
100
15V
0
0
FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
20
40
60
CAPACITANCE (CL) (pF)
80
FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE
7-87
100
CD4014BMS, CD4021BMS
Typical Performance Characteristics
POWER DISSIPATION (PD) (µW)
105
(Continued)
6
4
2
104
SUPPLY VOLTAGE
(VDD) = 15V
8
6
4
10V
10V
2
103
8
6
4
5V
2
102
CL = 50pF
CL = 15pF
8
6
4
AMBIENT TEMPERATURE (TA) = +25oC
2
10
2
1
FIGURE 9.
4 6 8
2
2
4 68
4 68
2
4 68
10
102
103
104
CLOCK INPUT FREQUENCY (fCL) (kHz)
2
4 68
105
TYPICAL POWER DISSIPATION AS A FUNCTION OF FREQUENCY
Chip Dimensions and Pad Layouts
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3 inch)
METALLIZATION: Thickness: 11kÅ − 14kÅ,
PASSIVATION:
AL.
10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS:
0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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