DATASHEET

CD4076BMS
CMOS 4 -Bit D-Type Registers
December 1992
Features
Pinout
• High Voltage Type (20V Rating)
CD4076BMS
TOP VIEW
• Three State Outputs
• Input Disabled Without Gating the Clock
OUTPUT
DISABLE
• Gated Output Control Lines for Enabling or Disabling
the Outputs
M
1
16 VDD
N
2
15 RESET
Q1
3
14 DATA 1
• Standardized Symmetrical Output Characteristics
Q2
4
13 DATA 2
• 100% Tested for Quiescent Current at 20V
Q3
5
12 DATA 3
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
Q4
6
11 DATA 4
CLOCK
7
10 G2
VSS
8
9 G1
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
Functional Diagram
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
DATA INPUT
DISABLE
Description
G1
CD4076BMS types are four-bit registers consisting of D-type
flip-flops that feature three-state outputs. Data Disable inputs
are provided to control the entry of data into the flip-flops.
When both Data Disable inputs are low, data at the D inputs
are loaded into their respective flip-flops on the next positive
transition of the clock input. Output Disable inputs are also
provided. When the Output Disable inputs are both low, the
normal logic states of the four outputs are available to the
load. The outputs are disabled independently of the clock by
a high logic level at either Output Disable input, and present
a high impedance.
9
G2
10
H4T
Frit Seal DIP
H1E
Ceramic Flatpack
H6W
CLOCK
7
M
1
N
2
14
3
Q1
13
D2
D3
12
4
4D - TYPE
FLIP-FLOPS
WITH
AND-OR
LOGIC
Q2
5
11
Q3
6
D4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1029
OUTPUT
DISABLE
D1
The CD4076BMS is supplied in these 16 lead outline packages:
Braze Seal DIP
DATA
INPUT
DISABLE
Q4
15
RESET
VSS = 8
VDD = 16
File Number
3325
Specifications CD4076BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . .
θja
θjc
Ceramic DIP and FRIT Package . . . . . 80oC/W
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
o
Maximum Package Power Dissipation (PD) at +125 C
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
Input Leakage Current
SYMBOL
IDD
IIL
GROUP A
SUBGROUP
S
TEMPERATURE
MIN
1
+25oC
-
10
µA
2
+125oC
-
1000
µA
VDD = 18V, VIN = VDD or GND
3
-55oC
-
10
µA
VIN = VDD or GND
1
+25oC
-100
-
nA
2
+125oC
-1000
-
nA
3
-55oC
-100
-
nA
1
+25oC
-
100
nA
2
+125oC
-
1000
nA
3
-55oC
-
100
nA
CONDITIONS (NOTE 1)
VDD = 20V, VIN = VDD or GND
VDD = 20
VDD = 18V
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 20
VDD = 18V
LIMITS
MAX
UNIT
S
Output Voltage
VOL15
VDD = 15V, No Load
1, 2, 3
+25oC, +125oC, 55oC
-
50
mV
Output Voltage
VOH15
VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, 55oC
14.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1
+25oC
0.53
-
mA
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1
+25oC
1.4
-
mA
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1
+25oC
3.5
-
mA
-
-0.53
mA
Output Current
(Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1
+25oC
Output Current
(Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1
+25oC
-
-1.8
mA
Output Current
(Source)
IOH10
VDD = 10V, VOUT = 9.5V
1
+25oC
-
-1.4
mA
Output Current
(Source)
IOH15
VDD = 15V, VOUT = 13.5V
1
+25oC
-
-3.5
mA
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10µA
1
+25oC
-2.8
-0.7
V
P Threshold Voltage
VPTH
VSS = 0V, IDD = 10µA
1
+25oC
0.7
2.8
V
VDD = 2.8V, VIN = VDD or GND
7
+25oC
7
+25oC
VOH >
VDD/2
VDD = 18V, VIN = VDD or GND
8A
+125oC
VOL
<
VDD/2
V
VDD = 20V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
8B
-
1.5
V
Functional
F
-55oC
Input Voltage Low
(Note 2)
VIL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC,
Input Voltage High
(Note 2)
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, 55oC
3.5
-
V
Input Voltage Low
(Note 2)
VIL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, 55oC
-
4
V
Input Voltage High
(Note 2)
VIH
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, 55oC
11
-
V
Tri-State Output
Leakage
IOZL
VIN = VDD or GND
VOUT = 0V
1
+25oC
-0.4
-
µA
2
+125oC
-12
-
µA
3
-55oC
-0.4
-
µA
VDD = 20V
VDD = 18V
7-1030
+125oC, 55oC
Specifications CD4076BMS
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Tri-State Output
Leakage
SYMBOL
CONDITIONS (NOTE 1)
IOZH
VIN = VDD or GND
VOUT = VDD
VDD = 20V
VDD = 18V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
GROUP A
SUBGROUP
S
LIMITS
TEMPERATURE
MIN
MAX
1
+25oC
-
0.4
µA
2
+125oC
-
12
µA
3
-55oC
-
0.4
µA
UNIT
S
3. For accuracy, voltage is measured differentially to VDD.
Limit is 0.050V max.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Propagation Delay
Clock to Q Output
Transition Time
SYMBOL
TPHL
TPLH
CONDITIONS (Notes 1, 2)
GROUP A
SUBGROUPS TEMPERATURE
VDD = 5V, VIN = VDD or GND
9
10, 11
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
+25oC
+125oC,
-55oC
LIMITS
MIN
MAX
UNITS
-
600
ns
-
810
ns
9
+25oC
-
200
ns
10, 11
+125oC, -55oC
-
270
ns
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55oC, +25oC
-
5
µA
+125oC
-
150
µA
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
Output Voltage
VOL
VDD = 5V, No Load
1, 2
1, 2
1, 2
-55 C, +25 C
-
10
µA
+125oC
-
300
µA
o
o
-
10
µA
+125oC
-
600
µA
+25oC, +125oC,
-
50
mV
-55oC,
+25oC
-55oC
Output Voltage
VOL
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
-
50
mV
Output Voltage
VOH
VDD = 5V, No Load
1, 2
+25oC, +125oC,
-55oC
4.95
-
V
Output Voltage
VOH
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
9.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1, 2
+125oC
0.36
-
mA
-55oC
0.64
-
mA
+125oC
0.9
-
mA
-55oC
1.6
-
mA
+125oC
2.4
-
mA
-55oC
4.2
-
mA
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
IOL10
IOL15
IOH5A
IOH5B
IOH10
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
1, 2
1, 2
1, 2
VDD = 5V, VOUT = 2.5V
1, 2
VDD = 10V, VOUT = 9.5V
7-1031
1, 2
+125oC
-
-0.36
mA
-55oC
-
-0.64
mA
+125oC
-
-1.15
mA
-55oC
-
-2.0
mA
+125oC
-
-0.9
mA
-55oC
-
-2.6
mA
Specifications CD4076BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
Output Current (Source)
SYMBOL
IOH15
CONDITIONS
VDD =15V, VOUT = 13.5V
NOTES
TEMPERATURE
MIN
MAX
UNITS
1, 2
+125oC
-
-2.4
mA
o
-55 C
-
-4.2
mA
Input Voltage Low
VIL
VDD = 10V, VOH > 9V, VOL <
1V
1, 2
+25oC, +125oC,
-55oC
-
3
V
Input Voltage High
VIH
VDD = 10V, VOH > 9V, VOL <
1V
1, 2
+25oC, +125oC,
-55oC
7
-
V
Propagation Delay
Clock to Q Output
TPHL1
TPLH1
VDD = 10V
1, 2, 3
+25oC
-
250
ns
VDD = 15V
1, 2, 3
+25oC
-
180
ns
o
-
460
ns
o
Propagation Delay
Reset
Propagation Delay
3 - State
TPHL2
TPHZ
TPLZ
VDD = 5V
1, 2, 3
VDD = 10V
1, 2, 3
+25 C
-
200
ns
VDD = 15V
1, 2, 3
+25oC
-
150
ns
VDD = 5V
1, 2, 4
+25oC
-
300
ns
VDD = 10V
1, 2, 4
+25oC
-
150
ns
1, 2, 4
+25oC
-
120
ns
VDD = 15V
Propagation Delay
3 - State
TPZH
TPZL
Transition Time
Maximum Clock Input
Frequency
Minimum Data Setup
Time
Minimum Data Hold Time
Reset Pulse Width
Minimum Clock Pulse
Width
Minimum Data Input SetUp Time
Maximum Clock Input
Rise and Fall Time
Input Capacitance
TTHL
TTLH
TTLH
FCL
TS
1, 2, 4
+25 C
-
300
ns
VDD = 10V
1, 2, 4
+25oC
-
150
ns
1, 2, 4
+25oC
-
120
ns
VDD = 10V
1, 2, 3
+25
oC
-
100
ns
VDD = 15V
1, 2, 3
+25oC
-
80
ns
ns
VDD = 10V
TW
TS
TRCL
TFCL
CIN
o
1, 2, 3
+25 C
-
-
VDD = 15V
1, 2, 3
+25
oC
-
-
ns
VDD = 5V
1, 2, 3
+25oC
3
-
MHz
VDD = 10V
1, 2, 3
+25oC
6
-
MHz
VDD = 15V
1, 2, 3
+25oC
8
-
MHz
VDD = 5V
1, 2, 3
+25oC
-
200
ns
1, 2, 3
+25
oC
-
80
ns
VDD = 15V
1, 2, 3
+25oC
-
60
ns
VDD = 5V
1, 2, 3
+25oC
-
120
ns
VDD = 10V
1, 2, 3
+25oC
-
50
ns
VDD = 15V
1, 2, 3
+25oC
-
40
ns
VDD = 5V
1, 2, 3
+25oC
-
200
ns
VDD = 10V
1, 2, 3
+25oC
-
100
ns
VDD = 15V
1, 2, 3
+25oC
-
80
ns
1, 2, 3
+25oC
-
180
ns
VDD = 10V
1, 2, 3
+25oC
-
100
ns
VDD = 15V
1, 2, 3
+25oC
-
70
ns
1, 2, 3, 5
+25oC
-
15
µs
VDD = 10V
1, 2, 3, 5
+25oC
-
5
µs
VDD = 15V
1, 2, 3, 5
+25oC
-
5
µs
1, 2
+25oC
-
7.5
pF
VDD = 10V
TW
o
VDD = 5V
VDD = 15V
Transition Time
+25 C
VDD = 5V
VDD = 5V
Any Input
7-1032
Specifications CD4076BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
5. If more than one unit is cascaded, TRCL should be made less than or equal to the sum of the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
Supply Current
CONDITIONS
NOTES
TEMPERATURE
MAX
UNITS
VDD = 20V, VIN = VDD or GND
1, 4
+25 C
-
25
µA
VDD = 10V, ISS = -10µA
1, 4
+25oC
-2.8
-0.2
V
VDD = 10V, ISS = -10µA
1, 4
+25oC
-
±1
V
VTP
VSS = 0V, IDD = 10µA
1, 4
+25oC
0.2
2.8
V
∆VTP
VSS = 0V, IDD = 10µA
1, 4
+25oC
-
±1
V
1
+25oC
VOH >
VDD/2
VOL <
VDD/2
V
1, 2, 3, 4
+25oC
-
1.35 x
+25oC
Limit
ns
IDD
N Threshold Voltage
VNTH
N Threshold Voltage
Delta
∆VTN
P Threshold Voltage
P Threshold Voltage
Delta
Functional
F
VDD = 18V, VIN = VDD or GND
o
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
MIN
TPHL
TPLH
VDD = 5V
3. See Table 2 for +25oC limit.
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-2
IDD
± 1.0µA
Output Current (Sink)
IOL5
± 20% x Pre-Test Reading
IOH5A
± 20% x Pre-Test Reading
Output Current (Source)
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
100% 5004
1, 7, 9, Deltas
CONFORMANCE GROUP
PDA (Note 1)
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
100% 5004
1, 7, 9, Deltas
100% 5004
2, 3, 8A, 8B, 10, 11
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Sample 5005
1, 2, 3, 8A, 8B, 9
PDA (Note 1)
Final Test
Group A
Group B
Group D
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
7-1033
READ AND RECORD
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
Specifications CD4076BMS
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
TEST
READ AND RECORD
MIL-STD-883
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
1, 9
Table 4
Group E Subgroup 2
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
Static Burn-In 1 Note 1
3-6
1, 2, 7 - 15
16
Static Burn-In 2 Note 1
3-6
8
1, 2, 7, 9 -16
-
1, 2, 8 - 10, 15
16
3-6
8
1, 2, 7, 9 - 16
Dynamic Burn-In Note 1
Irradiation (Note 2)
VDD
9V ± -0.5V
50kHz
25kHz
3-6
7
11 - 14
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V
M
1
N
2
*
OUTPUT
DISABLE
*
DATA
1
14
G1
9
G2
10
DATA
INPUT
DISABLE
D
*
CL Q
R
*
16
VDD
3
Q1
4
Q2
5
Q3
6
Q4
8
VSS
Q
*
DATA
2
Q
*
D
*
CL Q
R
*
D
13
CLOCK
7
DATA
3
12
Q
CL Q
R
* ALL INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
VDD
DATA
4
11
D
*
Q
CL Q
R
*
VSS
RESET
15
FIGURE 1. CD4076BMS LOGIC DIAGRAM
7-1034
CD4076BMS
TRUTH TABLE
DATA INPUT DISABLE
DATA
NEXT STATE
OUTPUT
Q
RESET
CLOCK
G1
G2
D
1
X
X
X
X
0
0
0
X
X
X
Q
0
1
X
X
Q
NC
0
X
1
X
Q
NC
0
0
0
1
1
0
0
0
0
0
X
X
X
Q
NC
X
X
X
Q
NC
0
1
0
NC
When either Output Disable M or N is high, the outputs are disabled (high impedance state), however sequential operation of the flip-flops is not affected.
1 = High Level
X = Don’t Care
0 = Low Level
NC = No Change
30
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25
20
15
10V
10
5
5V
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
AMBIENT TEMPERATURE (TA) = +25oC
15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
10V
7.5
5.0
2.5
5V
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
0
-5
-10
-15
-10V
-20
-25
-15V
-30
FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
AMBIENT TEMPERATURE (TA) = +25oC
0
0
0
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-5
-10V
-15V
-10
-15
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
Typical Performance Characteristics
FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
7-1035
CD4076BMS
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
TRANSITION TIME (tTHL, tTLH) (ns)
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
Typical Performance Characteristics (Continued)
500
400
SUPPLY VOLTAGE (VDD) = 5V
300
200
10V
100
15V
0
40
20
60
80
100
120
200
150
SUPPLY VOLTAGE (VDD) = 5V
100
10V
5V
50
0
0
140
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
LOAD CAPACITANCE (CL) (pF)
FIGURE 6. TYPICAL PROPAGATION DELAY TIME vs LOAD
CAPACITANCE (CLOCK TO Q)
FIGURE 7. TYPICAL TRANSITION TIME vs LOAD
CAPACITANCE
POWER DISSIPATION PER GATE (PD) (µW)
MAXIMUM CLOCK FREQUENCY
(fCL MAX) (MHz)
AMBIENT TEMPERATURE (TA) = +25oC
LOAD CAPACITANCE (CL) = 50pF
15
10
5
105
8
6
4
2
104 8
6
4
2
103
AMBIENT TEMPERATURE (TA) = +25oC
SUPPLY VOLTAGE (VDD) = 15V
10V
10V
8
6
4
2
102
5V
8
6
4
2
10
8
6
4
2
CL = 50pF
CL = 15pF
1
0
5
2 4 6 8
10
15
20
SUPPLY VOLTAGE (VDD) (V)
10-1
FIGURE 8. TYPICAL MAXIMUM CLOCK INPUT FREQUENCY vs
SUPPLY VOLTAGE
tW
CLOCK
tW
tS
50%
tS
DATA
INPUT
DIABLE
50%
tW
50%
RESET
tTHL
tTLH
90%
50%
Q
OUTPUT
10%
tPHL
tPLH
2 4 6 8
2 4 6 8
2 4 6 8
10
102
103
INPUT FREQUENCY (f) (kHz)
2 4 6 8
2 4 6 8
104
FIGURE 9. TYPICAL DYNAMIC POWER DISSIPATION vs
FREQUENCY
50%
tS
1
tPHL
FIGURE 10. FUNCTIONAL WAVEFORM
7-1036
CD4076BMS
VDD
50%
OUTPUT DISABLE
Q OUTPUT
VOLTAGE
CHARACTER
AT D
AT Q
VDD
tPHZ
VDD
VSS
VOL
tPLZ
VSS
VDD
VOH
tPZL
VSS
VDD
tPZH
VDD
VSS
VSS
tPLZ
Q OUTPUT
TEST
50%
tPZL
90%
10%
90%
10%
VSS
tPZH
tPHZ
FIGURE 11. FUNCTIONAL WAVEFORM
Chip Dimensions and Pad Layout
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3 inch)
METALLIZATION:
PASSIVATION:
Thickness: 11kÅ − 14kÅ,
AL.
10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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1037
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