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ISL8471
Data Sheet
September 15, 2008
Ultra Low ON-Resistance, Low Voltage,
Single Supply, Dual SPDT Analog Switch
The Intersil ISL84762 device is a low ON-resistance, low
voltage, bidirectional, dual single-pole/double-throw (SPDT)
analog switch designed to operate from a single +1.65V to
+3.6V supply. Targeted applications include battery powered
equipment that benefits from low rON (0.35 and fast
switching speeds (tON = 14ns, tOFF = 6ns). The digital logic
input is 1.8V logic-compatible when using a single +3V supply.
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This part may be used to “mux-in”
additional functionality while reducing ASIC design risk. The
ISL84762 is offered in small form factor packages, alleviating
board space limitations.
The ISL84762 is a committed dual single-pole/double-throw
(SPDT) that consist of two normally open (NO) and two
normally (NC) switches. This configuration can be used as a
dual 2-to-1 multiplexer. The ISL84762 is pin compatible with
the MAX4762.
TABLE 1. FEATURES AT A GLANCE
ISL84762
FN6105.1
Features
• Pb-Free Available (RoHS Compliant)
• Pin Compatible Replacement for the MAX4762
• ON-Resistance (rON)
- V+ = +2.7V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.39
- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.55
• rON Matching Between Channels . . . . . . . . . . . . . . . . 0.05
• rON Flatness Across Signal Range . . . . . . . . . . . . . . 0.043
• Single Supply Operation. . . . . . . . . . . . . . . . +1.65V to +3.6V
• Low Power Consumption (PD) . . . . . . . . . . . . . . . . . <0.02µW
• Fast Switching Action (V+ = +2.7V)
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ns
• ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >9kV
• Guaranteed Break-before-Make
• 1.8V Logic Compatible (+3V supply)
• Available in 10 Ld 3x3 Thin DFN and 10 Ld MSOP
Applications
ISL84762
• Battery-powered, Handheld, and Portable Equipment
- Cellular/mobile Phones
- Pagers
- Laptops, Notebooks, Palmtops
Number of Switches
2
SW
SPDT or 2-to-1 MUX
3V rON
0.35
3V tON/tOFF
12ns/5ns
1.8V rON
0.55
1.8V tON/tOFF
20ns/8ns
Packages
10 Ld 3x3 TDFN, 10 Ld MSOP
• Portable Test and Measurement
• Medical Equipment
• Audio and Video Switching
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL84762
Pinout
Ordering Information
(Note 1)
ISL84762
(10 LD TDFN, MSOP)
TOP VIEW
V+ 1
PART
NUMBER
10 NO2
NO1 2
9
COM2
COM1 3
8
NC2
7 IN2
NC1 4
IN1 5
6
GND
NOTE:
1. Switches Shown for Logic “0” Input.
Truth Table
LOGIC
NC1, NC2
NO1, NO2
0
ON
OFF
1
OFF
ON
NOTE:
Logic “0” 0.5V. Logic “1” 1.4V with a 3V supply.
Pin Descriptions
PIN
V+
FUNCTION
System Power Supply Input (+1.65V to +3.6V)
GND
Ground Connection
IN
Digital Control Input
COM
TEMP.
RANGE
PART
(°C)
MARKING
PACKAGE
PKG.
DWG. #
ISL84762IR
762
-40 to +85 10 Ld 3x3 TDFN L10.3x3A
ISL84762IR-T*
762
-40 to +85 10 Ld 3x3 TDFN L10.3x3A
Tape and Reel
ISL84762IU
4762
-40 to +85 10 Ld MSOP
M10.118
ISL84762IU-T*
4762
-40 to +85 10 Ld MSOP
Tape and Reel
M10.118
ISL84762IRZ
(Note)
762Z
-40 to +85 10 Ld 3x3 TDFN L10.3x3A
(Pb-free)
ISL84762IRZ-T* 762Z
(Note)
-40 to +85 10 Ld 3x3 TDFN L10.3x3A
Tape and Reel
(Pb-free)
ISL84762IUZ
(Note)
-40 to +85 10 Ld MSOP
(Pb-free)
M10.118
-40 to +85 10 Ld MSOP
Tape and Reel
(Pb-free)
M10.118
4762Z
ISL84762IUZ-T* 4762Z
(Note)
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
Analog Switch Common Pin
NO
Analog Switch Normally Open Pin
NC
Analog Switch Normally Closed Pin
2
FN6105.1
September 15, 2008
ISL84762
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V
Input Voltages
NO, NC, IN (Note 2) . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Output Voltages
COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . ±300mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±500mA
ESD Rating:
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>9kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1kV
Thermal Resistance (Typical)
JA (°C/W)
JC (°C/W)
10 Ld 3x3 TDFN Package (Note 3) . . .
47
11
10 Ld MSOP Package (Note 4) . . . . . .
162
N/A
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 5)
Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 6, 7)
TYP
MAX
(Notes 6, 7) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-Resistance, rON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+
(See Figure 5)
rON Matching Between Channels,
rON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at max
rON (Note 10)
rON Flatness, RFLAT(ON)
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+
(Note 8)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 3.3V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V = 3.3V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V, 3V,
or Floating
Full
0
-
V+
V
25
-
0.39
0.6

Full
-
-
0.6

25
-
0.05
0.2

Full
-
-
0.2

25
-
0.043
0.1

Full
-
-
0.15

25
-2
-
2
nA
Full
-40
-
40
nA
25
-3
-
3
nA
Full
-60
-
60
nA
25
-
14
20
ns
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF
(See Figure 1, Note 9)
Turn-OFF Time, tOFF
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF
(See Figure 1, Note 9)
Full
-
-
25
ns
25
-
6
12
ns
Full
-
-
17
ns
Break-Before-Make Time Delay, tD
V+ = 3.3V, VNO or VNC = 1.5V, RL = 50, CL = 35pF
(See Figure 3, Note 9)
Full
2
7
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0See Figure 2)
25
-
95
-
pC
OFF-Isolation
RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(See Figure 4)
25
-
-68
-
dB
Crosstalk (Channel-to-Channel)
RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(See Figure 6)
25
-
-95
-
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600
25
-
0.003
-
%
NO or NC OFF Capacitance, COFF
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
25
-
115
-
pF
3
FN6105.1
September 15, 2008
ISL84762
Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 5)
Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
COM ON Capacitance, CCOM(ON)
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
TEMP
MIN
(°C) (Notes 6, 7)
TYP
MAX
(Notes 6, 7) UNITS
25
-
224
-
pF
Full
1.65
-
3.6
V
25
-
-
40
nA
Full
-
-
750
nA
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
V+ = +3.6V, VIN = 0V or V+
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Full
-
-
0.5
V
Input Voltage High, VINH
Full
1.4
-
-
V
Full
-0.5
-
0.5
µA
Input Current, IINH, IINL
V+ = 3.3V, VIN = 0V or V+ (Note 9)
Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 5),
Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 6, 7) TYP (Notes 6, 7) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
Full
0
-
V+
V
V+ = 1.8V, ICOM = 100mA, VNO or VNC = 0V to V+
(See Figure 5, Note 9)
25
-
0.55
-

Full
-
0.6
-

V+ = 1.65V, VNO or VNC = 1.0V, RL =50, CL = 35pF
(See Figure 1, Note 9)
25
-
22
28
ns
Full
-
-
33
ns
V+ = 1.65V, VNO or VNC = 1.0V, RL =50, CL = 35pF
(See Figure 1, Note 9)
25
-
9
15
ns
Full
-
-
20
ns
V+ = 2.0V, VNO or VNC = 1.0V, RL =50, CL = 35pF,
(See Figure 3, Note 9)
Full
2
9
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0See Figure 2)
25
-
49
-
pC
OFF-Isolation
RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(See Figure 4)
25
-
-68
-
dB
Crosstalk (Channel-to-Channel)
RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(See Figure 6)
25
-
-95
-
dB
NO or NC OFF Capacitance, COFF
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
25
-
115
-
pF
COM ON Capacitance, CCOM(ON)
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
25
-
224
-
pF
Full
-
-
0.4
V
ON-Resistance, rON
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
Turn-OFF Time, tOFF
Break-Before-Make Time Delay, tD
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Input Voltage High, VINH
Input Current, IINH, IINL
V+ = 2.0V, VIN = 0V or V+ (Note 9)
Full
1.0
-
-
V
Full
-0.5
-
0.5
µA
NOTES:
5. VIN = input voltage to perform proper function.
6. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
8. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range.
9. Limits established by characterization and are not production tested.
10. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON
value.
4
FN6105.1
September 15, 2008
ISL84762
Test Circuits and Waveforms
V+
LOGIC
INPUT
V+
tr < 5ns
tf < 5ns
50%
0V
tOFF
SWITCH
INPUT VNO
SWITCH
INPUT
VOUT
NO OR NC
COM
IN
VOUT
90%
SWITCH
OUTPUT
C
90%
LOGIC
INPUT
CL
35pF
RL
50
GND
0V
tON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
V OUT = V (NO or NC) -----------------------R L + r ON
FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
V+
RG
SWITCH
OUTPUT
VOUT
C
VOUT
COM
NO OR NC
VOUT
VG
GND
IN
CL
V+
LOGIC
INPUT
ON
ON
OFF
LOGIC
INPUT
0V
Q = VOUT x CL
Repeat test for all switches.
FIGURE 2B. TEST CIRCUIT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. CHARGE INJECTION
V+
V+
LOGIC
INPUT
VNX
NO
RL
50
IN
SWITCH
OUTPUT
VOUT
90%
0V
LOGIC
INPUT
VOUT
COM
NC
0V
C
CL
35pF
GND
tD
FIGURE 3A. MEASUREMENT POINTS
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
5
FN6105.1
September 15, 2008
ISL84762
Test Circuits and Waveforms (Continued)
V+
C
V+
C
SIGNAL
GENERATOR
rON = V1/100mA
NO OR NC
NO OR NC
IN
VNX
0V OR V+
100mA
IN
V1
0V OR V+
COM
ANALYZER
GND
COM
RL
GND
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
Repeat test for all switches.
FIGURE 4. OFF-ISOLATION TEST CIRCUIT
FIGURE 5. rON TEST CIRCUIT
V+
C
V+
C
SIGNAL
GENERATOR
NO OR NC
COM
50
NO OR NC
IN1
IN
0V OR V+
NC OR NO
COM
ANALYZER
0V OR V+
IMPEDANCE
ANALYZER
COM
NC
GND
RL
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 6. CROSSTALK TEST CIRCUIT
Detailed Description
The ISL84762 is a bidirectional, dual single pole/double
throw (SPDT) analog switch that offers precise switching
capability from a single 1.65V to 3.6V supply with low
ON-resistance (0.39) and high speed operation
(tON = 14ns, tOFF = 6ns). The device is especially well suited
for portable battery powered equipment due to its low
operating supply voltage (1.65V), low power consumption
(2.7µW max), low leakage currents (60nA max), and the tiny,
Thin DFN and MSOP packages. The ultra low ON-resistance
and rON flatness provide very low insertion loss and distortion
to applications that require signal reproduction.
External V+ Series Resistor
For improved ESD and latch-up immunity, Intersil
recommends adding a 100 resistor in series with the V+
power supply pin of the ISL84762 IC (see Figure 8).
6
GND
Repeat test for all switches.
FIGURE 7. CAPACITANCE TEST CIRCUIT
During an overvoltage transient event, such as occurs during
system level IEC 61000 ESD testing, substrate currents can
be generated in the IC that can trigger parasitic SCR
structures to turn ON, creating a low impedance path from
the V+ power supply to ground. This will result in a
significant amount of current flow in the IC, which can
potentially create a latch-up state or permanently damage
the IC. The external V+ resistor limits the current during this
over-stress situation and has been found to prevent latch-up
or destructive damage for many overvoltage transient
events.
Under normal operation, the sub-microamp IDD current of
the IC produces an insignificant voltage drop across the
100 series resistor resulting in no impact to switch
operation or performance.
FN6105.1
September 15, 2008
ISL84762
V+
OPTIONAL
PROTECTION
RESISTOR
OPTIONAL
SCHOTTKY
DIODE
C
V+
100
OPTIONAL
PROTECTION
RESISTOR
NO
COM
INX
VNX
NC
VCOM
IN
GND
OPTIONAL
SCHOTTKY
DIODE
FIGURE 8. V+ SERIES RESISTOR FOR ENHANCED ESD AND
LATCH-UP IMMUNITY
Supply Sequencing and Overvoltage Protection
GND
FIGURE 9. OVERVOLTAGE PROTECTION
Power-Supply Considerations
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 9). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND.
The ISL84762 construction is typical of most single supply
CMOS analog switches, in that they have two supply pins:
V+ and GND. V+ and GND drive the internal CMOS
switches and set their analog voltage limits. Unlike switches
with a 4V maximum supply voltage, the ISL84762 4.8V
maximum supply voltage provides plenty of room for the
10% tolerance of 3.6V supplies, as well as room for
overshoot and noise spikes.
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be used
to provided additional protection to limit the current in the
event that the voltage at a signal pin or logic pin goes below
ground or above the V+ rail.
The minimum recommended supply voltage is 1.65V but the
part will operate with a supply below 1.5V. It is important to
note that the input signal range, switching times, and
ON-resistance degrade at lower supply voltages. Refer to
the “Electrical Specifications” tables beginning on page 3
and “Typical Performance Curves” beginning on page 8 for
details.
Logic inputs can be protected by adding a 1k resistor in
series with the logic input (see Figure 9). The resistor limits
the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
V+ and GND also power the internal logic and level shiftiers.
The level shiftiers convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low rON switch. Connecting Schottky
diodes to the signal pins as shown in Figure 9 will shunt the
fault current to the supply or to ground thereby protecting the
switch. These Schottky diodes must be sized to handle the
expected fault current.
7
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.
FN6105.1
September 15, 2008
ISL84762
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 2.0V to 3.6V (see Figure 16). At 3.6V
the VIH level is about 1.27V. This is still below the 1.8V
CMOS guaranteed high output minimum level of 1.4V, but
noise margin is reduced.
about 68dB in 50 systems, decreasing approximately 20dB
per decade as frequency increases. Higher load
impedances decrease off-Isolation and crosstalk rejection
due to the voltage divider action of the switch OFF
impedance and the load impedance.
Leakage Considerations
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One of
these diodes conducts if any analog signal exceeds V+ or
GND.
High-Frequency Performance
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
In 50 systems, the signal response is reasonably flat even
past 30MHz with a -3dB bandwidth of 120MHz (see
Figure 17). The frequency response is very consistent over a
wide V+ range, and for varying analog signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off-Isolation
is the resistance to this feedthrough, while crosstalk
indicates the amount of feedthrough from one switch to
another. Figure 18 details the high off-Isolation and crosstalk
rejection provided by this part. At 100kHz, off-Isolation is
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified.
0.44
0.7
V+ = 2.7V
ICOM = 100mA
ICOM = 100mA
0.42
0.6
+85°C
0.40
V+ = 1.8V
0.4
V+ = 3.6V
V+ = 2.7V
0.3
rON ()
rON ()
0.5
V+ = 3V
+25°C
0.36
0.34
0.2
0.1
0.38
-40°C
0.32
0.30
0
1
2
3
VCOM (V)
FIGURE 10. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
8
4
0
0.5
1.0
1.5
2.0
2.5
3.0
VCOM (V)
FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE
FN6105.1
September 15, 2008
ISL84762
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified. (Continued)
0.65
100
V+ = 1.8V
ICOM = 100mA
0.60
75
+85°C
V+ = 3V
50
0.50
Q (pC)
rON ()
0.55
25
V+ = 1.8V
0.45
0
-40°C
0.40
+25°C
-25
0.35
0
0.5
1.0
1.5
-50
2.0
0
0.5
1.0
1.5
2.0
2.5
3.0
VCOM (V)
VCOM (V)
FIGURE 13. CHARGE INJECTION vs SWITCH VOLTAGE
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
60
14
13
12
50
40
tOFF (ns)
30
9
+85°C
6
+25°C
5
-40°C
1.5
4
2.0
2.5
3.0
V+ (V)
3.5
4.0
3
1.0
4.5
FIGURE 14. TURN-ON TIME vs SUPPLY VOLTAGE
1.5
2.0
2.5
3.0
V+ (V)
3.5
4.0
NORMALIZED GAIN (dB)
1.4
1.3
V+ = 3V
0
GAIN
-20
1.2
1.1
VINH
1.0
0.9
0
PHASE
20
0.8
40
VINL
0.7
60
0.6
80
0.5
RL = 50
VIN = 0.2VP-P TO 2VP-P
0.4
0.3
1.0
4.5
FIGURE 15. TURN-OFF TIME vs SUPPLY VOLTAGE
1.5
VINH AND VINL (V)
-40°C
7
+25°C
20
10
1.0
+85°C
8
PHASE (°)
tON (ns)
11
10
1.5
2.0
2.5
3.0
3.5
4.0
4.5
V+ (V)
FIGURE 16. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
9
1M
100
10M
100M
FREQUENCY (Hz)
600M
FIGURE 17. FREQUENCY RESPONSE
FN6105.1
September 15, 2008
ISL84762
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified. (Continued)
-10
10
-20
20
-30
30
-40
40
-50
50
-60
60
ISOLATION
-70
70
-80
80
CROSSTALK
-90
SUBSTRATE POTENTIAL (POWERED UP):
GND (QFN Paddle Connection: Tie to GND or Float)
TRANSISTOR COUNT:
114
PROCESS:
Submicron CMOS
90
-100
-110
1k
Die Characteristics
OFF-ISOLATION (dB)
CROSSTALK (dB)
V+ = 3V
100
10k
100k
1M
10M
110
100M 500M
FREQUENCY (Hz)
FIGURE 18. CROSSTALK AND OFF-ISOLATION
10
FN6105.1
September 15, 2008
ISL84762
Thin Dual Flat No-Lead Plastic Package (TDFN)
L10.3x3A
2X
0.10 C A
A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
D
MILLIMETERS
2X
0.10 C B
E
B
//
A
C
SEATING
PLANE
D2
(DATUM B)
6
INDEX
AREA
0.10 C
0.08 C
A3
SIDE VIEW
7
8
MAX
NOTES
A
0.70
0.75
0.80
-
A1
-
-
0.05
-
0.20 REF
b
0.20
0.25
1
0.30
5, 8
D
2.95
3.0
3.05
-
D2
2.25
2.30
2.35
7, 8
E
2.95
3.0
3.05
-
E2
1.45
1.50
1.55
7, 8
e
0.50 BSC
-
k
0.25
-
-
-
L
0.25
0.30
0.35
8
N
10
2
Nd
5
3
Rev. 3 3/06
NOTES:
2
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
NX k
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
E2
E2/2
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
N
N-1
NX b
e
(Nd-1)Xe
REF.
BOTTOM VIEW
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
0.10 M C A B
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Compliant to JEDEC MO-229-WEED-3 except for D2
dimensions.
CL
NX (b)
NOMINAL
D2/2
(DATUM A)
8
MIN
A3
6
INDEX
AREA
TOP VIEW
SYMBOL
(A1)
L1
5
9 L
e
SECTION "C-C"
C C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
11
FN6105.1
September 15, 2008
ISL84762
Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1
INCHES
E
-B-
INDEX
AREA
1 2
0.20 (0.008)
A B C
TOP VIEW
4X 
0.25
(0.010)
R1
R
GAUGE
PLANE
SEATING
PLANE -CA
4X 
A2
A1
b
-H-
0.10 (0.004)
L
SEATING
PLANE
C
D
0.20 (0.008)
MAX
MIN
MAX
NOTES
0.037
0.043
0.94
1.10
-
A1
0.002
0.006
0.05
0.15
-
A2
0.030
0.037
0.75
0.95
-
b
0.007
0.011
0.18
0.27
9
c
0.004
0.008
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.116
0.120
2.95
3.05
4
0.020 BSC
C
a
CL
E1
0.20 (0.008)
C D
0.50 BSC
-
E
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
0.037 REF
N
C
SIDE VIEW
MIN
A
L1
-A-
e
SYMBOL
e
L1
MILLIMETERS
0.95 REF
10
R
0.003
R1


-
10
-
0.07
0.003
-
5o
15o
0o
6o
7
-
-
0.07
-
-
5o
15o
-
0o
6o
-B-
Rev. 0 12/02
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A -H- .
and - B -
to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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12
FN6105.1
September 15, 2008
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