PulseGuard® Suppressors Surface Mount Polymeric ESD Suppressors PGB2 Series Halogen Free / Lead-Free Description PulseGuard ESD Suppressors help protect sensitive electronic equipment against electrostatic discharge (ESD). They use polymer composite materials to suppress fastrising ESD transients (as specified in IEC 61000-4-2), while adding virtually no capacitance to the circuit. They supplement the on-chip protection of integrated circuitry and are best suited for low-voltage, high-speed applications where low capacitance is important to ensure minimal interference of data signal integrity. The new and ultra-small surface mount PGB2 0402 series offers a RoHS Compliant, Halogen Free, and 100% Lead Free circuit protection alternative. Equivalent Circuits 2 1 Features t 3P)4DPNQMJBOU t-FBEGSFF t)BMPHFOGSFF t6MUSBMPXDBQBDJUBODF t-PXMFBLBHFDVSSFOU t'BTUSFTQPOTFUJNF Product Characteristics Part Number Lines Protected Component Package 1 0402 PGB2010402KRHF t0OFMJOFPGQSUFDUJPO t#JEJSFDUJPOBM t8JUITUBOETNVMUJQMF &4%TUSJLFT t$PNQBUJCMFXJUI QJDLBOEQMBDFQSPDFTTFT Applications t)%57)BSEXBSF t-BQUPQ%FTLUPQ Computer t/FUXPSL)BSEXBSF t$PNQVUFS1FSJQIFSBMT t%JHJUBM$BNFSB t&YUFSOBM4UPSBHF t4FU5PQ#PY t"OUFOOB Electrical Characteristics Specification ESD Capability: IEC 61000-4-2 Direct Discharge *&$"JS%JTDIBSHF 5SJHHFS7PMUBHFUZQJDBM $MBNQJOH7PMUBHFUZQJDBM 5SJHHFS7PMUBHFUZQJDBM $MBNQJOH7PMUBHFUZQJDBM 3BUFE7PMUBHFNBYJNVN Capacitance (typical) PGB2010402 L7 L7 7 7 7 7 <1nS -FBLBHF$VSSFOUUZQJDBM O" PGB2 Series Specifications are subject to change without notice. Measured per IEC 61000-4-2 L7%JSFDU%JTDIBSHF.FUIPE .FBTVSFEVTJOH75-1%JSFDU Discharge Method 7%$NBY 0.07 pF, typical Response Time &4%1VMTF8JUITUBOE Notes 1000 pulses min Measured at 250 MHz Measured per IEC 61000-4-2 L7%JSFDU%JTDIBSHF.FUIPE .FBTVSFEBU7%$ Some shifting in characteristics may occur when tested over multiple pulses at a very rapid rate 1 Revised: March 8, 2011 www.littelfuse.com ©2011 Littelfuse PulseGuard® Suppressors Surface Mount Polymeric ESD Suppressors Typical ESD Response CurveL7*&$%JSFDU%JTDIBSHF Dimensions Dimensions: mm (inch) 0.99 +/- 0.05 (0.039" +/- 0.002") 500 Voltage (V) 400 0.51 +/- 0.05 (0.020" +/- 0.002") 300 0.18 +/- 0.10 (0.007" +/- 0.004") 200 0.30 +/- 0.08 (0.012" +/- 0.003") 0.23 Nom. (0.009") 100 0.23 +/- 0.10 (0.009" +/- 0.004") 0 -25 0 25 50 75 Time (ns) 100 125 150 175 Recommended for reflow soldering only 1.55 (0.061") 0.381 (0.015") .584 (0.023") Typical TLP Response Curve 7%JSFDU%JTDIBSHF 0.559 (0.022") Recommended Pad Layout 200 Voltage (V) 150 Part Numbering System 100 PGB2 01 0402 KR HF 50 HALOGEN FREE LEAD-FREE HALOGEN-FREE PULSEGUARD® ESD SUPPRESSORS 0 -15 0 15 30 45 60 QUANTITY & PACKAGING CODE: KR = 10,000 pieces 75 LINES PROTECTED: 01 = 1 line Time (ns) Typical Insertion Loss DEVICE SIZE CODE: 0402 = 0402 (1005) Typical Device Capacitance 2 0.1 -2 Capacitance (pF) Insertion Loss (dB) 0 -4 -6 -8 -10 -12 10 100 1000 Frequency (MHz) PGB2 Series Specifications are subject to change without notice. 10000 0.01 100000 100 2 Revised: March 8, 2011 1000 Frequency (MHz) 10000 www.littelfuse.com ©2011 Littelfuse PulseGuard® Suppressors Surface Mount Polymeric ESD Suppressors Physical Specifications Environmental Specifications Materials #PEZ&QPYZ(MBTT4VCTUSBUF 5FSNJOBUJPOT$V/J4O Device Weight 0.349 mg Solderability Soldering Parameters Operating Temperature -65°C to +125°C Biased Humity: 40°C, 95% RH, 1000 hours Biased Heat: 85°C, 1000 hours Thermal Shock MIL-STD-202, Method 107G, -65°C to 125°C, 30 min. cycle, 10 cycles Vibration .*-45%.FUIPE" Chemical Resistance MIL-STD-202, Method 215 Solder Leach Resistance and Terminal Adhesion *1$&*"+45% MIL-STD-202, Method 208 8BWFTPMEFS¡$TFDPOETNBYJNVN 3FnPXTPMEFS¡$TFDPOETNBYJNVN Design Consideration Because of the fast rise-time of the ESD transient, proper QMBDFNFOUPG1VMTF(VBSETVQQSFTTPSTBSFBLFZEFTJHO consideration to achieving optimal ESD suppression. The devices should be placed on the circuit board as close to the source of the ESD transient as possible. Install PulseGuard TVQQSFTTPSTDPOOFDUFEGSPNTJHOBMEBUBMJOFUPHSPVOE directly behind the connector so that they are the first boardlevel circuit component encountered by the ESD transient. Soldering Parameters Reflow Condition Pre Heat Pb – Free assembly - Temperature Min (Ts(min)) 150°C - Temperature Max (Ts(max)) 200°C - Time (min to max) (ts) 60 – 180 seconds Average ramp up rate (Liquidus Temp (TL) to peak ¡$TFDPOENBY TS(max) to TL - Ramp-up Rate ¡$TFDPOENBY Reflow - Temperature (TL) (Liquidus) - Temperature (tL) 217°C 60 – 150 seconds Peak Temperature (TP) 260°C Time within 5°C of actual peak Temperature (tp) 10 – 30 seconds Ramp-down Rate ¡$TFDPOENBY 3FDPNNFOEFEQSPmMFCBTFEPO*1$+&%&%+45%$ Time 25°C to peak Temperature (TP) NJOVUFTNBY - For recommended soldering pad layout dimensions, please refer to Dimensions section of this data sheet PGB2 Series Specifications are subject to change without notice. Notes: - PGB2 Series recommended for reflow soldering only 3 Revised: March 8, 2011 www.littelfuse.com ©2011 Littelfuse PulseGuard® Suppressors Surface Mount Polymeric ESD Suppressors Packaging Part Number Quantity & Packaging Code Quantity Packaging Option Packaging Specification KR 10000 Tape & Reel (7” reel) &*"34*&$QBSU PGB2010402 Tape and Reel Specifications Tt Ds Dd Tw Ph Pd Ct Ps Pw Carrier Tape: 8mm, paper Reel: 7” (178mm) Description 0402 Series (mm) Ct$PWFSUBQFUIJDLOFTT 0.053 Dd - Drive hole diameter 1.55 Ds - Drive hole spacing 4.00 Pd1PDLFUEFQUI 0.41 Ph1PDLFUIFJHIU 1.12 Ps1PDLFUTQBDJOH 2.00 Pw1PDLFUXJEUI 0.62 Tt$BSSJFSUBQFUIJDLOFTT 0.61 Tw - Carrier tape width 8.00 Typical ESD Pulse Test Setup FARADAY CAGE COMPUTER AGILENT INFINIIUM 1.5 GHz 8 GS/s 30dB PASTERNAK ATTENUATOR PE7025-30 TEKTRONIX LOW CAP PROBE 6158 (20x TIP) QUADTECH 1865 RESISTANCE METER RESISTANCE TEST FIXTURE ESD TEST FIXTURE TEST BOARD W/ DUT ESD PULSE GENERATOR Notes: - QuadQuadTech 1865 High Resistance Meter: Measures insulation resistance values ,FZ5FL.JOJ;BQ&4%TJNVMBUPSXJUI*&$UJQ4JNVMBUFTL7EJSFDUEJTDIBSHF&4%FWFOUQFS*&$ - Faraday cage: Shields the acquisition equipment from the electromagnetic fields generated by the simulator "HJMFOU()["0TDJMMPTDPQF3FDPSETUIFWPMUBHFXBWFGPSNGSPNUIFEFWJDFVOEFSUFTU 5FLUSPOJYQSPCFXJUIE#BUUFOVBUPS5SBOTNJUTUIFXBWFGPSNGSPNUIFEFWJDFUPUIFPTDJMMPTDPQF PGB2 Series Specifications are subject to change without notice. 4 Revised: March 8, 2011 www.littelfuse.com ©2011 Littelfuse PulseGuard® Suppressors Surface Mount Polymeric ESD Suppressors Characterization Methods for ESD Suppressors Two of the most common methods used in industry for characterizing the performance of ESD suppressors are ESD transient testing, per IEC 61000-4-2 ESD waveform, BOE5-14JODFOPTUBOEBSETFYJTUGPSNFBTVSFNFOUBOE qualification of ESD suppressor performance, these two methods have become the de-facto standard for determining device trigger and clamp specifications. It is common to see trigger values to be based on the TLP method and clamping values based on the ESD transient method. Low voltage TLP obtained trigger values most closely resemble device DC turn-on .Since the two test NFUIPETBSFEJGGFSFOUBOEOPNFUIPEFYJTUTUPBDDVSBUFMZ correlate suppressor response between the two test methods, trigger and clamp values should be specified for each method. Figure 1 Current (I) % 100% 90% 30n 60n tr = 0.7 to 1.0ns Figure 2 ESD Simulator 1 Scope Probe 30db Attenuator 50 Ohm Scope Input 2 330 950 46.93 46.93 + 8000 150pf DUT 3.165 50 - 5SBOTNJTTJPOMJOF1VMTFUFTUJOHDPNNPOMZLOPXBT TLP testing consists of subjecting a ESD suppressor to a 50 ohm transmission line discharge pulse with a subnanosecond risetime and a pulse width of 65ns. Trigger values are obtained by varying the TLP voltage until a EFWJDFUSJHHFSWPMUBHFJTEFUFSNJOFE0ODFUIFEFWJDFJT USJHHFSFEBDMBNQWBMVFJTEFUFSNJOFEBUOT8BWFGPSNT are captured using a 4 GHz oscilloscope(50 ohm input) with 20X resistive divider probes and a 30dB attenuator. Figures 3 and 4 show a typical TLP voltage waveform and test setup. Figure 3 600 500 Volts 400 300 200 *UTIPVMECFOPUFEUIBUOPNFBTVSFNFOUTUBOEBSEFYJUT for obtaining trigger and clamp voltage levels. Trigger and clamp values will vary from one test setup to another. Due to the subnanosecond risetime of ESD and TLP waveforms, any parasitic inductance and capacitance in UIFUFTUTZTUFNXJMMBGGFDUNFBTVSFNFOUT"OZFGGFDUT due to inductance and capacitance need to be subtracted from the final measurement. It is important to remember that the test system will introduce a load across the ESD suppressor under test and this will also affect NFBTVSFNFOUT"IJHICBOEXJEUI0INPTDJMMPTDPQF and probes(>1Ghz) need to be used for obtaining best SFTVMUT"UUFOVBUJPOWBMVFTGPSUIFQSPCFUJQTIPVMECF at least 20X in order to obtain high input impedance for measurements. Specifications are subject to change without notice. I60 10% ESD transient testing, which is based on the IEC 61000-4-2 standard waveform, consists of subjecting a ESD suppressor to an subnanosecond risetime 8Kv transient generated by a commercial ESD simulator and recording trigger and clamp voltage levels. Clamp voltage level is obtained at 25ns. The basic ESD simulator circuit consists PGB3$EJTDIBSHFOFUXPSLXJUI3BOE$WBMVFTPG PINTBOEQJDPGBSBET8BWFGPSNTBSFDBQUVSFEVTJOHB 4 GHz oscilloscope(50 ohm input) with 20X resistive divider probes and a 30dB attenuator. Figures 1 and 2 show IEC current waveform and test setup. PGB2 Series I30 100 0 0 20 40 60 80 Time in nanoseconds Figure 4 TLP Scope Probe 1 30db Attenuator 50 Ohm Scope Input 2 950 46.93 46.93 + 500 DUT 3.165 50 - 5 Revised: March 8, 2011 www.littelfuse.com ©2011 Littelfuse