DF N1 01 0D -3 PESD5V0S2BQA Protection against high surge currents in ultra small DFN1010D-3 package 1 June 2016 Product data sheet 1. General description Two bidirectional ElectroStatic Discharge (ESD) protection diodes designed to protect two signal lines from the damage caused by ESD and other transients. The device is housed in a leadless ultra small DFN1010D-3 (SOT1215) Surface-Mounted Device (SMD) plastic package with visible and solderable side pads. 2. Features and benefits • • • • • • • Bidirectional ESD protection of two lines Ultra small SMD plastic package ESD protection up to 30 kV AEC-Q101 qualified IEC 61000-4-5 (surge): IPPM = 14 A IEC 61000-4-5 (surge): IPPM = 28 A combined lines Ultra low leakage current: IRM = 1 nA 3. Applications • • • • • Computers and peripherals Audio and video equipment Cellular handsets and accessories Communication systems Portable electronics 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VRWM reverse standoff voltage Tamb = 25 °C - - 5 V Cd diode capacitance f = 1 MHz; VR = 0 V; Tamb = 25 °C; single line - 35 45 pF [1] Measured from pin 1 or 2 to pin 3. [1] PESD5V0S2BQA NXP Semiconductors Protection against high surge currents in ultra small DFN1010D-3 package 5. Pinning information Table 2. Pinning information Pin Symbol Description 1 K1 cathode 2 K2 cathode 3 CC common cathode 4 CC common cathode Simplified outline Graphic symbol K1 1 CC K2 4 3 aaa-023266 2 Transparent top view DFN1010D-3 (SOT1215) 6. Ordering information Table 3. Ordering information Type number Package PESD5V0S2BQA Name Description Version DFN1010D-3 DFN1010D-3: plastic thermal enhanced ultra thin small outline package; no leads; 3 terminals; body 1.1 x 1.0 x 0.37 mm SOT1215 7. Marking Table 4. Marking codes Type number Marking code PESD5V0S2BQA 00 01 10 MARKING CODE (EXAMPLE) READING DIRECTION YEAR DATE CODE VENDOR CODE PIN 1 INDICATION MARK MARK-FREE AREA READING EXAMPLE: 11 01 10 aaa-008041 Fig. 1. DFN1010D-3 (SOT1215) binary marking code description PESD5V0S2BQA Product data sheet All information provided in this document is subject to legal disclaimers. 1 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 2 / 14 PESD5V0S2BQA NXP Semiconductors Protection against high surge currents in ultra small DFN1010D-3 package 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit IPPM peak pulse current tp = 8/20 µs; single line [1][2] - 14 A tp = 8/20 µs; combined lines [1][3] - 28 A tp = 8/20 µs; average measured; single line [1][2] - 17.5 A tp = 8/20 µs; average measured; combined [1][3] lines - 35 A Tj junction temperature - 150 °C Tamb ambient temperature -55 125 °C Tstg storage temperature -65 150 °C ESD maximum ratings VESD electrostatic discharge voltage contact discharge [4][2] - 30 kV air discharge [4][2] - 30 kV - 10 kV human body model (MIL-STD-883) [1] [2] [3] [4] Device stressed with non-repetitive current pulses (8/20 µs exponential decay waveform according to IEC 61000-4-5). Measured from pin 1 or 2 to pin 3. Measured from pin 1 and 2 to pin 3. Device stressed with ten non-repetitive ESD pulses. 001aaa631 001aaa630 120 IPP 100 % 100 % IPP; 8 µs IPP (%) 80 90 % e-t 50 % IPP; 20 µs 40 10 % 0 0 10 20 30 tp (µs) Fig. 2. 8/20 µs pulse waveform according to IEC 61000-4-5 PESD5V0S2BQA Product data sheet tr = 0.6 ns to 1 ns 40 t 30 ns 60 ns Fig. 3. ESD pulse waveform according to IEC 61000-4-2 All information provided in this document is subject to legal disclaimers. 1 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 3 / 14 PESD5V0S2BQA NXP Semiconductors Protection against high surge currents in ultra small DFN1010D-3 package 9. Characteristics Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit VRWM reverse standoff voltage Tamb = 25 °C - - 5 V VBR breakdown voltage IR = 5 mA; Tamb = 25 °C 5.5 7 9.5 V IRM reverse leakage current VR = 5 V; Tamb = 25 °C [1] - 1 50 nA Cd diode capacitance f = 1 MHz; VR = 0 V; Tamb = 25 °C; single line [1] - 35 45 pF f = 1 MHz; VR = 0 V; Tamb = 25 °C; combined lines [2] - 70 90 pF IPP = 1 A; Tamb = 25 °C; tp = 8/20 µs; single line [3][1] - 6.5 8.5 V IPPM = 14 A; Tamb = 25 °C; tp = 8/20 µs; single line [3][1] - - 11.5 V IPPM = 28 A; Tamb = 25 °C; tp = 8/20 µs; combined lines [4][2] - 11.5 - V IPPM = 16 A; Tamb = 25 °C; tp = TLP; single line [4][1] - 8.5 - V IPPM = 16 A; Tamb = 25 °C; tp = TLP; combined lines [4][2] - 7.6 - V IR = 10 A; Tamb = 25 °C; single line [4][1] - 0.12 - Ω IR = 10 A; Tamb = 25 °C; combined lines [4][2] - 0.07 - Ω VCL clamping voltage Rdyn [1] [2] [3] [4] dynamic resistance Measured from pin 1 or 2 to pin 3. Measured from pin 1 and 2 to pin 3. Device stressed with 8/20 μs exponential decay waveform according to IEC 61000-4-5. Non-repetitive current pulse, Transmission Line Pulse (TLP) tp = 100 ns; square pulse; ANSI / ESD STM5.5.1-2008. PESD5V0S2BQA Product data sheet All information provided in this document is subject to legal disclaimers. 1 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 4 / 14 PESD5V0S2BQA NXP Semiconductors Protection against high surge currents in ultra small DFN1010D-3 package IPP aaa-023194 102 IR (nA) 10 1 IR IRM - VCL - VBR - VRWM - IRM - IR VRWM VBR VCL 10-1 - + 10-2 - IPP 10-3 -75 006aaa676 Fig. 4. V-I characteristics for a bidirectional ESD protection diode 25 75 125 Tj (°C) 175 VRWM = 5 V Fig. 5. Relative variation of reverse leakage current as a function of ambient temperature; typical values aaa-023195 35 Cd (pF) 30 -25 aaa-023196 90 IPP (A) combined lines; Rdyn = 0.07 Ω 70 25 50 20 15 single line; Rdyn = 0.11 Ω 30 10 10 5 0 -5 -3 -1 1 3 VR (V) Single line; f = 1 MHz; VGS = 0 V; Tamb = 25 °C Fig. 6. Diode capacitance as a function of reverse voltage; typical values PESD5V0S2BQA Product data sheet -10 5 0 6 12 VCL (V) 18 tp = 100 ns; Transmission Line Pulse (TLP) Fig. 7. Dynamic resistance with positive clamping voltage; typical values All information provided in this document is subject to legal disclaimers. 1 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 5 / 14 PESD5V0S2BQA NXP Semiconductors Protection against high surge currents in ultra small DFN1010D-3 package aaa-023197 10 aaa-023198 12 IPP (A) VCL (V) -10 single line 8 -30 single line; Rdyn = 0.12 Ω combined lines combined lines; Rdyn = 0.05 Ω -50 4 -70 -90 -18 -12 -6 VCL (V) 0 0 tp = 100 ns; Transmission Line Pulse (TLP) Fig. 8. Dynamic resistance with negative clamping voltage; typical values 0 10 20 30 IPP (A) 40 tp = 8/20 µs; according to IEC 61000-4-5 Fig. 9. Dynamic resistance with positive clamping voltage; typical values aaa-023199 0 VCL (V) -4 -8 combined lines single line -12 -40 -30 -20 -10 IPP (A) 0 tp = 8/20 µs; according to IEC 61000-4-5 Fig. 10. Dynamic resistance with negative clamping voltage; typical values PESD5V0S2BQA Product data sheet All information provided in this document is subject to legal disclaimers. 1 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 6 / 14 PESD5V0S2BQA NXP Semiconductors Protection against high surge currents in ultra small DFN1010D-3 package ESD TESTER 4 GHz DIGITAL OSCILLOSCOPE RG 223/U 50 Ω coax Rd 40 dB ATTENUATOR Cs 50 Ω DUT (DEVICE UNDER TEST) IEC 61000-4-2 ed.2 Cs = 150 pF; Rd = 330 Ω 10 2 V (kV) 8 V (kV) 0 6 -2 4 -4 2 -6 0 -8 -2 -10 0 10 20 30 40 50 t (ns) 60 -10 -10 70 unclamped +8 kV ESD pulse waveform (IEC 61000-4-2 network) 0 10 20 30 40 50 t (ns) 60 70 unclamped -8 kV ESD pulse waveform (IEC 61000-4-2 network) aaa-003952 Fig. 11. ESD clamping test setup and waveforms aaa-023263 60 VCL (V) aaa-023264 60 VCL (V) 20 20 VCL at 30 ns = 6.7 V -20 -60 -10 VCL at 30 ns = -6 V -20 0 10 20 30 40 50 60 t (ns) Fig. 12. Clamped +8 kV pulse waveform (IEC 61000-4-2 network) PESD5V0S2BQA Product data sheet -60 -10 70 0 10 20 30 40 50 60 t (ns) 70 Fig. 13. Clamped -8 kV pulse waveform (IEC 61000-4-2 network) All information provided in this document is subject to legal disclaimers. 1 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 7 / 14 PESD5V0S2BQA NXP Semiconductors Protection against high surge currents in ultra small DFN1010D-3 package 10. Application information The device is designed for the protection of up to two bidirectional data lines from surge pulses and ESD damage. lines to be protected ESD protection diode GND 006aab332 Fig. 14. Application diagram Circuit board layout and protection device placement Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT) and surge transients. The following guidelines are recommended: 1. 2. 3. 4. 5. 6. 7. 8. Place the device as close to the input terminal or connector as possible. Minimize the path length between the device and the protected line. Keep parallel signal paths to a minimum. Avoid running protected conductors in parallel with unprotected conductors. Minimize all Printed-Circuit Board (PCB) conductive loops including power and ground loops. Minimize the length of the transient return path to ground. Avoid using shared transient return paths to a common ground point. Use ground planes whenever possible. For multilayer PCBs, use ground vias. 11. Test information Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is suitable for use in automotive applications. PESD5V0S2BQA Product data sheet All information provided in this document is subject to legal disclaimers. 1 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 8 / 14 PESD5V0S2BQA NXP Semiconductors Protection against high surge currents in ultra small DFN1010D-3 package 12. Package outline 0.87 0.95 0.75 1 0.95 1.05 0.22 0.30 2 0.16 0.24 0.1 3 0.04 max 0.34 0.40 Dimensions in mm 0.17 0.25 0.245 0.325 1.05 1.15 0.195 0.275 13-03-05 Fig. 15. Package outline DFN1010D-3 (SOT1215) PESD5V0S2BQA Product data sheet All information provided in this document is subject to legal disclaimers. 1 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 9 / 14 PESD5V0S2BQA NXP Semiconductors Protection against high surge currents in ultra small DFN1010D-3 package 13. Soldering Footprint information for reflow soldering of DFN1010D-3 package SOT1215 1.2 0.45 (2x) 0.3 1.1 0.35 (2x) 0.4 0.25 (2x) 0.75 0.3 0.5 1.5 1.4 0.4 0.5 0.4 0.3 0.5 1.3 0.4 0.3 0.4 0.5 1.3 solder land solder land plus solder paste occupied area solder resist Dimensions in mm Issue date 12-11-23 13-03-06 sot1215_fr Fig. 16. Reflow soldering footprint for DFN1010D-3 (SOT1215) PESD5V0S2BQA Product data sheet All information provided in this document is subject to legal disclaimers. 1 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 10 / 14 PESD5V0S2BQA NXP Semiconductors Protection against high surge currents in ultra small DFN1010D-3 package 14. Revision history Table 7. Revision history Data sheet ID Release date Data sheet status Change notice Supersedes PESD5V0S2BQA v.1 20160601 Product data sheet - - PESD5V0S2BQA Product data sheet All information provided in this document is subject to legal disclaimers. 1 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 11 / 14 PESD5V0S2BQA NXP Semiconductors Protection against high surge currents in ultra small DFN1010D-3 package Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. 15. Legal information Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Data sheet status Document status [1][2] Product status [3] Objective [short] data sheet Development This document contains data from the objective specification for product development. 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Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. All information provided in this document is subject to legal disclaimers. 1 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 12 / 14 PESD5V0S2BQA NXP Semiconductors Protection against high surge currents in ultra small DFN1010D-3 package Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Bitsound, CoolFlux, CoReUse, DESFire, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, MIFARE, MIFARE Plus, MIFARE Ultralight, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP Semiconductors N.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. PESD5V0S2BQA Product data sheet All information provided in this document is subject to legal disclaimers. 1 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 13 / 14 PESD5V0S2BQA NXP Semiconductors Protection against high surge currents in ultra small DFN1010D-3 package 16. Contents 1. General description......................................................1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Quick reference data....................................................1 5. Pinning information......................................................2 6. Ordering information....................................................2 7. Marking.......................................................................... 2 8. Limiting values............................................................. 3 9. Characteristics..............................................................4 10. Application information............................................. 8 11. Test information......................................................... 8 12. Package outline.......................................................... 9 13. Soldering................................................................... 10 14. Revision history........................................................11 15. Legal information..................................................... 12 © NXP Semiconductors N.V. 2016. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 1 June 2016 PESD5V0S2BQA Product data sheet All information provided in this document is subject to legal disclaimers. 1 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 14 / 14