cd00211034

AN2833
Application note
Dual step-down controller with auxiliary voltages
for industrial system power
Introduction
The PM6681A is a dual step-down controller with adjustable output voltages that can be
used in industrial power systems and this demonstration kit represents a typical application
circuit. The PM6681A demonstration kit allows testing all the device's functions and provides
two switching sections, with (typically) 3.3 V (OUT1) and 1.8 V (OUT2) outputs from 5.5 V to
36 V input voltage. The typical operating switching frequency of the two available sections is
200 kHz/300 kHz, respectively. Each switching section delivers more than 2.5 A output
current. An internal linear regulator provides a fixed 5 V output voltage. Another internal
linear regulator provides an adjustable output voltage (default 2.5 V). Both linear regulators
can deliver up to 100 mA peak current.
Figure 1.
PM6681A demonstration kit
AM01436v1
February 2009
Rev 2
1/32
www.st.com
Contents
AN2833
Contents
1
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Demonstration kit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5
Demonstration kit layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
I/O interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7
Recommended equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8
Quick start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
9
Jumper settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
10
Feedback output connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
11
Test setup and performance summary . . . . . . . . . . . . . . . . . . . . . . . . . 18
11.1
Test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
11.2
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
11.3
Soft-start and shutdown waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
11.4
3.3 V and 1.8 V output efficiency vs. load current . . . . . . . . . . . . . . . . . . 22
11.5
Power consumption analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
11.6
Switching frequency vs. load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
11.7
Linear regulator output voltages vs. output current . . . . . . . . . . . . . . . . . 26
11.8
Load transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
12
Representative waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/32
AN2833
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
PM6681A demonstration kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Demonstration kit schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PM6681A demonstration board layout - top layer (PGND plane and component side) . . . 10
PM6681A demonstration board layout - inner layer 1 (SGND layer and VIN plane) . . . . . 10
PM6681A demonstration board layout - inner layer 2 (SGND layer and signals). . . . . . . . 11
PM6681A demonstration board layout - bottom layer (PM6681A and component side) . . 11
Setup connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
REF, LDO5 and LDO power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Section 1 soft-start waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Section 2 soft-start waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Section 1 shutdown waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Section 2 shutdown waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3 V SMPS efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.8 V SMPS efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Input current vs. input voltage in PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Input current vs. input voltage in skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Input current vs. input voltage in non-audible skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Device current consumption vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Device current consumption vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3 V output switching frequency vs. load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.8 V output switching frequency vs. load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LDO5 output vs. load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ADJ_LDO load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SMPS 1.5 V load transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SMPS 1.05 V load transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SMPS pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SMPS non-audible skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SMPS PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3/32
Main features
1
4/32
AN2833
Main features
●
5.5 V to 36 V input voltage range
●
Adjustable output voltages
●
0.9 - 3.3 V adjustable LDO delivers 100 mA peak current
●
5 V LDO delivers 100 mA peak current
●
1.237 V ±1% reference voltage available
●
Lossless current sensing using low-side MOSFET RDS(ON)
●
Negative current limit
●
Soft-start internally fixed at 2 ms
●
Soft output discharge
●
Latched UVP
●
Non-latched OVP
●
Selectable pulse-skipping at light loads
●
Selectable minimum frequency (33 kHz) in pulse-skip mode
●
4 mW maximum quiescent power
●
Independent power-good signals
●
Output voltage ripple compensation
AN2833
2
Applications
Applications
●
Embedded computer systems
●
FPGA system power
●
Industrial applications at 24 V
●
High-performance and high-density DC/DC modules
5/32
Demonstration kit schematic
3
AN2833
Demonstration kit schematic
Figure 2.
Demonstration kit schematic
AM01437v1
6/32
AN2833
Component list
4
Component list
Table 1.
Bill of material
Qty Component
Description
Package
Part number
MFR
Value
Taiyo-Yuden
10 µF - 50 V
3
C1:C3
Ceramic
capacitor
1812
UMK325BJ106KM-T
1
C4
Ceramic
capacitor
1812
NM
2
C5, C6
Ceramic
capacitor
0805
100 nF – 50 V
1
C19
Ceramic
capacitor
0805
100 nF – 50 V
1
C7
POSCAP
capacitor
7343
NM
2
C9, C10
Ceramic
capacitor
0805
NM
1
C11
POSCAP
capacitor
7343
NM
Sanyo
1
C8
POSCAP
capacitor
7343
6TPE220M
Sanyo
220 µF –
25 mR – 6 V
1
C12
POSCAP
capacitor
7343
4TPE150MI
Sanyo
150 µF –
18 mR – 4 V
2
C13, C14
Ceramic
capacitor
0603
10 nF – 50 V
2
C15, C16
Ceramic
capacitor
0603
1.5 nF – 50 V
2
C17, C18
Ceramic
Capacitor
0603
47 pF – 50 V
1
C20
Ceramic
capacitor
0805
1 µF – 10 V
1
C21
Tantalum
capacitor
3216
4.7 µF – 16 V
1
C22
Ceramic
capacitor
0805
220 nF – 10 V
1
C23
Ceramic
capacitor
0805
10 pF
1
CIN
Electrolytic
capacitor
D = 10 mm
1
CREF
Ceramic
capacitor
0805
100 nF – 50 V
1
C26
Tantalum
capacitor
6032
4.7 µF – 35 V
10 µF - 50
Sanyo
NM
7/32
Component list
Table 1.
AN2833
Bill of material (continued)
Qty Component
Description
Package
Part number
MFR
Value
1
C24, C25
Tantalum
capacitor
0805
10 µF – 6.3 V
1
C27
Tantalum
capacitor
0805
10 µF – 6.3 V
1
C28
Tantalum
capacitor
3216
4.7 µF – 16 V
1
D1
Dual Schottky
diode
SOT23
BAS70
STMicroelectronics
2
D2, D3
Diode 1 A 40 V
DO216AA
STPS1L40M
STMicroelectronics
1
IC1
PM6681A
device
QFN-32
PM6681A
STMicroelectronics
1
L1
Inductor
10 mm x
10 mm
TPC 7440650047
Wurth
4.7 µH - 4.2 A
1
L2
Inductor
10 mm x
10 mm
TPC 7440650082
Wurth
8.2 µH 2.8 A
4
M1:M4
MOSFET
control FET
SO-8
STS12NH3LL
1
R3
Resistor
0805
22 kΩ - 1%
1
R4
Resistor
0805
36 kΩ - 1%
1
R5
Resistor
0805
3.3 kΩ - 1%
1
R6
Resistor
0805
3 kΩ - 1%
2
R7, R8
Resistor
0805
680 Ω - 1%
1
R9
Resistor
0805
47 Ω - 1%
2
R10, R11
Resistor
0805
10 Ω – 1%
4
R12:R15
Resistor
0805
100 kΩ – 1%
1
R16
Resistor
0805
150 kΩ – 1%
1
R17
Resistor
0805
560 kΩ – 1%
2
R18, R19
Resistor
0805
4
R20, R21,
R22, R23
Resistor
0805
0 Ω – 1%
1
R24
Resistor
0805
1.1 kΩ – 1%
1
R25
Resistor
0805
820 Ω – 1%
1
R26
Resistor
1206
3.9 Ω – 1%
1
R27
Resistor
0805
10 kΩ – 1%
1
R29
Resistor
0805
11 kΩ – 1%
1
R28
Resistor
0805
6.8 kΩ – 1%
1
R30
Resistor
0805
1.8 kΩ – 1%
8/32
NM
AN2833
Table 1.
Component list
Bill of material (continued)
Qty Component
Description
Package
Part number
MFR
Value
1
R31
Resistor
0603
8.2 kΩ – 1%
1
R32
Resistor
0603
15 kΩ – 1%
1
RLD5V,
RLD3V
Resistor
0805
NM
9/32
Demonstration kit layout
5
AN2833
Demonstration kit layout
Figure 3.
PM6681A demonstration board layout - top layer (PGND plane and
component side)
AM01438v1
Figure 4.
PM6681A demonstration board layout - inner layer 1 (SGND layer and VIN
plane)
AM01439v1
10/32
AN2833
Demonstration kit layout
Figure 5.
PM6681A demonstration board layout - inner layer 2 (SGND layer and
signals)
AM01440v1
Figure 6.
PM6681A demonstration board layout - bottom layer (PM6681A and
component side)
AM01441v1
11/32
I/O interface
6
AN2833
I/O interface
The demonstration board has the following test points given in Table 2.
Table 2.
12/32
Test points of the demonstration board
Test point
Description
VIN+
Input voltage
VIN-
Input voltage ground
LDO5
5 V linear regulator output
LDO_ADJ
Adjustable linear regulator output
EXT5V
5 V external input
OUT1+
OUT1 switching section output
OUT1-
OUT1 switching section output ground
PGOOD1
OUT1 switching section power-good
OUT2+
OUT2 switching section output
OUT2+
OUT2 switching section output ground
PGOOD2
OUT2 switching section power-good
J10
Junction pin between PGND and SGND planes
AN2833
7
Recommended equipment
Recommended equipment
●
5.5 V to 36 V power supply, notebook battery or AC adapter
●
Active loads
●
Digital multimeters
●
500 MHz four-trace oscilloscope
13/32
Quick start
8
14/32
AN2833
Quick start
1.
Connect VIN+ and VIN- test points of the demonstration board to an external power
supply
2.
Ensure that all switches of DIP-switch "S2" are "OFF". In this condition all outputs are
disabled (shutdown mode)
3.
Turn "S21" on (SHDN pin high). The LDO5 and LDO_ADJ outputs are turned on
(standby mode)
4.
Turn "S22" on (EN1 pin high). The 1.5 V switching controller brings its output in
regulation. PGood1 pin goes high after the soft-start
5.
Turn "S23" on (EN2 pin high). The 1.05 V switching controller brings its output in
regulation. PGood2 pin goes high after the soft-start
6.
In order to load the switching outputs, loads must be connected between the "+" and
the "-" output test points
7.
In order to load the LDO5 linear output, loads must be connected between J10 and
LDO5 or resistor RLD5V can be mounted on the demonstration board
8.
In order to load the LDO_ADJ linear output, loads must be connected between J10 and
LDO_ADJ or the alternative resistor R33 can be mounted on the demonstration board
AN2833
9
Jumper settings
Jumper settings
Different working conditions can be selected by using the jumpers.
Note:
Please note that the jumpers S1, S12 and S13 are already soldered on the demonstration
board and it is not necessary to change them. Refer to the schematic (Figure 2) to check
their correct connections.
●
External bypass connections for the linear regulator LDO5(V5SW)
Table 3.
Jumper S11 (connect V5SW pin to S11)
Position
OUT5V
SGND
EXT5V
●
LDO5 working conditions
When the main ouput voltage is greater than the boostrap-switchover
threshold, an internal 3 Ω (max) P-channel MOSFET switch connects the
V5SW pin to the LDO5 pin, shutting down the LDO5 internal linear
regulator. If not used, it must be tied to ground.
The internal linear regulator LDO5 is always on. In this case LDO5
supplies all gate drivers and the internal circuitry. It can provide an output
peak current of 100 mA.
The internal linear regulator LDO5 remains off if an alternative 5 V external
voltage is applied to the EXT5V test point. An internal 3 Ω (max) P-channel
MOSFET switch connects the V5SW pin to the LDO5 output. The gate
drivers and internal circuitry are supplied by the same 5 V external voltage
applied.
SMPS frequency selection (FSEL)
Table 4.
Jumper S3 (connect FSEL pin to S3)
Position
SMPS OUT1
SMPS OUT2
200 kHz
325 kHz
290 kHz
425 kHz
390 kHz
590 kHz
SGND
VREF
LDO5
15/32
Jumper settings
●
AN2833
SMPS-mode selection (skip)
Table 5.
Jumper S10 (connect skip pin to S10)
Position
GND
Switching operating mode
If the skip pin is tied to ground, a pulse-skip mode takes place at light
loads. A zero-crossing comparator prevents the inductor current from
going negative.
VREF
If the skip pin is tied to the VREF pin, the pulse-skip mode is enabled with
a minimum switching frequency of about 25 kHz (ultrasonic mode).
LDO5
If the skip pin is tied to 5 V, the fixed PWM mode is enabled. The switching
output is in a position to sink and source current from the load.
16/32
AN2833
10
Feedback output connections
Feedback output connections
●
Loop compensation network for very low output voltage ripple.
Table 6.
Jumper S4, S5
Position
Output ripple compensation
Short
Virtual ESR output ripple is generated by using a compensation network connected
between the output and the PHASE pin of the switching section.
Table 7.
Jumper S8, S9
Position
Feedback connection
Controller feedback signal connected to the compensation network
●
Loop compensation network for high output voltage ripple
Table 8.
Jumper S4, S5
Position
Output ripple compensation
Open
ESR output ripple is used.
Table 9.
Position
Jumper S8, S9
Feedback connection
Controller feedback signal connected directly to the output capacitor
17/32
Test setup and performance summary
AN2833
11
Test setup and performance summary
11.1
Test setup
The PM6681A demonstration board has the following input/output connections:
●
24 V input through J5 - J2 (VIN+ and VIN-)
●
3.3 V SMPS output through J4 - J13 (OUT1+ and OUT1-)
●
1.8 V SMPS output through J1 - J12 (OUT2+ and OUT2-)
●
2.5 V linear regulator output through LDO_ADJ - J10
●
5 V linear regulator output through LDO5 - J3 (LDO5)
A power supply capable of supplying at least 6 A should be connected to VIN+, VIN- and two
active loads should be connected respectively to OUT1+, OUT1- and OUT2+, OUT2-.
Figure 7.
Setup connections
Active load
Active load
5 V @:
2.5 V @:
50 mA cont
100 mA pk
50 mA cont
100 mA pk
Active load
Active load
3.3 V @ 5 A
1.8 V @ 5 A
DC supply 24 V
AM01442v1
18/32
AN2833
11.2
Test setup and performance summary
Power-up
As shown in Figure 8 power-up starts when the input voltage is applied and the voltage on
the SHDN pin is above the SHDN on threshold (1.5 V). First LDO5 goes up with a masking
time of about 4 ms. If the LDO5 output is above the UVLO threshold at this time, the device
enters standby mode and the adjustable internal linear regulator LDO is turned on.
Figure 8.
REF, LDO5 and LDO power-up
AM01443v1
11.3
Soft-start and shutdown waveforms
Figure 9, 10, 11 and 12 show respectively the soft-start and shutdown waveforms.
The PM681A has an independent internal digital soft-start for each switching section.
During the soft-start phase the internal current limit increases from 25% to 100% with steps
of 25% to avoid that the inductor current rises abruptly.
19/32
Test setup and performance summary
Figure 9.
AN2833
Section 1 soft-start waveforms
AM01444v1
Figure 10. Section 2 soft-start waveforms
AM01445v1
Driving the EN1, EN2 pins below the EN off threshold (0.8 V), the switching outputs are
connected to ground through an internal 12 Ω P-MOSFET and are discharged gradually,
(discharge mode). When the output voltages reach 0.3 V, the low-side MOSFETs are turned
on, quickly discharging them to ground.
20/32
AN2833
Test setup and performance summary
Figure 11. Section 1 shutdown waveforms
AM01446v1
Figure 12. Section 2 shutdown waveforms
AM01447v1
21/32
Test setup and performance summary
11.4
AN2833
3.3 V and 1.8 V output efficiency vs. load current
Figure 13 and 14 show the efficiency versus load current at 24 V of input voltage, in PWM
mode, skip mode and non-audible skip mode.
Figure 13. 3.3 V SMPS efficiency
/546EFFICIENCYVSLOADCURRENT
%FFICIENCY;=
,OADCURRENT;!=
!-V
Figure 14. 1.8 V SMPS efficiency
/546EFFICIENCYVSLOADCURRENT
%FFICIENCY;=
,OADCURRENT;!=
11.5
!-V
Power consumption analysis
To measure the device consumption in real working conditions, an external power supply of
+5 V is connected to EXT5V.
The two traces in the following figures show the differentiation in the two input currents.
Once the internal linear regulator is turned on, the device consumption increases.
22/32
AN2833
Test setup and performance summary
Figure 15 shows the input current consumption measured at VIN+ (includes ISHDN) and the
input device current consumption measured by the VCC pin. Both switching sections are
working in forced PWM mode. No load is applied on the outputs.
Figure 15. Input current vs. input voltage in PWM mode
07-NOLOADBATTERYCURRENT
VSINPUTVOLTAGE
)NPUTCURRENT;M!=
)INPUT
)%846
)NPUTVOLTAGE;6=
!-V
Figure 16 shows the input current consumption measured at VIN+, with both switching
sections working in pulse-skip mode. No load is applied on the outputs.
Figure 16. Input current vs. input voltage in skip mode
3+)0NOLOADBATTERYCURRENT
VSINPUTVOLTAGE
)NPUTCURRENT;M!=
)%846
)INPUT
)NPUTVOLTAGE;6=
!-V
Figure 17 shows the input current consumption measured at VIN+, with both switching
sections working in non-audible skip mode. No load is applied on the outputs.
23/32
Test setup and performance summary
AN2833
Figure 17. Input current vs. input voltage in non-audible skip mode
NONAUDIBLE3+)0NOLOADBATTERYCURRENT
VSINPUTVOLTAGE
)NPUTCURRENT;M!=
)INPUT
)%846
)NPUTVOLTAGE;6=
!-V
Figure 18 and 19 show the device current consumption measured in shutdown mode. In
shutdown mode and in standby mode all outputs are off (SHDN pin low). In standby mode
only the linear regulators output are on (V5SW = SGND; SHDN pin high; EN5, EN3 pins
low).
Figure 18. Device current consumption vs. input voltage
3HUTDOWNMODEINPUTBATTERYCURRENT
VSINPUTVOLTAGE
)NPUTCURRENT;U!=
)NPUTVOLTAGE;6=
24/32
!-V
AN2833
Test setup and performance summary
Figure 19. Device current consumption vs. input voltage
Standby mode input battery current
vs input voltage
380
Input current [uA]
360
340
320
300
280
260
240
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
Input voltage [V]
Switching frequency vs. load current
Figure 20 and 21 show the switching frequency variation with the load current in PWM
mode, skip mode and non-audible skip mode. 12 V is applied at VIN+ and VIN- test points.
Figure 20. 3.3 V output switching frequency vs. load current
OUT1=3.3 V switching frequency
250
SKIP @ 12 V
SKIP @ 24 V
200
SKIP @ 32 V
fsw [kHz]
11.6
AM01454v1
NO aud. SKIP @ 12 V
150
NO aud. SKIP @ 24 V
NO aud. SKIP @ 32 V
100
PWM @ 12 V
50
PWM @ 24 V
PWM @ 32 V
0
0.01
0.10
1.00
10.00
Load current [A]
AM01455v1
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Test setup and performance summary
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Figure 21. 1.8 V output switching frequency vs. load current
OUT2=1.8 V switching frequency
300
SKIP @ 12 V
250
SKIP @ 24 V
fsw [kHz]
200
SKIP @ 32 V
No aud. SKIP @ 12 V
150
No aud. SKIP @ 24 V
No aud. SKIP @ 32 V
100
PWM @ 12 V
50
PWM @ 24 V
PWM @ 32 V
0
0.01
0.10
1.00
10.00
Load current [A]
11.7
AM01456v1
Linear regulator output voltages vs. output current
Figure 22 and 23 show the load regulation respectively for the internal linear regulators
LDO5 and the adjustable linear regulator LDO_ADJ. Both switching sections are disabled.
12 V is applied at VIN+ and VIN- test points.
Figure 22. LDO5 output vs. load current
LDO5 vs. output current
4.9890
Linear output voltage [V]
4.9880
4.9870
4.9860
4.9850
4.9840
4.9830
4.9820
4.9810
4.9800
4.9790
0
10
20
30
40
50
60
Load current [mA]
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70
80
90
100
AM01457v1
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Test setup and performance summary
Figure 23. ADJ_LDO load regulation
ADJ_LDO vs. output current
2.5670
LDO output voltage [V]
2.5660
2.5650
2.5640
2.5630
2.5620
2.5610
2.5600
2.5590
2.5580
2.5570
0
10
20
30
40
50
60
70
80
90
100
Load current [mA]
AM01458v1
11.8
Load transient response
Figure 24 and 25 show the load transient response from 1 A to 4 A for both switching
outputs. In both cases the PM6681A works in forced PWM mode (the skip pin is high).
Figure 24. SMPS 1.5 V load transient response
OUT1
I_L
Vphase
AM01459v1
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Test setup and performance summary
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Figure 25. SMPS 1.05 V load transient response
OUT2
I_L
Vphase
AM01460v1
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12
Representative waveforms
Representative waveforms
Figure 26, 27, and 28 show the relevant waveforms of a switching section in different
working conditions: pulse-skip mode, non-audible skip mode, forced PWM mode.
Figure 26. SMPS pulse-skip mode
AM01600v1
Figure 27. SMPS non-audible skip mode
AM01601v1
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Representative waveforms
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Figure 28. SMPS PWM mode
AM01602v1
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13
Revision history
Revision history
Table 10.
Document revision history
Date
Revision
Changes
10-Feb-2009
1
Initial release
24-Feb-2009
2
Modified: Table 1 (value of component 31)
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